2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
37 reg = <0x00a01000 0x1000>,
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
68 dma_apbh: dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
71 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
72 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
78 gpmi: gpmi-nand@00112000 {
79 compatible = "fsl,imx6q-gpmi-nand";
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch";
92 fsl,gpmi-dma-channel = <0>;
97 compatible = "arm,cortex-a9-twd-timer";
98 reg = <0x00a00600 0x20>;
99 interrupts = <1 13 0xf01>;
102 L2: l2-cache@00a02000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x00a02000 0x1000>;
105 interrupts = <0 92 0x04>;
110 aips-bus@02000000 { /* AIPS1 */
111 compatible = "fsl,aips-bus", "simple-bus";
112 #address-cells = <1>;
114 reg = <0x02000000 0x100000>;
118 compatible = "fsl,spba-bus", "simple-bus";
119 #address-cells = <1>;
121 reg = <0x02000000 0x40000>;
124 spdif: spdif@02004000 {
125 reg = <0x02004000 0x4000>;
126 interrupts = <0 52 0x04>;
129 ecspi1: ecspi@02008000 {
130 #address-cells = <1>;
132 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
133 reg = <0x02008000 0x4000>;
134 interrupts = <0 31 0x04>;
135 clocks = <&clks 112>, <&clks 112>;
136 clock-names = "ipg", "per";
140 ecspi2: ecspi@0200c000 {
141 #address-cells = <1>;
143 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
144 reg = <0x0200c000 0x4000>;
145 interrupts = <0 32 0x04>;
146 clocks = <&clks 113>, <&clks 113>;
147 clock-names = "ipg", "per";
151 ecspi3: ecspi@02010000 {
152 #address-cells = <1>;
154 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
155 reg = <0x02010000 0x4000>;
156 interrupts = <0 33 0x04>;
157 clocks = <&clks 114>, <&clks 114>;
158 clock-names = "ipg", "per";
162 ecspi4: ecspi@02014000 {
163 #address-cells = <1>;
165 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
166 reg = <0x02014000 0x4000>;
167 interrupts = <0 34 0x04>;
168 clocks = <&clks 115>, <&clks 115>;
169 clock-names = "ipg", "per";
173 uart1: serial@02020000 {
174 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
175 reg = <0x02020000 0x4000>;
176 interrupts = <0 26 0x04>;
177 clocks = <&clks 160>, <&clks 161>;
178 clock-names = "ipg", "per";
182 esai: esai@02024000 {
183 reg = <0x02024000 0x4000>;
184 interrupts = <0 51 0x04>;
188 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
189 reg = <0x02028000 0x4000>;
190 interrupts = <0 46 0x04>;
191 clocks = <&clks 178>;
192 fsl,fifo-depth = <15>;
193 fsl,ssi-dma-events = <38 37>;
198 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
199 reg = <0x0202c000 0x4000>;
200 interrupts = <0 47 0x04>;
201 clocks = <&clks 179>;
202 fsl,fifo-depth = <15>;
203 fsl,ssi-dma-events = <42 41>;
208 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
209 reg = <0x02030000 0x4000>;
210 interrupts = <0 48 0x04>;
211 clocks = <&clks 180>;
212 fsl,fifo-depth = <15>;
213 fsl,ssi-dma-events = <46 45>;
217 asrc: asrc@02034000 {
218 reg = <0x02034000 0x4000>;
219 interrupts = <0 50 0x04>;
223 reg = <0x0203c000 0x4000>;
228 reg = <0x02040000 0x3c000>;
229 interrupts = <0 3 0x04 0 12 0x04>;
232 aipstz@0207c000 { /* AIPSTZ1 */
233 reg = <0x0207c000 0x4000>;
238 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
239 reg = <0x02080000 0x4000>;
240 interrupts = <0 83 0x04>;
241 clocks = <&clks 62>, <&clks 145>;
242 clock-names = "ipg", "per";
247 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
248 reg = <0x02084000 0x4000>;
249 interrupts = <0 84 0x04>;
250 clocks = <&clks 62>, <&clks 146>;
251 clock-names = "ipg", "per";
256 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
257 reg = <0x02088000 0x4000>;
258 interrupts = <0 85 0x04>;
259 clocks = <&clks 62>, <&clks 147>;
260 clock-names = "ipg", "per";
265 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
266 reg = <0x0208c000 0x4000>;
267 interrupts = <0 86 0x04>;
268 clocks = <&clks 62>, <&clks 148>;
269 clock-names = "ipg", "per";
272 can1: flexcan@02090000 {
273 reg = <0x02090000 0x4000>;
274 interrupts = <0 110 0x04>;
277 can2: flexcan@02094000 {
278 reg = <0x02094000 0x4000>;
279 interrupts = <0 111 0x04>;
283 compatible = "fsl,imx6q-gpt";
284 reg = <0x02098000 0x4000>;
285 interrupts = <0 55 0x04>;
288 gpio1: gpio@0209c000 {
289 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
290 reg = <0x0209c000 0x4000>;
291 interrupts = <0 66 0x04 0 67 0x04>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
298 gpio2: gpio@020a0000 {
299 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
300 reg = <0x020a0000 0x4000>;
301 interrupts = <0 68 0x04 0 69 0x04>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
308 gpio3: gpio@020a4000 {
309 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
310 reg = <0x020a4000 0x4000>;
311 interrupts = <0 70 0x04 0 71 0x04>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
318 gpio4: gpio@020a8000 {
319 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
320 reg = <0x020a8000 0x4000>;
321 interrupts = <0 72 0x04 0 73 0x04>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio5: gpio@020ac000 {
329 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
330 reg = <0x020ac000 0x4000>;
331 interrupts = <0 74 0x04 0 75 0x04>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
338 gpio6: gpio@020b0000 {
339 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
340 reg = <0x020b0000 0x4000>;
341 interrupts = <0 76 0x04 0 77 0x04>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 gpio7: gpio@020b4000 {
349 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
350 reg = <0x020b4000 0x4000>;
351 interrupts = <0 78 0x04 0 79 0x04>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
359 reg = <0x020b8000 0x4000>;
360 interrupts = <0 82 0x04>;
363 wdog1: wdog@020bc000 {
364 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
365 reg = <0x020bc000 0x4000>;
366 interrupts = <0 80 0x04>;
370 wdog2: wdog@020c0000 {
371 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
372 reg = <0x020c0000 0x4000>;
373 interrupts = <0 81 0x04>;
379 compatible = "fsl,imx6q-ccm";
380 reg = <0x020c4000 0x4000>;
381 interrupts = <0 87 0x04 0 88 0x04>;
385 anatop: anatop@020c8000 {
386 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
387 reg = <0x020c8000 0x1000>;
388 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
391 compatible = "fsl,anatop-regulator";
392 regulator-name = "vdd1p1";
393 regulator-min-microvolt = <800000>;
394 regulator-max-microvolt = <1375000>;
396 anatop-reg-offset = <0x110>;
397 anatop-vol-bit-shift = <8>;
398 anatop-vol-bit-width = <5>;
399 anatop-min-bit-val = <4>;
400 anatop-min-voltage = <800000>;
401 anatop-max-voltage = <1375000>;
405 compatible = "fsl,anatop-regulator";
406 regulator-name = "vdd3p0";
407 regulator-min-microvolt = <2800000>;
408 regulator-max-microvolt = <3150000>;
410 anatop-reg-offset = <0x120>;
411 anatop-vol-bit-shift = <8>;
412 anatop-vol-bit-width = <5>;
413 anatop-min-bit-val = <0>;
414 anatop-min-voltage = <2625000>;
415 anatop-max-voltage = <3400000>;
419 compatible = "fsl,anatop-regulator";
420 regulator-name = "vdd2p5";
421 regulator-min-microvolt = <2000000>;
422 regulator-max-microvolt = <2750000>;
424 anatop-reg-offset = <0x130>;
425 anatop-vol-bit-shift = <8>;
426 anatop-vol-bit-width = <5>;
427 anatop-min-bit-val = <0>;
428 anatop-min-voltage = <2000000>;
429 anatop-max-voltage = <2750000>;
432 reg_arm: regulator-vddcore@140 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "cpu";
435 regulator-min-microvolt = <725000>;
436 regulator-max-microvolt = <1450000>;
438 anatop-reg-offset = <0x140>;
439 anatop-vol-bit-shift = <0>;
440 anatop-vol-bit-width = <5>;
441 anatop-delay-reg-offset = <0x170>;
442 anatop-delay-bit-shift = <24>;
443 anatop-delay-bit-width = <2>;
444 anatop-min-bit-val = <1>;
445 anatop-min-voltage = <725000>;
446 anatop-max-voltage = <1450000>;
449 reg_pu: regulator-vddpu@140 {
450 compatible = "fsl,anatop-regulator";
451 regulator-name = "vddpu";
452 regulator-min-microvolt = <725000>;
453 regulator-max-microvolt = <1450000>;
455 anatop-reg-offset = <0x140>;
456 anatop-vol-bit-shift = <9>;
457 anatop-vol-bit-width = <5>;
458 anatop-delay-reg-offset = <0x170>;
459 anatop-delay-bit-shift = <26>;
460 anatop-delay-bit-width = <2>;
461 anatop-min-bit-val = <1>;
462 anatop-min-voltage = <725000>;
463 anatop-max-voltage = <1450000>;
466 reg_soc: regulator-vddsoc@140 {
467 compatible = "fsl,anatop-regulator";
468 regulator-name = "vddsoc";
469 regulator-min-microvolt = <725000>;
470 regulator-max-microvolt = <1450000>;
472 anatop-reg-offset = <0x140>;
473 anatop-vol-bit-shift = <18>;
474 anatop-vol-bit-width = <5>;
475 anatop-delay-reg-offset = <0x170>;
476 anatop-delay-bit-shift = <28>;
477 anatop-delay-bit-width = <2>;
478 anatop-min-bit-val = <1>;
479 anatop-min-voltage = <725000>;
480 anatop-max-voltage = <1450000>;
484 usbphy1: usbphy@020c9000 {
485 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
486 reg = <0x020c9000 0x1000>;
487 interrupts = <0 44 0x04>;
488 clocks = <&clks 182>;
491 usbphy2: usbphy@020ca000 {
492 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
493 reg = <0x020ca000 0x1000>;
494 interrupts = <0 45 0x04>;
495 clocks = <&clks 183>;
499 compatible = "fsl,sec-v4.0-mon", "simple-bus";
500 #address-cells = <1>;
502 ranges = <0 0x020cc000 0x4000>;
505 compatible = "fsl,sec-v4.0-mon-rtc-lp";
507 interrupts = <0 19 0x04 0 20 0x04>;
511 epit1: epit@020d0000 { /* EPIT1 */
512 reg = <0x020d0000 0x4000>;
513 interrupts = <0 56 0x04>;
516 epit2: epit@020d4000 { /* EPIT2 */
517 reg = <0x020d4000 0x4000>;
518 interrupts = <0 57 0x04>;
522 compatible = "fsl,imx6q-src";
523 reg = <0x020d8000 0x4000>;
524 interrupts = <0 91 0x04 0 96 0x04>;
528 compatible = "fsl,imx6q-gpc";
529 reg = <0x020dc000 0x4000>;
530 interrupts = <0 89 0x04 0 90 0x04>;
533 gpr: iomuxc-gpr@020e0000 {
534 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
535 reg = <0x020e0000 0x38>;
538 dcic1: dcic@020e4000 {
539 reg = <0x020e4000 0x4000>;
540 interrupts = <0 124 0x04>;
543 dcic2: dcic@020e8000 {
544 reg = <0x020e8000 0x4000>;
545 interrupts = <0 125 0x04>;
548 sdma: sdma@020ec000 {
549 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
550 reg = <0x020ec000 0x4000>;
551 interrupts = <0 2 0x04>;
552 clocks = <&clks 155>, <&clks 155>;
553 clock-names = "ipg", "ahb";
554 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
558 aips-bus@02100000 { /* AIPS2 */
559 compatible = "fsl,aips-bus", "simple-bus";
560 #address-cells = <1>;
562 reg = <0x02100000 0x100000>;
566 reg = <0x02100000 0x40000>;
567 interrupts = <0 105 0x04 0 106 0x04>;
570 aipstz@0217c000 { /* AIPSTZ2 */
571 reg = <0x0217c000 0x4000>;
574 usbotg: usb@02184000 {
575 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
576 reg = <0x02184000 0x200>;
577 interrupts = <0 43 0x04>;
578 clocks = <&clks 162>;
579 fsl,usbphy = <&usbphy1>;
580 fsl,usbmisc = <&usbmisc 0>;
584 usbh1: usb@02184200 {
585 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
586 reg = <0x02184200 0x200>;
587 interrupts = <0 40 0x04>;
588 clocks = <&clks 162>;
589 fsl,usbphy = <&usbphy2>;
590 fsl,usbmisc = <&usbmisc 1>;
594 usbh2: usb@02184400 {
595 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
596 reg = <0x02184400 0x200>;
597 interrupts = <0 41 0x04>;
598 clocks = <&clks 162>;
599 fsl,usbmisc = <&usbmisc 2>;
603 usbh3: usb@02184600 {
604 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
605 reg = <0x02184600 0x200>;
606 interrupts = <0 42 0x04>;
607 clocks = <&clks 162>;
608 fsl,usbmisc = <&usbmisc 3>;
612 usbmisc: usbmisc: usbmisc@02184800 {
614 compatible = "fsl,imx6q-usbmisc";
615 reg = <0x02184800 0x200>;
616 clocks = <&clks 162>;
619 fec: ethernet@02188000 {
620 compatible = "fsl,imx6q-fec";
621 reg = <0x02188000 0x4000>;
622 interrupts = <0 118 0x04 0 119 0x04>;
623 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
624 clock-names = "ipg", "ahb", "ptp";
629 reg = <0x0218c000 0x4000>;
630 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
633 usdhc1: usdhc@02190000 {
634 compatible = "fsl,imx6q-usdhc";
635 reg = <0x02190000 0x4000>;
636 interrupts = <0 22 0x04>;
637 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
638 clock-names = "ipg", "ahb", "per";
643 usdhc2: usdhc@02194000 {
644 compatible = "fsl,imx6q-usdhc";
645 reg = <0x02194000 0x4000>;
646 interrupts = <0 23 0x04>;
647 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
648 clock-names = "ipg", "ahb", "per";
653 usdhc3: usdhc@02198000 {
654 compatible = "fsl,imx6q-usdhc";
655 reg = <0x02198000 0x4000>;
656 interrupts = <0 24 0x04>;
657 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
658 clock-names = "ipg", "ahb", "per";
663 usdhc4: usdhc@0219c000 {
664 compatible = "fsl,imx6q-usdhc";
665 reg = <0x0219c000 0x4000>;
666 interrupts = <0 25 0x04>;
667 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
668 clock-names = "ipg", "ahb", "per";
674 #address-cells = <1>;
676 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
677 reg = <0x021a0000 0x4000>;
678 interrupts = <0 36 0x04>;
679 clocks = <&clks 125>;
684 #address-cells = <1>;
686 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
687 reg = <0x021a4000 0x4000>;
688 interrupts = <0 37 0x04>;
689 clocks = <&clks 126>;
694 #address-cells = <1>;
696 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
697 reg = <0x021a8000 0x4000>;
698 interrupts = <0 38 0x04>;
699 clocks = <&clks 127>;
704 reg = <0x021ac000 0x4000>;
707 mmdc0: mmdc@021b0000 { /* MMDC0 */
708 compatible = "fsl,imx6q-mmdc";
709 reg = <0x021b0000 0x4000>;
712 mmdc1: mmdc@021b4000 { /* MMDC1 */
713 reg = <0x021b4000 0x4000>;
717 reg = <0x021b8000 0x4000>;
718 interrupts = <0 14 0x04>;
722 compatible = "fsl,imx6q-ocotp";
723 reg = <0x021bc000 0x4000>;
727 reg = <0x021c0000 0x4000>;
728 interrupts = <0 21 0x04>;
731 tzasc@021d0000 { /* TZASC1 */
732 reg = <0x021d0000 0x4000>;
733 interrupts = <0 108 0x04>;
736 tzasc@021d4000 { /* TZASC2 */
737 reg = <0x021d4000 0x4000>;
738 interrupts = <0 109 0x04>;
741 audmux: audmux@021d8000 {
742 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
743 reg = <0x021d8000 0x4000>;
747 mipi@021dc000 { /* MIPI-CSI */
748 reg = <0x021dc000 0x4000>;
751 mipi@021e0000 { /* MIPI-DSI */
752 reg = <0x021e0000 0x4000>;
756 reg = <0x021e4000 0x4000>;
757 interrupts = <0 18 0x04>;
760 uart2: serial@021e8000 {
761 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
762 reg = <0x021e8000 0x4000>;
763 interrupts = <0 27 0x04>;
764 clocks = <&clks 160>, <&clks 161>;
765 clock-names = "ipg", "per";
769 uart3: serial@021ec000 {
770 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
771 reg = <0x021ec000 0x4000>;
772 interrupts = <0 28 0x04>;
773 clocks = <&clks 160>, <&clks 161>;
774 clock-names = "ipg", "per";
778 uart4: serial@021f0000 {
779 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
780 reg = <0x021f0000 0x4000>;
781 interrupts = <0 29 0x04>;
782 clocks = <&clks 160>, <&clks 161>;
783 clock-names = "ipg", "per";
787 uart5: serial@021f4000 {
788 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
789 reg = <0x021f4000 0x4000>;
790 interrupts = <0 30 0x04>;
791 clocks = <&clks 160>, <&clks 161>;
792 clock-names = "ipg", "per";
799 compatible = "fsl,imx6q-ipu";
800 reg = <0x02400000 0x400000>;
801 interrupts = <0 6 0x4 0 5 0x4>;
802 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
803 clock-names = "bus", "di0", "di1";