arch/arm/boot/dts/imx6sl-evk.dts

   1 /*
   2  * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sl.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloLite EVK Board";
  16         compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
  17
  18         battery: max8903@0 {
  19                 compatible = "fsl,max8903-charger";
  20                 pinctrl-names = "default";
  21                 dok_input = <&gpio4 13 1>;
  22                 uok_input = <&gpio4 13 1>;
  23                 chg_input = <&gpio4 15 1>;
  24                 flt_input = <&gpio4 14 1>;
  25                 fsl,dcm_always_high;
  26                 fsl,dc_valid;
  27                 fsl,adc_disable;
  28                 status = "okay";
  29         };
  30
  31         memory {
  32                 reg = <0x80000000 0x40000000>;
  33         };
  34
  35         regulators {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 reg_lcd_3v3: lcd-3v3 {
  41                         compatible = "regulator-fixed";
  42                         regulator-name = "lcd-3v3";
  43                         gpio = <&gpio4 3 0>;
  44                         enable-active-high;
  45                 };
  46
  47                 reg_usb_otg1_vbus: regulator@0 {
  48                         compatible = "regulator-fixed";
  49                         reg = <0>;
  50                         regulator-name = "usb_otg1_vbus";
  51                         regulator-min-microvolt = <5000000>;
  52                         regulator-max-microvolt = <5000000>;
  53                         gpio = <&gpio4 0 0>;
  54                         enable-active-high;
  55                 };
  56
  57                 reg_usb_otg2_vbus: regulator@1 {
  58                         compatible = "regulator-fixed";
  59                         reg = <1>;
  60                         regulator-name = "usb_otg2_vbus";
  61                         regulator-min-microvolt = <5000000>;
  62                         regulator-max-microvolt = <5000000>;
  63                         gpio = <&gpio4 2 0>;
  64                         enable-active-high;
  65                 };
  66
  67                 reg_aud3v: regulator@2 {
  68                         compatible = "regulator-fixed";
  69                         reg = <2>;
  70                         regulator-name = "wm8962-supply-3v15";
  71                         regulator-min-microvolt = <3150000>;
  72                         regulator-max-microvolt = <3150000>;
  73                         regulator-boot-on;
  74                 };
  75
  76                 reg_aud4v: regulator@3 {
  77                         compatible = "regulator-fixed";
  78                         reg = <3>;
  79                         regulator-name = "wm8962-supply-4v2";
  80                         regulator-min-microvolt = <4325000>;
  81                         regulator-max-microvolt = <4325000>;
  82                         regulator-boot-on;
  83                 };
  84         };
  85
  86         backlight {
  87                 compatible = "pwm-backlight";
  88                 pwms = <&pwm1 0 5000000>;
  89                 brightness-levels = <0 4 8 16 32 64 128 255>;
  90                 default-brightness-level = <6>;
  91         };
  92
  93         pxp_v4l2_out {
  94                 compatible = "fsl,imx6sl-pxp-v4l2";
  95                 status = "okay";
  96         };
  97
  98         sound {
  99                 compatible = "fsl,imx6q-sabresd-wm8962",
 100                            "fsl,imx-audio-wm8962";
 101                 model = "wm8962-audio";
 102                 cpu-dai = <&ssi2>;
 103                 audio-codec = <&codec>;
 104                 audio-routing =
 105                         "Headphone Jack", "HPOUTL",
 106                         "Headphone Jack", "HPOUTR",
 107                         "Ext Spk", "SPKOUTL",
 108                         "Ext Spk", "SPKOUTR",
 109                         "AMIC", "MICBIAS",
 110                         "IN3R", "AMIC";
 111                 amic-mono;
 112                 mux-int-port = <2>;
 113                 mux-ext-port = <3>;
 114                 hp-det-gpios = <&gpio4 19 1>;
 115         };
 116
 117         sound-spdif {
 118                 compatible = "fsl,imx-audio-spdif",
 119                            "fsl,imx6sl-evk-spdif";
 120                 model = "imx-spdif";
 121                 spdif-controller = <&spdif>;
 122                 spdif-out;
 123         };
 124 };
 125
 126 &audmux {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_audmux>;
 129         status = "okay";
 130 };
 131
 132 &clks {
 133         assigned-clocks = <&clks IMX6SL_PLL4_BYPASS_SRC>,
 134                           <&clks IMX6SL_PLL4_BYPASS>,
 135                           <&clks IMX6SL_CLK_EXTERN_AUDIO_SEL>,
 136                           <&clks IMX6SL_CLK_EXTERN_AUDIO>,
 137                           <&clks IMX6SL_CLK_PLL4_POST_DIV>;
 138         assigned-clock-parents = <&clks IMX6SL_CLK_OSC>,
 139                                 <&clks IMX6SL_PLL4_BYPASS_SRC>,
 140                                 <&clks IMX6SL_CLK_PLL4_AUDIO_DIV>;
 141         assigned-clock-rates = <0>, <0>, <0>, <24000000>,
 142                                 <24000000>;
 143 };
 144
 145 &csi {
 146         port {
 147                 csi_ep: endpoint {
 148                         remote-endpoint = <&ov5640_ep>;
 149                 };
 150         };
 151 };
 152
 153 &cpu0 {
 154         arm-supply = <&sw1a_reg>;
 155         soc-supply = <&sw1c_reg>;
 156 };
 157
 158 &ecspi1 {
 159         fsl,spi-num-chipselects = <1>;
 160         cs-gpios = <&gpio4 11 0>;
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_ecspi1>;
 163         status = "okay";
 164
 165         flash: m25p80@0 {
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 compatible = "st,m25p32";
 169                 spi-max-frequency = <20000000>;
 170                 reg = <0>;
 171         };
 172 };
 173
 174 &epdc {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_epdc_0>;
 177         V3P3-supply = <&V3P3_reg>;
 178         VCOM-supply = <&VCOM_reg>;
 179         DISPLAY-supply = <&DISPLAY_reg>;
 180         status = "okay";
 181 };
 182
 183 &fec {
 184         pinctrl-names = "default", "sleep";
 185         pinctrl-0 = <&pinctrl_fec>;
 186         pinctrl-1 = <&pinctrl_fec_sleep>;
 187         phy-mode = "rmii";
 188         status = "okay";
 189 };
 190
 191 &gpc {
 192         /* use ldo-bypass, u-boot will check it and configure */
 193         fsl,ldo-bypass = <1>;
 194         /* watchdog select of reset source */
 195         fsl,wdog-reset = <1>;
 196 };
 197
 198 &i2c1 {
 199         clock-frequency = <100000>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_i2c1>;
 202         status = "okay";
 203
 204         pmic: pfuze100@08 {
 205                 compatible = "fsl,pfuze100";
 206                 reg = <0x08>;
 207
 208                 regulators {
 209                         sw1a_reg: sw1ab {
 210                                 regulator-min-microvolt = <300000>;
 211                                 regulator-max-microvolt = <1875000>;
 212                                 regulator-boot-on;
 213                                 regulator-always-on;
 214                                 regulator-ramp-delay = <6250>;
 215                         };
 216
 217                         sw1c_reg: sw1c {
 218                                 regulator-min-microvolt = <300000>;
 219                                 regulator-max-microvolt = <1875000>;
 220                                 regulator-boot-on;
 221                                 regulator-always-on;
 222                                 regulator-ramp-delay = <6250>;
 223                         };
 224
 225                         sw2_reg: sw2 {
 226                                 regulator-min-microvolt = <800000>;
 227                                 regulator-max-microvolt = <3300000>;
 228                                 regulator-boot-on;
 229                                 regulator-always-on;
 230                         };
 231
 232                         sw3a_reg: sw3a {
 233                                 regulator-min-microvolt = <400000>;
 234                                 regulator-max-microvolt = <1975000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                         };
 238
 239                         sw3b_reg: sw3b {
 240                                 regulator-min-microvolt = <400000>;
 241                                 regulator-max-microvolt = <1975000>;
 242                                 regulator-boot-on;
 243                                 regulator-always-on;
 244                         };
 245
 246                         sw4_reg: sw4 {
 247                                 regulator-min-microvolt = <800000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                         };
 250
 251                         swbst_reg: swbst {
 252                                 regulator-min-microvolt = <5000000>;
 253                                 regulator-max-microvolt = <5150000>;
 254                         };
 255
 256                         snvs_reg: vsnvs {
 257                                 regulator-min-microvolt = <1000000>;
 258                                 regulator-max-microvolt = <3000000>;
 259                                 regulator-boot-on;
 260                                 regulator-always-on;
 261                         };
 262
 263                         vref_reg: vrefddr {
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                         };
 267
 268                         vgen1_reg: vgen1 {
 269                                 regulator-min-microvolt = <800000>;
 270                                 regulator-max-microvolt = <1550000>;
 271                                 regulator-always-on;
 272                         };
 273
 274                         vgen2_reg: vgen2 {
 275                                 regulator-min-microvolt = <800000>;
 276                                 regulator-max-microvolt = <1550000>;
 277                         };
 278
 279                         vgen3_reg: vgen3 {
 280                                 regulator-min-microvolt = <1800000>;
 281                                 regulator-max-microvolt = <3300000>;
 282                                 regulator-always-on;
 283                         };
 284
 285                         vgen4_reg: vgen4 {
 286                                 regulator-min-microvolt = <1800000>;
 287                                 regulator-max-microvolt = <3300000>;
 288                                 regulator-always-on;
 289                         };
 290
 291                         vgen5_reg: vgen5 {
 292                                 regulator-min-microvolt = <1800000>;
 293                                 regulator-max-microvolt = <3300000>;
 294                                 regulator-always-on;
 295                         };
 296
 297                         vgen6_reg: vgen6 {
 298                                 regulator-min-microvolt = <1800000>;
 299                                 regulator-max-microvolt = <3300000>;
 300                                 regulator-always-on;
 301                         };
 302                 };
 303         };
 304
 305         mma8450@1c {
 306                 compatible = "fsl,mma8450";
 307                 reg = <0x1c>;
 308         };
 309
 310         max17135@48 {
 311                 compatible = "maxim,max17135";
 312                 reg = <0x48>;
 313                 vneg_pwrup = <1>;
 314                 gvee_pwrup = <2>;
 315                 vpos_pwrup = <10>;
 316                 gvdd_pwrup = <12>;
 317                 gvdd_pwrdn = <1>;
 318                 vpos_pwrdn = <2>;
 319                 gvee_pwrdn = <8>;
 320                 vneg_pwrdn = <10>;
 321                 gpio_pmic_pwrgood = <&gpio2 13 0>;
 322                 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
 323                 gpio_pmic_wakeup = <&gpio2 14 0>;
 324                 gpio_pmic_v3p3 = <&gpio2 7 0>;
 325                 gpio_pmic_intr = <&gpio2 12 0>;
 326
 327                 regulators {
 328                         DISPLAY_reg: DISPLAY {
 329                                 regulator-name = "DISPLAY";
 330                         };
 331
 332                         GVDD_reg: GVDD {
 333                                 /* 20v */
 334                                 regulator-name = "GVDD";
 335                         };
 336
 337                         GVEE_reg: GVEE {
 338                                 /* -22v */
 339                                 regulator-name = "GVEE";
 340                         };
 341
 342                         HVINN_reg: HVINN {
 343                                 /* -22v */
 344                                 regulator-name = "HVINN";
 345                         };
 346
 347                         HVINP_reg: HVINP {
 348                                 /* 20v */
 349                                 regulator-name = "HVINP";
 350                         };
 351
 352                         VCOM_reg: VCOM {
 353                                 regulator-name = "VCOM";
 354                                 /* 2's-compliment, -4325000 */
 355                                 regulator-min-microvolt = <0xffbe0178>;
 356                                 /* 2's-compliment, -500000 */
 357                                 regulator-max-microvolt = <0xfff85ee0>;
 358                         };
 359
 360                         VNEG_reg: VNEG {
 361                                 /* -15v */
 362                                 regulator-name = "VNEG";
 363                         };
 364
 365                         VPOS_reg: VPOS {
 366                                 /* 15v */
 367                                 regulator-name = "VPOS";
 368                         };
 369
 370                         V3P3_reg: V3P3 {
 371                                 regulator-name = "V3P3";
 372                         };
 373                 };
 374         };
 375
 376 };
 377
 378 &i2c2 {
 379         clock-frequency = <100000>;
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_i2c2>;
 382         status = "okay";
 383
 384         codec: wm8962@1a {
 385                 compatible = "wlf,wm8962";
 386                 reg = <0x1a>;
 387                 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
 388                 DCVDD-supply = <&vgen3_reg>;
 389                 DBVDD-supply = <&reg_aud3v>;
 390                 AVDD-supply = <&vgen3_reg>;
 391                 CPVDD-supply = <&vgen3_reg>;
 392                 MICVDD-supply = <&reg_aud3v>;
 393                 PLLVDD-supply = <&vgen3_reg>;
 394                 SPKVDD1-supply = <&reg_aud4v>;
 395                 SPKVDD2-supply = <&reg_aud4v>;
 396                 amic-mono;
 397         };
 398
 399 };
 400
 401 &i2c3 {
 402         clock-frequency = <100000>;
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_i2c3>;
 405         status = "disabled";
 406
 407         ov5640: ov5640@3c {
 408                 compatible = "ovti,ov5640";
 409                 reg = <0x3c>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&pinctrl_csi_0>;
 412                 clocks = <&clks IMX6SL_CLK_CSI>;
 413                 clock-names = "csi_mclk";
 414                 AVDD-supply = <&vgen6_reg>;  /* 2.8v */
 415                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 416                 pwn-gpios = <&gpio1 25 1>;
 417                 rst-gpios = <&gpio1 26 0>;
 418                 csi_id = <0>;
 419                 mclk = <24000000>;
 420                 mclk_source = <0>;
 421                 port {
 422                         ov5640_ep: endpoint {
 423                                 remote-endpoint = <&csi_ep>;
 424                         };
 425                 };
 426         };
 427 };
 428
 429 &iomuxc {
 430         pinctrl-names = "default";
 431         pinctrl-0 = <&pinctrl_hog>;
 432
 433         imx6sl-evk {
 434                 pinctrl_hog: hoggrp {
 435                         fsl,pins = <
 436                                 MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
 437                                 MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
 438                                 MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
 439                                 MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
 440                                 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
 441                                 MX6SL_PAD_KEY_COL4__GPIO4_IO00  0x80000000
 442                                 MX6SL_PAD_KEY_COL5__GPIO4_IO02  0x80000000
 443                                 MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
 444                                 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
 445                                 MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
 446                                 MX6SL_PAD_FEC_RX_ER__GPIO4_IO19   0x1b0b0
 447                         >;
 448                 };
 449
 450                 pinctrl_audmux: audmuxgrp {
 451                         fsl,pins = <
 452                                 MX6SL_PAD_AUD_RXD__AUD3_RXD       0x4130b0
 453                                 MX6SL_PAD_AUD_TXC__AUD3_TXC       0x4130b0
 454                                 MX6SL_PAD_AUD_TXD__AUD3_TXD       0x4110b0
 455                                 MX6SL_PAD_AUD_TXFS__AUD3_TXFS     0x4130b0
 456                                 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
 457                         >;
 458                 };
 459
 460
 461                 pinctrl_ecspi1: ecspi1grp {
 462                         fsl,pins = <
 463                                 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO      0x100b1
 464                                 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI      0x100b1
 465                                 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK      0x100b1
 466                         >;
 467                 };
 468
 469                 pinctrl_epdc_0: epdcgrp-0 {
 470                         fsl,pins = <
 471                                 MX6SL_PAD_EPDC_D0__EPDC_DATA00  0x80000000
 472                                 MX6SL_PAD_EPDC_D1__EPDC_DATA01  0x80000000
 473                                 MX6SL_PAD_EPDC_D2__EPDC_DATA02  0x80000000
 474                                 MX6SL_PAD_EPDC_D3__EPDC_DATA03  0x80000000
 475                                 MX6SL_PAD_EPDC_D4__EPDC_DATA04  0x80000000
 476                                 MX6SL_PAD_EPDC_D5__EPDC_DATA05  0x80000000
 477                                 MX6SL_PAD_EPDC_D6__EPDC_DATA06  0x80000000
 478                                 MX6SL_PAD_EPDC_D7__EPDC_DATA07  0x80000000
 479                                 MX6SL_PAD_EPDC_D8__EPDC_DATA08  0x80000000
 480                                 MX6SL_PAD_EPDC_D9__EPDC_DATA09  0x80000000
 481                                 MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
 482                                 MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
 483                                 MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
 484                                 MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
 485                                 MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
 486                                 MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
 487                                 MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
 488                                 MX6SL_PAD_EPDC_GDSP__EPDC_GDSP   0x80000000
 489                                 MX6SL_PAD_EPDC_GDOE__EPDC_GDOE   0x80000000
 490                                 MX6SL_PAD_EPDC_GDRL__EPDC_GDRL   0x80000000
 491                                 MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
 492                                 MX6SL_PAD_EPDC_SDOE__EPDC_SDOE   0x80000000
 493                                 MX6SL_PAD_EPDC_SDLE__EPDC_SDLE   0x80000000
 494                                 MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
 495                                 MX6SL_PAD_EPDC_BDR0__EPDC_BDR0   0x80000000
 496                                 MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
 497                                 MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
 498                                 MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
 499                         >;
 500                 };
 501
 502                 pinctrl_fec: fecgrp {
 503                         fsl,pins = <
 504                                 MX6SL_PAD_FEC_MDC__FEC_MDC              0x1b0b0
 505                                 MX6SL_PAD_FEC_MDIO__FEC_MDIO            0x1b0b0
 506                                 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV         0x1b0b0
 507                                 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0        0x1b0b0
 508                                 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1        0x1b0b0
 509                                 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN          0x1b0b0
 510                                 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0        0x1b0b0
 511                                 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1        0x1b0b0
 512                                 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT      0x4001b0a8
 513                         >;
 514                 };
 515
 516                 pinctrl_fec_sleep: fecgrp-sleep {
 517                         fsl,pins = <
 518                                 MX6SL_PAD_FEC_MDC__GPIO4_IO23           0x3080
 519                                 MX6SL_PAD_FEC_MDIO__GPIO4_IO20          0x3080
 520                                 MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25        0x3080
 521                                 MX6SL_PAD_FEC_RXD0__GPIO4_IO17          0x3080
 522                                 MX6SL_PAD_FEC_RXD1__GPIO4_IO18          0x3080
 523                                 MX6SL_PAD_FEC_TX_EN__GPIO4_IO22         0x3080
 524                                 MX6SL_PAD_FEC_TXD0__GPIO4_IO24          0x3080
 525                                 MX6SL_PAD_FEC_TXD1__GPIO4_IO16          0x3080
 526                                 MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26       0x3080
 527                         >;
 528                 };
 529
 530                 pinctrl_i2c1: i2c1grp {
 531                         fsl,pins = <
 532                                 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
 533                                 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
 534                         >;
 535                 };
 536
 537                 pinctrl_i2c2: i2c2grp {
 538                         fsl,pins = <
 539                                 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
 540                                 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
 541                         >;
 542                 };
 543
 544                 pinctrl_i2c3: i2c3grp {
 545                         fsl,pins = <
 546                                 MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
 547                                 MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
 548                         >;
 549                 };
 550
 551                 pinctrl_kpp: kppgrp {
 552                         fsl,pins = <
 553                                 MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
 554                                 MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
 555                                 MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
 556                                 MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
 557                                 MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
 558                                 MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
 559                         >;
 560                 };
 561
 562                 pinctrl_lcdif_dat: lcdifdatgrp {
 563                         fsl,pins = <
 564                                 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
 565                                 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
 566                                 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
 567                                 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
 568                                 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
 569                                 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
 570                                 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
 571                                 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
 572                                 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
 573                                 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
 574                                 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
 575                                 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
 576                                 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
 577                                 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
 578                                 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
 579                                 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
 580                                 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
 581                                 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
 582                                 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
 583                                 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
 584                                 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
 585                                 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
 586                                 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
 587                                 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
 588                         >;
 589                 };
 590
 591                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 592                         fsl,pins = <
 593                                 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
 594                                 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
 595                                 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
 596                                 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
 597                         >;
 598                 };
 599
 600                 pinctrl_pwm1: pwm1grp {
 601                         fsl,pins = <
 602                                 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
 603                         >;
 604                 };
 605
 606                 pinctrl_pwm1_sleep: pwm1grp-sleep {
 607                         fsl,pins = <
 608                                 MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
 609                         >;
 610                 };
 611
 612                 pinctrl_spdif: spdifgrp {
 613                         fsl,pins = <
 614                                 MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
 615                         >;
 616                 };
 617
 618                 pinctrl_uart1: uart1grp {
 619                         fsl,pins = <
 620                                 MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x1b0b1
 621                                 MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x1b0b1
 622                         >;
 623                 };
 624
 625                 pinctrl_uart4_1: uart4grp-1 {
 626                         fsl,pins = <
 627                                 MX6SL_PAD_SD1_DAT4__UART4_RX_DATA       0x1b0b1
 628                                 MX6SL_PAD_SD1_DAT5__UART4_TX_DATA       0x1b0b1
 629                                 MX6SL_PAD_SD1_DAT7__UART4_CTS_B         0x1b0b1
 630                                 MX6SL_PAD_SD1_DAT6__UART4_RTS_B         0x1b0b1
 631                         >;
 632                 };
 633
 634                 pinctrl_uart4dte_1: uart4dtegrp-1 {
 635                         fsl,pins = <
 636                                 MX6SL_PAD_SD1_DAT5__UART4_RX_DATA       0x1b0b1
 637                                 MX6SL_PAD_SD1_DAT4__UART4_TX_DATA       0x1b0b1
 638                                 MX6SL_PAD_SD1_DAT6__UART4_CTS_B         0x1b0b1
 639                                 MX6SL_PAD_SD1_DAT7__UART4_RTS_B         0x1b0b1
 640                         >;
 641                 };
 642
 643                 pinctrl_usbotg1: usbotg1grp {
 644                         fsl,pins = <
 645                                 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID      0x17059
 646                         >;
 647                 };
 648
 649                 pinctrl_usdhc1: usdhc1grp {
 650                         fsl,pins = <
 651                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x17059
 652                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x10059
 653                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x17059
 654                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x17059
 655                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x17059
 656                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x17059
 657                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x17059
 658                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x17059
 659                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x17059
 660                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x17059
 661                         >;
 662                 };
 663
 664                 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 665                         fsl,pins = <
 666                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x170b9
 667                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x100b9
 668                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170b9
 669                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170b9
 670                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170b9
 671                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170b9
 672                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170b9
 673                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170b9
 674                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170b9
 675                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170b9
 676                         >;
 677                 };
 678
 679                 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 680                         fsl,pins = <
 681                                 MX6SL_PAD_SD1_CMD__SD1_CMD              0x170f9
 682                                 MX6SL_PAD_SD1_CLK__SD1_CLK              0x100f9
 683                                 MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170f9
 684                                 MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170f9
 685                                 MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170f9
 686                                 MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170f9
 687                                 MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170f9
 688                                 MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170f9
 689                                 MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170f9
 690                                 MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170f9
 691                         >;
 692                 };
 693
 694                 pinctrl_usdhc2: usdhc2grp {
 695                         fsl,pins = <
 696                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x17059
 697                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x10059
 698                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x17059
 699                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x17059
 700                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x17059
 701                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x17059
 702                         >;
 703                 };
 704
 705                 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 706                         fsl,pins = <
 707                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x170b9
 708                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x100b9
 709                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170b9
 710                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170b9
 711                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170b9
 712                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170b9
 713                         >;
 714                 };
 715
 716                 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 717                         fsl,pins = <
 718                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x170f9
 719                                 MX6SL_PAD_SD2_CLK__SD2_CLK              0x100f9
 720                                 MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170f9
 721                                 MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170f9
 722                                 MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170f9
 723                                 MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170f9
 724                         >;
 725                 };
 726
 727                 pinctrl_usdhc3: usdhc3grp {
 728                         fsl,pins = <
 729                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x17059
 730                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x10059
 731                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x17059
 732                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x17059
 733                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x17059
 734                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x17059
 735                         >;
 736                 };
 737
 738                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 739                         fsl,pins = <
 740                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x170b9
 741                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x100b9
 742                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170b9
 743                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170b9
 744                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170b9
 745                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170b9
 746                         >;
 747                 };
 748
 749                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 750                         fsl,pins = <
 751                                 MX6SL_PAD_SD3_CMD__SD3_CMD              0x170f9
 752                                 MX6SL_PAD_SD3_CLK__SD3_CLK              0x100f9
 753                                 MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170f9
 754                                 MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170f9
 755                                 MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170f9
 756                                 MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170f9
 757                         >;
 758                 };
 759
 760                 pinctrl_csi_0: csigrp-0 {
 761                         fsl,pins = <
 762                                 MX6SL_PAD_EPDC_GDRL__CSI_MCLK   0x110b0
 763                                 MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
 764                                 MX6SL_PAD_EPDC_GDSP__CSI_VSYNC  0x110b0
 765                                 MX6SL_PAD_EPDC_GDOE__CSI_HSYNC  0x110b0
 766                                 MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
 767                                 MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
 768                                 MX6SL_PAD_EPDC_D7__CSI_DATA07   0x110b0
 769                                 MX6SL_PAD_EPDC_D6__CSI_DATA06   0x110b0
 770                                 MX6SL_PAD_EPDC_D5__CSI_DATA05   0x110b0
 771                                 MX6SL_PAD_EPDC_D4__CSI_DATA04   0x110b0
 772                                 MX6SL_PAD_EPDC_D3__CSI_DATA03   0x110b0
 773                                 MX6SL_PAD_EPDC_D2__CSI_DATA02   0x110b0
 774                                 MX6SL_PAD_EPDC_D1__CSI_DATA01   0x110b0
 775                                 MX6SL_PAD_EPDC_D0__CSI_DATA00   0x110b0
 776                                 MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
 777                                 MX6SL_PAD_EPDC_SDOE__GPIO1_IO25  0x80000000
 778                         >;
 779                 };
 780         };
 781 };
 782
 783 &pxp {
 784         status = "okay";
 785 };
 786
 787 &kpp {
 788         pinctrl-names = "default";
 789         pinctrl-0 = <&pinctrl_kpp>;
 790         linux,keymap = <
 791                         MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
 792                         MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
 793                         MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
 794                         MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
 795                         MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
 796                         MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
 797                         MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
 798                         MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
 799         >;
 800         status = "okay";
 801 };
 802
 803 &lcdif {
 804         pinctrl-names = "default";
 805         pinctrl-0 = <&pinctrl_lcdif_dat
 806                      &pinctrl_lcdif_ctrl>;
 807         lcd-supply = <&reg_lcd_3v3>;
 808         display = <&display>;
 809         status = "okay";
 810
 811         display: display {
 812                 bits-per-pixel = <16>;
 813                 bus-width = <24>;
 814
 815                 display-timings {
 816                         native-mode = <&timing0>;
 817                         timing0: timing0 {
 818                                 clock-frequency = <33500000>;
 819                                 hactive = <800>;
 820                                 vactive = <480>;
 821                                 hback-porch = <89>;
 822                                 hfront-porch = <164>;
 823                                 vback-porch = <23>;
 824                                 vfront-porch = <10>;
 825                                 hsync-len = <10>;
 826                                 vsync-len = <10>;
 827                                 hsync-active = <0>;
 828                                 vsync-active = <0>;
 829                                 de-active = <1>;
 830                                 pixelclk-active = <0>;
 831                         };
 832                 };
 833         };
 834 };
 835
 836 &pwm1 {
 837         pinctrl-names = "default", "sleep";
 838         pinctrl-0 = <&pinctrl_pwm1>;
 839         pinctrl-1 = <&pinctrl_pwm1_sleep>;
 840         status = "okay";
 841 };
 842
 843 &spdif {
 844         pinctrl-names = "default";
 845         pinctrl-0 = <&pinctrl_spdif>;
 846         assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>,
 847                           <&clks IMX6SL_CLK_SPDIF0_PODF>;
 848         assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>;
 849         assigned-clock-rates = <0>, <227368421>;
 850         status = "okay";
 851 };
 852
 853 &ssi2 {
 854         fsl,mode = "i2s-slave";
 855         assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>,
 856                           <&clks IMX6SL_CLK_SSI2>;
 857         assigned-clock-rates = <0>, <24000000>;
 858         status = "okay";
 859 };
 860
 861 &uart1 {
 862         pinctrl-names = "default";
 863         pinctrl-0 = <&pinctrl_uart1>;
 864         status = "okay";
 865 };
 866
 867 &usbotg1 {
 868         vbus-supply = <&reg_usb_otg1_vbus>;
 869         pinctrl-names = "default";
 870         pinctrl-0 = <&pinctrl_usbotg1>;
 871         disable-over-current;
 872         status = "okay";
 873 };
 874
 875 &usbotg2 {
 876         vbus-supply = <&reg_usb_otg2_vbus>;
 877         dr_mode = "host";
 878         disable-over-current;
 879         status = "okay";
 880 };
 881
 882 &usdhc1 {
 883         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 884         pinctrl-0 = <&pinctrl_usdhc1>;
 885         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 886         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 887         bus-width = <8>;
 888         cd-gpios = <&gpio4 7 0>;
 889         wp-gpios = <&gpio4 6 0>;
 890         keep-power-in-suspend;
 891         enable-sdio-wakeup;
 892         status = "okay";
 893 };
 894
 895 &usdhc2 {
 896         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 897         pinctrl-0 = <&pinctrl_usdhc2>;
 898         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 899         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 900         cd-gpios = <&gpio5 0 0>;
 901         wp-gpios = <&gpio4 29 0>;
 902         keep-power-in-suspend;
 903         enable-sdio-wakeup;
 904         status = "okay";
 905 };
 906
 907 &usdhc3 {
 908         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 909         pinctrl-0 = <&pinctrl_usdhc3>;
 910         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 911         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 912         cd-gpios = <&gpio3 22 0>;
 913         keep-power-in-suspend;
 914         enable-sdio-wakeup;
 915         status = "okay";
 916 };