arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "skeleton.dtsi"
  12 #include "imx6sl-pinfunc.h"
  13 #include <dt-bindings/clock/imx6sl-clock.h>
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 serial0 = &uart1;
  23                 serial1 = &uart2;
  24                 serial2 = &uart3;
  25                 serial3 = &uart4;
  26                 serial4 = &uart5;
  27                 spi0 = &ecspi1;
  28                 spi1 = &ecspi2;
  29                 spi2 = &ecspi3;
  30                 spi3 = &ecspi4;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         next-level-cache = <&L2>;
  42                         operating-points = <
  43                                 /* kHz    uV */
  44                                 996000  1275000
  45                                 792000  1175000
  46                                 396000  975000
  47                         >;
  48                         fsl,soc-operating-points = <
  49                                 /* ARM kHz      SOC-PU uV */
  50                                 996000          1225000
  51                                 792000          1175000
  52                                 396000          1175000
  53                         >;
  54                         clock-latency = <61036>; /* two CLK32 periods */
  55                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  56                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  57                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  58                         clock-names = "arm", "pll2_pfd2_396m", "step",
  59                                       "pll1_sw", "pll1_sys";
  60                         arm-supply = <&reg_arm>;
  61                         pu-supply = <&reg_pu>;
  62                         soc-supply = <&reg_soc>;
  63                 };
  64         };
  65
  66         intc: interrupt-controller@00a01000 {
  67                 compatible = "arm,cortex-a9-gic";
  68                 #interrupt-cells = <3>;
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 interrupt-controller;
  72                 reg = <0x00a01000 0x1000>,
  73                       <0x00a00100 0x100>;
  74         };
  75
  76         clocks {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 ckil {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                 };
  84
  85                 osc {
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <24000000>;
  88                 };
  89         };
  90
  91         soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 compatible = "simple-bus";
  95                 interrupt-parent = <&intc>;
  96                 ranges;
  97
  98                 ocram: sram@00900000 {
  99                         compatible = "mmio-sram";
 100                         reg = <0x00900000 0x20000>;
 101                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 102                 };
 103
 104                 L2: l2-cache@00a02000 {
 105                         compatible = "arm,pl310-cache";
 106                         reg = <0x00a02000 0x1000>;
 107                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 108                         cache-unified;
 109                         cache-level = <2>;
 110                         arm,tag-latency = <4 2 3>;
 111                         arm,data-latency = <4 2 3>;
 112                 };
 113
 114                 pmu {
 115                         compatible = "arm,cortex-a9-pmu";
 116                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 117                 };
 118
 119                 aips1: aips-bus@02000000 {
 120                         compatible = "fsl,aips-bus", "simple-bus";
 121                         #address-cells = <1>;
 122                         #size-cells = <1>;
 123                         reg = <0x02000000 0x100000>;
 124                         ranges;
 125
 126                         spba: spba-bus@02000000 {
 127                                 compatible = "fsl,spba-bus", "simple-bus";
 128                                 #address-cells = <1>;
 129                                 #size-cells = <1>;
 130                                 reg = <0x02000000 0x40000>;
 131                                 ranges;
 132
 133                                 spdif: spdif@02004000 {
 134                                         reg = <0x02004000 0x4000>;
 135                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 136                                 };
 137
 138                                 ecspi1: ecspi@02008000 {
 139                                         #address-cells = <1>;
 140                                         #size-cells = <0>;
 141                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 142                                         reg = <0x02008000 0x4000>;
 143                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 144                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 145                                                  <&clks IMX6SL_CLK_ECSPI1>;
 146                                         clock-names = "ipg", "per";
 147                                         status = "disabled";
 148                                 };
 149
 150                                 ecspi2: ecspi@0200c000 {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x0200c000 0x4000>;
 155                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 156                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 157                                                  <&clks IMX6SL_CLK_ECSPI2>;
 158                                         clock-names = "ipg", "per";
 159                                         status = "disabled";
 160                                 };
 161
 162                                 ecspi3: ecspi@02010000 {
 163                                         #address-cells = <1>;
 164                                         #size-cells = <0>;
 165                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 166                                         reg = <0x02010000 0x4000>;
 167                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 168                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 169                                                  <&clks IMX6SL_CLK_ECSPI3>;
 170                                         clock-names = "ipg", "per";
 171                                         status = "disabled";
 172                                 };
 173
 174                                 ecspi4: ecspi@02014000 {
 175                                         #address-cells = <1>;
 176                                         #size-cells = <0>;
 177                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 178                                         reg = <0x02014000 0x4000>;
 179                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 180                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 181                                                  <&clks IMX6SL_CLK_ECSPI4>;
 182                                         clock-names = "ipg", "per";
 183                                         status = "disabled";
 184                                 };
 185
 186                                 uart5: serial@02018000 {
 187                                         compatible = "fsl,imx6sl-uart",
 188                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 189                                         reg = <0x02018000 0x4000>;
 190                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 191                                         clocks = <&clks IMX6SL_CLK_UART>,
 192                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 193                                         clock-names = "ipg", "per";
 194                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 195                                         dma-names = "rx", "tx";
 196                                         status = "disabled";
 197                                 };
 198
 199                                 uart1: serial@02020000 {
 200                                         compatible = "fsl,imx6sl-uart",
 201                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 202                                         reg = <0x02020000 0x4000>;
 203                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 204                                         clocks = <&clks IMX6SL_CLK_UART>,
 205                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 206                                         clock-names = "ipg", "per";
 207                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 208                                         dma-names = "rx", "tx";
 209                                         status = "disabled";
 210                                 };
 211
 212                                 uart2: serial@02024000 {
 213                                         compatible = "fsl,imx6sl-uart",
 214                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 215                                         reg = <0x02024000 0x4000>;
 216                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 217                                         clocks = <&clks IMX6SL_CLK_UART>,
 218                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 219                                         clock-names = "ipg", "per";
 220                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 221                                         dma-names = "rx", "tx";
 222                                         status = "disabled";
 223                                 };
 224
 225                                 ssi1: ssi@02028000 {
 226                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 227                                         reg = <0x02028000 0x4000>;
 228                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 229                                         clocks = <&clks IMX6SL_CLK_SSI1>;
 230                                         dmas = <&sdma 37 1 0>,
 231                                                <&sdma 38 1 0>;
 232                                         dma-names = "rx", "tx";
 233                                         fsl,fifo-depth = <15>;
 234                                         status = "disabled";
 235                                 };
 236
 237                                 ssi2: ssi@0202c000 {
 238                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 239                                         reg = <0x0202c000 0x4000>;
 240                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks IMX6SL_CLK_SSI2>;
 242                                         dmas = <&sdma 41 1 0>,
 243                                                <&sdma 42 1 0>;
 244                                         dma-names = "rx", "tx";
 245                                         fsl,fifo-depth = <15>;
 246                                         status = "disabled";
 247                                 };
 248
 249                                 ssi3: ssi@02030000 {
 250                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 251                                         reg = <0x02030000 0x4000>;
 252                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks IMX6SL_CLK_SSI3>;
 254                                         dmas = <&sdma 45 1 0>,
 255                                                <&sdma 46 1 0>;
 256                                         dma-names = "rx", "tx";
 257                                         fsl,fifo-depth = <15>;
 258                                         status = "disabled";
 259                                 };
 260
 261                                 uart3: serial@02034000 {
 262                                         compatible = "fsl,imx6sl-uart",
 263                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 264                                         reg = <0x02034000 0x4000>;
 265                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6SL_CLK_UART>,
 267                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 270                                         dma-names = "rx", "tx";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 uart4: serial@02038000 {
 275                                         compatible = "fsl,imx6sl-uart",
 276                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 277                                         reg = <0x02038000 0x4000>;
 278                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6SL_CLK_UART>,
 280                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 281                                         clock-names = "ipg", "per";
 282                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 283                                         dma-names = "rx", "tx";
 284                                         status = "disabled";
 285                                 };
 286                         };
 287
 288                         pwm1: pwm@02080000 {
 289                                 #pwm-cells = <2>;
 290                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 291                                 reg = <0x02080000 0x4000>;
 292                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 293                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 294                                          <&clks IMX6SL_CLK_PWM1>;
 295                                 clock-names = "ipg", "per";
 296                         };
 297
 298                         pwm2: pwm@02084000 {
 299                                 #pwm-cells = <2>;
 300                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 301                                 reg = <0x02084000 0x4000>;
 302                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 303                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 304                                          <&clks IMX6SL_CLK_PWM2>;
 305                                 clock-names = "ipg", "per";
 306                         };
 307
 308                         pwm3: pwm@02088000 {
 309                                 #pwm-cells = <2>;
 310                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 311                                 reg = <0x02088000 0x4000>;
 312                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 313                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 314                                          <&clks IMX6SL_CLK_PWM3>;
 315                                 clock-names = "ipg", "per";
 316                         };
 317
 318                         pwm4: pwm@0208c000 {
 319                                 #pwm-cells = <2>;
 320                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 321                                 reg = <0x0208c000 0x4000>;
 322                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 324                                          <&clks IMX6SL_CLK_PWM4>;
 325                                 clock-names = "ipg", "per";
 326                         };
 327
 328                         gpt: gpt@02098000 {
 329                                 compatible = "fsl,imx6sl-gpt";
 330                                 reg = <0x02098000 0x4000>;
 331                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 332                                 clocks = <&clks IMX6SL_CLK_GPT>,
 333                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 334                                 clock-names = "ipg", "per";
 335                         };
 336
 337                         gpio1: gpio@0209c000 {
 338                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x0209c000 0x4000>;
 340                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 341                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <2>;
 344                                 interrupt-controller;
 345                                 #interrupt-cells = <2>;
 346                         };
 347
 348                         gpio2: gpio@020a0000 {
 349                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 350                                 reg = <0x020a0000 0x4000>;
 351                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 352                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 353                                 gpio-controller;
 354                                 #gpio-cells = <2>;
 355                                 interrupt-controller;
 356                                 #interrupt-cells = <2>;
 357                         };
 358
 359                         gpio3: gpio@020a4000 {
 360                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 361                                 reg = <0x020a4000 0x4000>;
 362                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 363                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 364                                 gpio-controller;
 365                                 #gpio-cells = <2>;
 366                                 interrupt-controller;
 367                                 #interrupt-cells = <2>;
 368                         };
 369
 370                         gpio4: gpio@020a8000 {
 371                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 372                                 reg = <0x020a8000 0x4000>;
 373                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 374                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 375                                 gpio-controller;
 376                                 #gpio-cells = <2>;
 377                                 interrupt-controller;
 378                                 #interrupt-cells = <2>;
 379                         };
 380
 381                         gpio5: gpio@020ac000 {
 382                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 383                                 reg = <0x020ac000 0x4000>;
 384                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 385                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 386                                 gpio-controller;
 387                                 #gpio-cells = <2>;
 388                                 interrupt-controller;
 389                                 #interrupt-cells = <2>;
 390                         };
 391
 392                         kpp: kpp@020b8000 {
 393                                 reg = <0x020b8000 0x4000>;
 394                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 395                         };
 396
 397                         wdog1: wdog@020bc000 {
 398                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 399                                 reg = <0x020bc000 0x4000>;
 400                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 402                         };
 403
 404                         wdog2: wdog@020c0000 {
 405                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 406                                 reg = <0x020c0000 0x4000>;
 407                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 409                                 status = "disabled";
 410                         };
 411
 412                         clks: ccm@020c4000 {
 413                                 compatible = "fsl,imx6sl-ccm";
 414                                 reg = <0x020c4000 0x4000>;
 415                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 416                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 417                                 #clock-cells = <1>;
 418                         };
 419
 420                         anatop: anatop@020c8000 {
 421                                 compatible = "fsl,imx6sl-anatop",
 422                                              "fsl,imx6q-anatop",
 423                                              "syscon", "simple-bus";
 424                                 reg = <0x020c8000 0x1000>;
 425                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 426                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 427                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 428
 429                                 regulator-1p1@110 {
 430                                         compatible = "fsl,anatop-regulator";
 431                                         regulator-name = "vdd1p1";
 432                                         regulator-min-microvolt = <800000>;
 433                                         regulator-max-microvolt = <1375000>;
 434                                         regulator-always-on;
 435                                         anatop-reg-offset = <0x110>;
 436                                         anatop-vol-bit-shift = <8>;
 437                                         anatop-vol-bit-width = <5>;
 438                                         anatop-min-bit-val = <4>;
 439                                         anatop-min-voltage = <800000>;
 440                                         anatop-max-voltage = <1375000>;
 441                                 };
 442
 443                                 regulator-3p0@120 {
 444                                         compatible = "fsl,anatop-regulator";
 445                                         regulator-name = "vdd3p0";
 446                                         regulator-min-microvolt = <2800000>;
 447                                         regulator-max-microvolt = <3150000>;
 448                                         regulator-always-on;
 449                                         anatop-reg-offset = <0x120>;
 450                                         anatop-vol-bit-shift = <8>;
 451                                         anatop-vol-bit-width = <5>;
 452                                         anatop-min-bit-val = <0>;
 453                                         anatop-min-voltage = <2625000>;
 454                                         anatop-max-voltage = <3400000>;
 455                                 };
 456
 457                                 regulator-2p5@130 {
 458                                         compatible = "fsl,anatop-regulator";
 459                                         regulator-name = "vdd2p5";
 460                                         regulator-min-microvolt = <2100000>;
 461                                         regulator-max-microvolt = <2850000>;
 462                                         regulator-always-on;
 463                                         anatop-reg-offset = <0x130>;
 464                                         anatop-vol-bit-shift = <8>;
 465                                         anatop-vol-bit-width = <5>;
 466                                         anatop-min-bit-val = <0>;
 467                                         anatop-min-voltage = <2100000>;
 468                                         anatop-max-voltage = <2850000>;
 469                                 };
 470
 471                                 reg_arm: regulator-vddcore@140 {
 472                                         compatible = "fsl,anatop-regulator";
 473                                         regulator-name = "vddarm";
 474                                         regulator-min-microvolt = <725000>;
 475                                         regulator-max-microvolt = <1450000>;
 476                                         regulator-always-on;
 477                                         anatop-reg-offset = <0x140>;
 478                                         anatop-vol-bit-shift = <0>;
 479                                         anatop-vol-bit-width = <5>;
 480                                         anatop-delay-reg-offset = <0x170>;
 481                                         anatop-delay-bit-shift = <24>;
 482                                         anatop-delay-bit-width = <2>;
 483                                         anatop-min-bit-val = <1>;
 484                                         anatop-min-voltage = <725000>;
 485                                         anatop-max-voltage = <1450000>;
 486                                 };
 487
 488                                 reg_pu: regulator-vddpu@140 {
 489                                         compatible = "fsl,anatop-regulator";
 490                                         regulator-name = "vddpu";
 491                                         regulator-min-microvolt = <725000>;
 492                                         regulator-max-microvolt = <1450000>;
 493                                         regulator-always-on;
 494                                         anatop-reg-offset = <0x140>;
 495                                         anatop-vol-bit-shift = <9>;
 496                                         anatop-vol-bit-width = <5>;
 497                                         anatop-delay-reg-offset = <0x170>;
 498                                         anatop-delay-bit-shift = <26>;
 499                                         anatop-delay-bit-width = <2>;
 500                                         anatop-min-bit-val = <1>;
 501                                         anatop-min-voltage = <725000>;
 502                                         anatop-max-voltage = <1450000>;
 503                                 };
 504
 505                                 reg_soc: regulator-vddsoc@140 {
 506                                         compatible = "fsl,anatop-regulator";
 507                                         regulator-name = "vddsoc";
 508                                         regulator-min-microvolt = <725000>;
 509                                         regulator-max-microvolt = <1450000>;
 510                                         regulator-always-on;
 511                                         anatop-reg-offset = <0x140>;
 512                                         anatop-vol-bit-shift = <18>;
 513                                         anatop-vol-bit-width = <5>;
 514                                         anatop-delay-reg-offset = <0x170>;
 515                                         anatop-delay-bit-shift = <28>;
 516                                         anatop-delay-bit-width = <2>;
 517                                         anatop-min-bit-val = <1>;
 518                                         anatop-min-voltage = <725000>;
 519                                         anatop-max-voltage = <1450000>;
 520                                 };
 521                         };
 522
 523                         usbphy1: usbphy@020c9000 {
 524                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 525                                 reg = <0x020c9000 0x1000>;
 526                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 527                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 528                                 fsl,anatop = <&anatop>;
 529                         };
 530
 531                         usbphy2: usbphy@020ca000 {
 532                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 533                                 reg = <0x020ca000 0x1000>;
 534                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 535                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 536                                 fsl,anatop = <&anatop>;
 537                         };
 538
 539                         snvs@020cc000 {
 540                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 541                                 #address-cells = <1>;
 542                                 #size-cells = <1>;
 543                                 ranges = <0 0x020cc000 0x4000>;
 544
 545                                 snvs-rtc-lp@34 {
 546                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 547                                         reg = <0x34 0x58>;
 548                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 549                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 550                                 };
 551                         };
 552
 553                         epit1: epit@020d0000 {
 554                                 reg = <0x020d0000 0x4000>;
 555                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 556                         };
 557
 558                         epit2: epit@020d4000 {
 559                                 reg = <0x020d4000 0x4000>;
 560                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 561                         };
 562
 563                         src: src@020d8000 {
 564                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 565                                 reg = <0x020d8000 0x4000>;
 566                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 567                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 568                                 #reset-cells = <1>;
 569                         };
 570
 571                         gpc: gpc@020dc000 {
 572                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 573                                 reg = <0x020dc000 0x4000>;
 574                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 575                         };
 576
 577                         gpr: iomuxc-gpr@020e0000 {
 578                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 579                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 580                                 reg = <0x020e0000 0x38>;
 581                         };
 582
 583                         iomuxc: iomuxc@020e0000 {
 584                                 compatible = "fsl,imx6sl-iomuxc";
 585                                 reg = <0x020e0000 0x4000>;
 586                         };
 587
 588                         csi: csi@020e4000 {
 589                                 reg = <0x020e4000 0x4000>;
 590                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 591                         };
 592
 593                         spdc: spdc@020e8000 {
 594                                 reg = <0x020e8000 0x4000>;
 595                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 596                         };
 597
 598                         sdma: sdma@020ec000 {
 599                                 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
 600                                 reg = <0x020ec000 0x4000>;
 601                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 602                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 603                                          <&clks IMX6SL_CLK_SDMA>;
 604                                 clock-names = "ipg", "ahb";
 605                                 #dma-cells = <3>;
 606                                 /* imx6sl reuses imx6q sdma firmware */
 607                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 608                         };
 609
 610                         pxp: pxp@020f0000 {
 611                                 reg = <0x020f0000 0x4000>;
 612                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 613                         };
 614
 615                         epdc: epdc@020f4000 {
 616                                 reg = <0x020f4000 0x4000>;
 617                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 618                         };
 619
 620                         lcdif: lcdif@020f8000 {
 621                                 reg = <0x020f8000 0x4000>;
 622                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 623                         };
 624
 625                         dcp: dcp@020fc000 {
 626                                 reg = <0x020fc000 0x4000>;
 627                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 628                         };
 629                 };
 630
 631                 aips2: aips-bus@02100000 {
 632                         compatible = "fsl,aips-bus", "simple-bus";
 633                         #address-cells = <1>;
 634                         #size-cells = <1>;
 635                         reg = <0x02100000 0x100000>;
 636                         ranges;
 637
 638                         usbotg1: usb@02184000 {
 639                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 640                                 reg = <0x02184000 0x200>;
 641                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 642                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 643                                 fsl,usbphy = <&usbphy1>;
 644                                 fsl,usbmisc = <&usbmisc 0>;
 645                                 status = "disabled";
 646                         };
 647
 648                         usbotg2: usb@02184200 {
 649                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 650                                 reg = <0x02184200 0x200>;
 651                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 652                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 653                                 fsl,usbphy = <&usbphy2>;
 654                                 fsl,usbmisc = <&usbmisc 1>;
 655                                 status = "disabled";
 656                         };
 657
 658                         usbh: usb@02184400 {
 659                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 660                                 reg = <0x02184400 0x200>;
 661                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 662                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 663                                 fsl,usbmisc = <&usbmisc 2>;
 664                                 status = "disabled";
 665                         };
 666
 667                         usbmisc: usbmisc@02184800 {
 668                                 #index-cells = <1>;
 669                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 670                                 reg = <0x02184800 0x200>;
 671                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 672                         };
 673
 674                         fec: ethernet@02188000 {
 675                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 676                                 reg = <0x02188000 0x4000>;
 677                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 678                                 clocks = <&clks IMX6SL_CLK_ENET_REF>,
 679                                          <&clks IMX6SL_CLK_ENET_REF>;
 680                                 clock-names = "ipg", "ahb";
 681                                 status = "disabled";
 682                         };
 683
 684                         usdhc1: usdhc@02190000 {
 685                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 686                                 reg = <0x02190000 0x4000>;
 687                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 688                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 689                                          <&clks IMX6SL_CLK_USDHC1>,
 690                                          <&clks IMX6SL_CLK_USDHC1>;
 691                                 clock-names = "ipg", "ahb", "per";
 692                                 bus-width = <4>;
 693                                 status = "disabled";
 694                         };
 695
 696                         usdhc2: usdhc@02194000 {
 697                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 698                                 reg = <0x02194000 0x4000>;
 699                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 700                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 701                                          <&clks IMX6SL_CLK_USDHC2>,
 702                                          <&clks IMX6SL_CLK_USDHC2>;
 703                                 clock-names = "ipg", "ahb", "per";
 704                                 bus-width = <4>;
 705                                 status = "disabled";
 706                         };
 707
 708                         usdhc3: usdhc@02198000 {
 709                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 710                                 reg = <0x02198000 0x4000>;
 711                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 712                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 713                                          <&clks IMX6SL_CLK_USDHC3>,
 714                                          <&clks IMX6SL_CLK_USDHC3>;
 715                                 clock-names = "ipg", "ahb", "per";
 716                                 bus-width = <4>;
 717                                 status = "disabled";
 718                         };
 719
 720                         usdhc4: usdhc@0219c000 {
 721                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 722                                 reg = <0x0219c000 0x4000>;
 723                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 725                                          <&clks IMX6SL_CLK_USDHC4>,
 726                                          <&clks IMX6SL_CLK_USDHC4>;
 727                                 clock-names = "ipg", "ahb", "per";
 728                                 bus-width = <4>;
 729                                 status = "disabled";
 730                         };
 731
 732                         i2c1: i2c@021a0000 {
 733                                 #address-cells = <1>;
 734                                 #size-cells = <0>;
 735                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 736                                 reg = <0x021a0000 0x4000>;
 737                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 738                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c2: i2c@021a4000 {
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 746                                 reg = <0x021a4000 0x4000>;
 747                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 749                                 status = "disabled";
 750                         };
 751
 752                         i2c3: i2c@021a8000 {
 753                                 #address-cells = <1>;
 754                                 #size-cells = <0>;
 755                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 756                                 reg = <0x021a8000 0x4000>;
 757                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 759                                 status = "disabled";
 760                         };
 761
 762                         mmdc: mmdc@021b0000 {
 763                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 764                                 reg = <0x021b0000 0x4000>;
 765                         };
 766
 767                         rngb: rngb@021b4000 {
 768                                 reg = <0x021b4000 0x4000>;
 769                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 770                         };
 771
 772                         weim: weim@021b8000 {
 773                                 reg = <0x021b8000 0x4000>;
 774                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 775                         };
 776
 777                         ocotp: ocotp@021bc000 {
 778                                 compatible = "fsl,imx6sl-ocotp";
 779                                 reg = <0x021bc000 0x4000>;
 780                         };
 781
 782                         audmux: audmux@021d8000 {
 783                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 784                                 reg = <0x021d8000 0x4000>;
 785                                 status = "disabled";
 786                         };
 787                 };
 788         };
 789 };