2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "skeleton.dtsi"
11 #include "imx6sl-pinfunc.h"
12 #include <dt-bindings/clock/imx6sl-clock.h>
35 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
45 fsl,soc-operating-points = <
46 /* ARM kHz SOC-PU uV */
51 clock-latency = <61036>; /* two CLK32 periods */
52 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
53 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
54 <&clks IMX6SL_CLK_PLL1_SYS>;
55 clock-names = "arm", "pll2_pfd2_396m", "step",
56 "pll1_sw", "pll1_sys";
57 arm-supply = <®_arm>;
58 pu-supply = <®_pu>;
59 soc-supply = <®_soc>;
63 intc: interrupt-controller@00a01000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
69 reg = <0x00a01000 0x1000>,
78 compatible = "fixed-clock";
79 clock-frequency = <32768>;
83 compatible = "fixed-clock";
84 clock-frequency = <24000000>;
88 pu_dummy: pudummy_reg {
89 compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
93 compatible = "fsl,mxs_viim";
94 reg = <0x02098000 0x1000>, /* GPT base */
95 <0x021bc000 0x1000>; /* OCOTP base */
101 compatible = "simple-bus";
102 interrupt-parent = <&intc>;
105 busfreq { /* BUSFREQ */
106 compatible = "fsl,imx6_busfreq";
107 clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
108 <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
109 <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
110 <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2>,
111 <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
112 <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
113 <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM>,
114 <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
115 <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2>,
116 <&clks IMX6SL_CLK_STEP>;
117 clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
118 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
119 "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step";
120 fsl,max_ddr_freq = <400000000>;
123 L2: l2-cache@00a02000 {
124 compatible = "arm,pl310-cache";
125 reg = <0x00a02000 0x1000>;
126 interrupts = <0 92 0x04>;
129 arm,tag-latency = <4 2 3>;
130 arm,data-latency = <4 2 3>;
134 compatible = "arm,cortex-a9-pmu";
135 interrupts = <0 94 0x04>;
138 aips1: aips-bus@02000000 {
139 compatible = "fsl,aips-bus", "simple-bus";
140 #address-cells = <1>;
142 reg = <0x02000000 0x100000>;
145 spba: spba-bus@02000000 {
146 compatible = "fsl,spba-bus", "simple-bus";
147 #address-cells = <1>;
149 reg = <0x02000000 0x40000>;
152 spdif: spdif@02004000 {
153 compatible = "fsl,imx6sl-spdif",
155 reg = <0x02004000 0x4000>;
156 interrupts = <0 52 0x04>;
157 dmas = <&sdma 14 18 0>,
159 dma-names = "rx", "tx";
160 clocks = <&clks IMX6SL_CLK_SPDIF>,
161 <&clks IMX6SL_CLK_OSC>,
162 <&clks IMX6SL_CLK_SPDIF>,
163 <&clks 0>, <&clks 0>, <&clks 0>,
164 <&clks IMX6SL_CLK_IPG>,
165 <&clks 0>, <&clks 0>,
166 <&clks IMX6SL_CLK_SPBA>;
167 clock-names = "core", "rxtx0",
175 ecspi1: ecspi@02008000 {
176 #address-cells = <1>;
178 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
179 reg = <0x02008000 0x4000>;
180 interrupts = <0 31 0x04>;
181 clocks = <&clks IMX6SL_CLK_ECSPI1>,
182 <&clks IMX6SL_CLK_ECSPI1>;
183 clock-names = "ipg", "per";
187 ecspi2: ecspi@0200c000 {
188 #address-cells = <1>;
190 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
191 reg = <0x0200c000 0x4000>;
192 interrupts = <0 32 0x04>;
193 clocks = <&clks IMX6SL_CLK_ECSPI2>,
194 <&clks IMX6SL_CLK_ECSPI2>;
195 clock-names = "ipg", "per";
199 ecspi3: ecspi@02010000 {
200 #address-cells = <1>;
202 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
203 reg = <0x02010000 0x4000>;
204 interrupts = <0 33 0x04>;
205 clocks = <&clks IMX6SL_CLK_ECSPI3>,
206 <&clks IMX6SL_CLK_ECSPI3>;
207 clock-names = "ipg", "per";
211 ecspi4: ecspi@02014000 {
212 #address-cells = <1>;
214 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
215 reg = <0x02014000 0x4000>;
216 interrupts = <0 34 0x04>;
217 clocks = <&clks IMX6SL_CLK_ECSPI4>,
218 <&clks IMX6SL_CLK_ECSPI4>;
219 clock-names = "ipg", "per";
223 uart5: serial@02018000 {
224 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
225 reg = <0x02018000 0x4000>;
226 interrupts = <0 30 0x04>;
227 clocks = <&clks IMX6SL_CLK_UART>,
228 <&clks IMX6SL_CLK_UART_SERIAL>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
231 dma-names = "rx", "tx";
235 uart1: serial@02020000 {
236 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
237 reg = <0x02020000 0x4000>;
238 interrupts = <0 26 0x04>;
239 clocks = <&clks IMX6SL_CLK_UART>,
240 <&clks IMX6SL_CLK_UART_SERIAL>;
241 clock-names = "ipg", "per";
242 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
243 dma-names = "rx", "tx";
247 uart2: serial@02024000 {
248 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
249 reg = <0x02024000 0x4000>;
250 interrupts = <0 27 0x04>;
251 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per";
254 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
255 dma-names = "rx", "tx";
260 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
261 reg = <0x02028000 0x4000>;
262 interrupts = <0 46 0x04>;
263 clocks = <&clks IMX6SL_CLK_SSI1>, <&clks IMX6SL_CLK_SSI1>;
264 clock-names = "ipg", "baud";
265 dmas = <&sdma 37 1 0>,
267 dma-names = "rx", "tx";
272 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
273 reg = <0x0202c000 0x4000>;
274 interrupts = <0 47 0x04>;
275 clocks = <&clks IMX6SL_CLK_SSI2>, <&clks IMX6SL_CLK_SSI2>;
276 clock-names = "ipg", "baud";
277 dmas = <&sdma 41 1 0>,
279 dma-names = "rx", "tx";
284 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
285 reg = <0x02030000 0x4000>;
286 interrupts = <0 48 0x04>;
287 clocks = <&clks IMX6SL_CLK_SSI3>, <&clks IMX6SL_CLK_SSI3>;
288 clock-names = "ipg", "baud";
289 dmas = <&sdma 45 1 0>,
291 dma-names = "rx", "tx";
295 uart3: serial@02034000 {
296 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
297 reg = <0x02034000 0x4000>;
298 interrupts = <0 28 0x04>;
299 clocks = <&clks IMX6SL_CLK_UART>,
300 <&clks IMX6SL_CLK_UART_SERIAL>;
301 clock-names = "ipg", "per";
302 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
303 dma-names = "rx", "tx";
307 uart4: serial@02038000 {
308 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
309 reg = <0x02038000 0x4000>;
310 interrupts = <0 29 0x04>;
311 clocks = <&clks IMX6SL_CLK_UART>,
312 <&clks IMX6SL_CLK_UART_SERIAL>;
313 clock-names = "ipg", "per";
314 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
315 dma-names = "rx", "tx";
322 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
323 reg = <0x02080000 0x4000>;
324 interrupts = <0 83 0x04>;
325 clocks = <&clks IMX6SL_CLK_PWM1>,
326 <&clks IMX6SL_CLK_PWM1>;
327 clock-names = "ipg", "per";
332 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
333 reg = <0x02084000 0x4000>;
334 interrupts = <0 84 0x04>;
335 clocks = <&clks IMX6SL_CLK_PWM2>,
336 <&clks IMX6SL_CLK_PWM2>;
337 clock-names = "ipg", "per";
342 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
343 reg = <0x02088000 0x4000>;
344 interrupts = <0 85 0x04>;
345 clocks = <&clks IMX6SL_CLK_PWM3>,
346 <&clks IMX6SL_CLK_PWM3>;
347 clock-names = "ipg", "per";
352 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
353 reg = <0x0208c000 0x4000>;
354 interrupts = <0 86 0x04>;
355 clocks = <&clks IMX6SL_CLK_PWM4>,
356 <&clks IMX6SL_CLK_PWM4>;
357 clock-names = "ipg", "per";
361 compatible = "fsl,imx6sl-gpt";
362 reg = <0x02098000 0x4000>;
363 interrupts = <0 55 0x04>;
364 clocks = <&clks IMX6SL_CLK_GPT>,
365 <&clks IMX6SL_CLK_GPT_SERIAL>;
366 clock-names = "ipg", "per";
369 gpio1: gpio@0209c000 {
370 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
371 reg = <0x0209c000 0x4000>;
372 interrupts = <0 66 0x04 0 67 0x04>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
379 gpio2: gpio@020a0000 {
380 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
381 reg = <0x020a0000 0x4000>;
382 interrupts = <0 68 0x04 0 69 0x04>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
389 gpio3: gpio@020a4000 {
390 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
391 reg = <0x020a4000 0x4000>;
392 interrupts = <0 70 0x04 0 71 0x04>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
399 gpio4: gpio@020a8000 {
400 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
401 reg = <0x020a8000 0x4000>;
402 interrupts = <0 72 0x04 0 73 0x04>;
405 interrupt-controller;
406 #interrupt-cells = <2>;
409 gpio5: gpio@020ac000 {
410 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
411 reg = <0x020ac000 0x4000>;
412 interrupts = <0 74 0x04 0 75 0x04>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
420 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
421 reg = <0x020b8000 0x4000>;
422 interrupts = <0 82 0x04>;
423 clocks = <&clks IMX6SL_CLK_DUMMY>;
426 wdog1: wdog@020bc000 {
427 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
428 reg = <0x020bc000 0x4000>;
429 interrupts = <0 80 0x04>;
430 clocks = <&clks IMX6SL_CLK_DUMMY>;
433 wdog2: wdog@020c0000 {
434 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
435 reg = <0x020c0000 0x4000>;
436 interrupts = <0 81 0x04>;
437 clocks = <&clks IMX6SL_CLK_DUMMY>;
442 compatible = "fsl,imx6sl-ccm";
443 reg = <0x020c4000 0x4000>;
444 interrupts = <0 87 0x04 0 88 0x04>;
448 anatop: anatop@020c8000 {
449 compatible = "fsl,imx6sl-anatop",
451 "syscon", "simple-bus";
452 reg = <0x020c8000 0x1000>;
453 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
456 compatible = "fsl,anatop-regulator";
457 regulator-name = "vdd1p1";
458 regulator-min-microvolt = <800000>;
459 regulator-max-microvolt = <1375000>;
461 anatop-reg-offset = <0x110>;
462 anatop-vol-bit-shift = <8>;
463 anatop-vol-bit-width = <5>;
464 anatop-min-bit-val = <4>;
465 anatop-min-voltage = <800000>;
466 anatop-max-voltage = <1375000>;
470 compatible = "fsl,anatop-regulator";
471 regulator-name = "vdd3p0";
472 regulator-min-microvolt = <2800000>;
473 regulator-max-microvolt = <3150000>;
475 anatop-reg-offset = <0x120>;
476 anatop-vol-bit-shift = <8>;
477 anatop-vol-bit-width = <5>;
478 anatop-min-bit-val = <0>;
479 anatop-min-voltage = <2625000>;
480 anatop-max-voltage = <3400000>;
484 compatible = "fsl,anatop-regulator";
485 regulator-name = "vdd2p5";
486 regulator-min-microvolt = <2100000>;
487 regulator-max-microvolt = <2850000>;
489 anatop-reg-offset = <0x130>;
490 anatop-vol-bit-shift = <8>;
491 anatop-vol-bit-width = <5>;
492 anatop-min-bit-val = <0>;
493 anatop-min-voltage = <2100000>;
494 anatop-max-voltage = <2850000>;
497 reg_arm: regulator-vddcore@140 {
498 compatible = "fsl,anatop-regulator";
499 regulator-name = "cpu";
500 regulator-min-microvolt = <725000>;
501 regulator-max-microvolt = <1450000>;
503 anatop-reg-offset = <0x140>;
504 anatop-vol-bit-shift = <0>;
505 anatop-vol-bit-width = <5>;
506 anatop-delay-reg-offset = <0x170>;
507 anatop-delay-bit-shift = <24>;
508 anatop-delay-bit-width = <2>;
509 anatop-min-bit-val = <1>;
510 anatop-min-voltage = <725000>;
511 anatop-max-voltage = <1450000>;
514 reg_pu: regulator-vddpu@140 {
515 compatible = "fsl,anatop-regulator";
516 regulator-name = "vddpu";
517 regulator-min-microvolt = <725000>;
518 regulator-max-microvolt = <1450000>;
519 anatop-reg-offset = <0x140>;
520 anatop-vol-bit-shift = <9>;
521 anatop-vol-bit-width = <5>;
522 anatop-delay-reg-offset = <0x170>;
523 anatop-delay-bit-shift = <26>;
524 anatop-delay-bit-width = <2>;
525 anatop-min-bit-val = <1>;
526 anatop-min-voltage = <725000>;
527 anatop-max-voltage = <1450000>;
530 reg_soc: regulator-vddsoc@140 {
531 compatible = "fsl,anatop-regulator";
532 regulator-name = "vddsoc";
533 regulator-min-microvolt = <725000>;
534 regulator-max-microvolt = <1450000>;
536 anatop-reg-offset = <0x140>;
537 anatop-vol-bit-shift = <18>;
538 anatop-vol-bit-width = <5>;
539 anatop-delay-reg-offset = <0x170>;
540 anatop-delay-bit-shift = <28>;
541 anatop-delay-bit-width = <2>;
542 anatop-min-bit-val = <1>;
543 anatop-min-voltage = <725000>;
544 anatop-max-voltage = <1450000>;
549 compatible = "fsl,imx6sl-tempmon", "fsl,imx6q-tempmon";
550 interrupts = <0 49 0x04>;
551 fsl,tempmon = <&anatop>;
552 fsl,tempmon-data = <&ocotp>;
553 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
556 usbphy1: usbphy@020c9000 {
557 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
558 reg = <0x020c9000 0x1000>;
559 interrupts = <0 44 0x04>;
560 clocks = <&clks IMX6SL_CLK_USBPHY1>;
561 fsl,anatop = <&anatop>;
564 usbphy2: usbphy@020ca000 {
565 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
566 reg = <0x020ca000 0x1000>;
567 interrupts = <0 45 0x04>;
568 clocks = <&clks IMX6SL_CLK_USBPHY2>;
569 fsl,anatop = <&anatop>;
572 usbphy_nop1: usbphy_nop1 {
573 compatible = "usb-nop-xceiv";
574 clocks = <&clks IMX6SL_CLK_USBPHY1>;
575 clock-names = "main_clk";
579 compatible = "fsl,sec-v4.0-mon", "simple-bus";
580 #address-cells = <1>;
582 ranges = <0 0x020cc000 0x4000>;
585 compatible = "fsl,sec-v4.0-mon-rtc-lp";
587 interrupts = <0 19 0x04 0 20 0x04>;
591 epit1: epit@020d0000 {
592 reg = <0x020d0000 0x4000>;
593 interrupts = <0 56 0x04>;
596 epit2: epit@020d4000 {
597 reg = <0x020d4000 0x4000>;
598 interrupts = <0 57 0x04>;
602 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
603 reg = <0x020d8000 0x4000>;
604 interrupts = <0 91 0x04 0 96 0x04>;
608 ocram: sram@00904000 {
609 compatible = "mmio-sram";
610 reg = <0x00904000 0x1C000>;
611 clocks = <&clks IMX6SL_CLK_OCRAM>;
615 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
616 reg = <0x020dc000 0x4000>;
617 interrupts = <0 89 0x04>;
618 clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
619 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
620 <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
621 <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
622 clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
623 "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
624 pu-supply = <®_pu>;
627 gpr: iomuxc-gpr@020e0000 {
628 compatible = "fsl,imx6sl-iomuxc-gpr", "syscon";
629 reg = <0x020e0000 0x38>;
632 iomuxc: iomuxc@020e0000 {
633 compatible = "fsl,imx6sl-iomuxc";
634 reg = <0x020e0000 0x4000>;
638 compatible = "fsl,imx6sl-csi";
639 reg = <0x020e4000 0x4000>;
640 interrupts = <0 7 0x04>;
644 spdc: spdc@020e8000 {
645 reg = <0x020e8000 0x4000>;
646 interrupts = <0 6 0x04>;
649 sdma: sdma@020ec000 {
650 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
651 reg = <0x020ec000 0x4000>;
652 interrupts = <0 2 0x04>;
653 clocks = <&clks IMX6SL_CLK_SDMA>,
654 <&clks IMX6SL_CLK_SDMA>;
655 clock-names = "ipg", "ahb";
658 /* imx6sl reuses imx6q sdma firmware */
659 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
663 compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
664 reg = <0x020f0000 0x4000>;
665 interrupts = <0 98 0x04>;
666 clocks = <&clks 111>;
667 clock-names = "pxp-axi";
671 epdc: epdc@020f4000 {
672 compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
673 reg = <0x020f4000 0x4000>;
674 interrupts = <0 97 0x04>;
675 clocks = <&clks IMX6SL_CLK_EPDC_AXI>,
676 <&clks IMX6SL_CLK_EPDC_PIX>;
677 clock-names = "epdc_axi", "epdc_pix";
680 lcdif: lcdif@020f8000 {
681 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
682 reg = <0x020f8000 0x4000>;
683 interrupts = <0 39 0x04>;
684 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
685 <&clks IMX6SL_CLK_LCDIF_AXI>;
686 clock-names = "pix", "axi";
691 reg = <0x020fc000 0x4000>;
692 interrupts = <0 99 0x04>;
696 aips2: aips-bus@02100000 {
697 compatible = "fsl,aips-bus", "simple-bus";
698 #address-cells = <1>;
700 reg = <0x02100000 0x100000>;
703 usbotg1: usb@02184000 {
704 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
705 reg = <0x02184000 0x200>;
706 interrupts = <0 43 0x04>;
707 clocks = <&clks IMX6SL_CLK_USBOH3>;
708 fsl,usbphy = <&usbphy1>;
709 fsl,usbmisc = <&usbmisc 0>;
710 fsl,anatop = <&anatop>;
714 usbotg2: usb@02184200 {
715 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
716 reg = <0x02184200 0x200>;
717 interrupts = <0 42 0x04>;
718 clocks = <&clks IMX6SL_CLK_USBOH3>;
719 fsl,usbphy = <&usbphy2>;
720 fsl,usbmisc = <&usbmisc 1>;
725 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
726 reg = <0x02184400 0x200>;
727 interrupts = <0 40 0x04>;
728 clocks = <&clks IMX6SL_CLK_USBOH3>;
729 fsl,usbmisc = <&usbmisc 2>;
731 fsl,usbphy = <&usbphy_nop1>;
732 fsl,anatop = <&anatop>;
736 usbmisc: usbmisc@02184800 {
738 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
739 reg = <0x02184800 0x200>;
740 clocks = <&clks IMX6SL_CLK_USBOH3>;
743 fec: ethernet@02188000 {
744 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
745 reg = <0x02188000 0x4000>;
746 interrupts = <0 114 0x04>;
747 clocks = <&clks IMX6SL_CLK_ENET>,
748 <&clks IMX6SL_CLK_ENET_REF>;
749 clock-names = "ipg", "ahb";
753 usdhc1: usdhc@02190000 {
754 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
755 reg = <0x02190000 0x4000>;
756 interrupts = <0 22 0x04>;
757 clocks = <&clks IMX6SL_CLK_USDHC1>,
758 <&clks IMX6SL_CLK_USDHC1>,
759 <&clks IMX6SL_CLK_USDHC1>;
760 clock-names = "ipg", "ahb", "per";
765 usdhc2: usdhc@02194000 {
766 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
767 reg = <0x02194000 0x4000>;
768 interrupts = <0 23 0x04>;
769 clocks = <&clks IMX6SL_CLK_USDHC2>,
770 <&clks IMX6SL_CLK_USDHC2>,
771 <&clks IMX6SL_CLK_USDHC2>;
772 clock-names = "ipg", "ahb", "per";
777 usdhc3: usdhc@02198000 {
778 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
779 reg = <0x02198000 0x4000>;
780 interrupts = <0 24 0x04>;
781 clocks = <&clks IMX6SL_CLK_USDHC3>,
782 <&clks IMX6SL_CLK_USDHC3>,
783 <&clks IMX6SL_CLK_USDHC3>;
784 clock-names = "ipg", "ahb", "per";
789 usdhc4: usdhc@0219c000 {
790 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
791 reg = <0x0219c000 0x4000>;
792 interrupts = <0 25 0x04>;
793 clocks = <&clks IMX6SL_CLK_USDHC4>,
794 <&clks IMX6SL_CLK_USDHC4>,
795 <&clks IMX6SL_CLK_USDHC4>;
796 clock-names = "ipg", "ahb", "per";
802 #address-cells = <1>;
804 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
805 reg = <0x021a0000 0x4000>;
806 interrupts = <0 36 0x04>;
807 clocks = <&clks IMX6SL_CLK_I2C1>;
812 #address-cells = <1>;
814 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
815 reg = <0x021a4000 0x4000>;
816 interrupts = <0 37 0x04>;
817 clocks = <&clks IMX6SL_CLK_I2C2>;
822 #address-cells = <1>;
824 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
825 reg = <0x021a8000 0x4000>;
826 interrupts = <0 38 0x04>;
827 clocks = <&clks IMX6SL_CLK_I2C3>;
831 mmdc: mmdc@021b0000 {
832 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
833 reg = <0x021b0000 0x4000>;
836 rngb: rngb@021b4000 {
837 reg = <0x021b4000 0x4000>;
838 interrupts = <0 5 0x04>;
841 weim: weim@021b8000 {
842 reg = <0x021b8000 0x4000>;
843 interrupts = <0 14 0x04>;
846 ocotp: ocotp-ctrl@021bc000 {
847 compatible = "syscon";
848 reg = <0x021bc000 0x4000>;
851 ocotp-fuse@021bc000 {
852 compatible = "fsl,imx6sl-ocotp", "fsl,imx6q-ocotp";
853 reg = <0x021bc000 0x4000>;
854 clocks = <&clks IMX6SL_CLK_OCOTP>;
857 audmux: audmux@021d8000 {
858 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
859 reg = <0x021d8000 0x4000>;
864 compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
865 reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
867 reg-names = "iobase_2d", "iobase_vg",
869 interrupts = <0 10 0x04>, <0 11 0x04>;
870 interrupt-names = "irq_2d", "irq_vg";
871 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
872 <&clks IMX6SL_CLK_MMDC_ROOT>,
873 <&clks IMX6SL_CLK_GPU2D_OVG>;
874 clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
876 resets = <&src 3>, <&src 3>;
877 reset-names = "gpu2d", "gpuvg";
878 pu-supply = <®_pu>;
887 pinctrl_audmux_1: audmux-1 {
889 MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130B0
890 MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130B0
891 MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110B0
892 MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130B0
893 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130B0
899 pinctrl_csi_0: csigrp-0 {
901 MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
902 MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
903 MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
904 MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
905 MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
906 MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
907 MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
908 MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
909 MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
910 MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
911 MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
912 MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
913 MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
914 MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
915 MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
916 MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
922 pinctrl_ecspi1_1: ecspi1grp-1 {
924 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
925 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
926 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
932 pinctrl_epdc_0: epdcgrp-0 {
934 MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000
935 MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000
936 MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000
937 MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000
938 MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000
939 MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000
940 MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000
941 MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000
942 MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000
943 MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000
944 MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
945 MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
946 MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
947 MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
948 MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
949 MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
950 MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
951 MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000
952 MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000
953 MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000
954 MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
955 MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000
956 MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000
957 MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
958 MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000
959 MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
960 MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
961 MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
967 pinctrl_fec_1: fecgrp-1 {
969 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
970 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
971 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
972 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
973 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
974 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
975 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
976 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
977 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
981 pinctrl_fec_1_sleep: fecgrp-1-sleep {
983 MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
984 MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
985 MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
986 MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
987 MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
988 MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
989 MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
990 MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
996 pinctrl_i2c1_1: i2c1grp-1 {
998 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
999 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
1005 pinctrl_i2c2_1: i2c2grp-1 {
1007 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
1008 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
1014 pinctrl_i2c3_1: i2c3grp-1 {
1016 MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
1017 MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
1023 pinctrl_kpp_1: kpp_grp_1 {
1025 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
1026 MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
1027 MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
1028 MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
1029 MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
1030 MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
1034 pinctrl_kpp_1_sleep: kpp_grp_1_sleep {
1036 MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x3080
1037 MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x3080
1038 MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x3080
1039 MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x3080
1040 MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x3080
1041 MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x3080
1047 pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
1049 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
1050 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
1051 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
1052 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
1053 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
1054 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
1055 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
1056 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
1057 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
1058 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
1059 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
1060 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
1061 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
1062 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
1063 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
1064 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
1065 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
1066 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
1067 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
1068 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
1069 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
1070 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
1071 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
1072 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
1076 pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
1078 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
1079 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
1080 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
1081 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
1087 pinctrl_pwm1_0: pwm1grp-0 {
1089 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
1093 pinctrl_pwm1_0_sleep: pwm1grp-0-sleep {
1095 MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
1101 pinctrl_spdif_1: spdifgrp-1 {
1103 MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
1109 pinctrl_uart1_1: uart1grp-1 {
1111 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
1112 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
1118 pinctrl_usbotg1_1: usbotg1grp-1 {
1120 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
1124 pinctrl_usbotg1_2: usbotg1grp-2 {
1126 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
1130 pinctrl_usbotg1_3: usbotg1grp-3 {
1132 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
1136 pinctrl_usbotg1_4: usbotg1grp-4 {
1138 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
1142 pinctrl_usbotg1_5: usbotg1grp-5 {
1144 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
1150 pinctrl_usbotg2_1: usbotg2grp-1 {
1152 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
1156 pinctrl_usbotg2_2: usbotg2grp-2 {
1158 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
1162 pinctrl_usbotg2_3: usbotg2grp-3 {
1164 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
1168 pinctrl_usbotg2_4: usbotg2grp-4 {
1170 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
1176 pinctrl_usdhc1_1: usdhc1grp-1 {
1178 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
1179 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
1180 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1181 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1182 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1183 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1184 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
1185 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
1186 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
1187 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
1191 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
1193 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
1194 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
1195 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
1196 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
1197 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
1198 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
1199 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
1200 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
1201 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
1202 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
1206 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
1208 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
1209 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
1210 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
1211 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
1212 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
1213 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
1214 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
1215 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
1216 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
1217 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
1224 pinctrl_usdhc2_1: usdhc2grp-1 {
1226 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
1227 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
1228 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1229 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1230 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1231 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1235 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
1237 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
1238 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
1239 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
1240 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
1241 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
1242 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
1246 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
1248 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
1249 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
1250 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
1251 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
1252 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
1253 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
1259 pinctrl_usdhc3_1: usdhc3grp-1 {
1261 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
1262 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
1263 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1264 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1265 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1266 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1270 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
1272 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
1273 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
1274 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1275 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1276 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1277 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1281 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
1283 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
1284 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
1285 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1286 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1287 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1288 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9