2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "skeleton.dtsi"
11 #include "imx6sl-pinfunc.h"
12 #include <dt-bindings/clock/imx6sl-clock.h>
37 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
44 intc: interrupt-controller@00a01000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
50 reg = <0x00a01000 0x1000>,
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
72 compatible = "simple-bus";
73 interrupt-parent = <&intc>;
76 L2: l2-cache@00a02000 {
77 compatible = "arm,pl310-cache";
78 reg = <0x00a02000 0x1000>;
79 interrupts = <0 92 0x04>;
82 arm,tag-latency = <4 2 3>;
83 arm,data-latency = <4 2 3>;
87 compatible = "arm,cortex-a9-pmu";
88 interrupts = <0 94 0x04>;
91 aips1: aips-bus@02000000 {
92 compatible = "fsl,aips-bus", "simple-bus";
95 reg = <0x02000000 0x100000>;
98 spba: spba-bus@02000000 {
99 compatible = "fsl,spba-bus", "simple-bus";
100 #address-cells = <1>;
102 reg = <0x02000000 0x40000>;
105 spdif: spdif@02004000 {
106 reg = <0x02004000 0x4000>;
107 interrupts = <0 52 0x04>;
110 ecspi1: ecspi@02008000 {
111 #address-cells = <1>;
113 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
114 reg = <0x02008000 0x4000>;
115 interrupts = <0 31 0x04>;
116 clocks = <&clks IMX6SL_CLK_ECSPI1>,
117 <&clks IMX6SL_CLK_ECSPI1>;
118 clock-names = "ipg", "per";
122 ecspi2: ecspi@0200c000 {
123 #address-cells = <1>;
125 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
126 reg = <0x0200c000 0x4000>;
127 interrupts = <0 32 0x04>;
128 clocks = <&clks IMX6SL_CLK_ECSPI2>,
129 <&clks IMX6SL_CLK_ECSPI2>;
130 clock-names = "ipg", "per";
134 ecspi3: ecspi@02010000 {
135 #address-cells = <1>;
137 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
138 reg = <0x02010000 0x4000>;
139 interrupts = <0 33 0x04>;
140 clocks = <&clks IMX6SL_CLK_ECSPI3>,
141 <&clks IMX6SL_CLK_ECSPI3>;
142 clock-names = "ipg", "per";
146 ecspi4: ecspi@02014000 {
147 #address-cells = <1>;
149 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02014000 0x4000>;
151 interrupts = <0 34 0x04>;
152 clocks = <&clks IMX6SL_CLK_ECSPI4>,
153 <&clks IMX6SL_CLK_ECSPI4>;
154 clock-names = "ipg", "per";
158 uart5: serial@02018000 {
159 compatible = "fsl,imx6sl-uart",
160 "fsl,imx6q-uart", "fsl,imx21-uart";
161 reg = <0x02018000 0x4000>;
162 interrupts = <0 30 0x04>;
163 clocks = <&clks IMX6SL_CLK_UART>,
164 <&clks IMX6SL_CLK_UART_SERIAL>;
165 clock-names = "ipg", "per";
166 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
167 dma-names = "rx", "tx";
171 uart1: serial@02020000 {
172 compatible = "fsl,imx6sl-uart",
173 "fsl,imx6q-uart", "fsl,imx21-uart";
174 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>;
176 clocks = <&clks IMX6SL_CLK_UART>,
177 <&clks IMX6SL_CLK_UART_SERIAL>;
178 clock-names = "ipg", "per";
179 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
180 dma-names = "rx", "tx";
184 uart2: serial@02024000 {
185 compatible = "fsl,imx6sl-uart",
186 "fsl,imx6q-uart", "fsl,imx21-uart";
187 reg = <0x02024000 0x4000>;
188 interrupts = <0 27 0x04>;
189 clocks = <&clks IMX6SL_CLK_UART>,
190 <&clks IMX6SL_CLK_UART_SERIAL>;
191 clock-names = "ipg", "per";
192 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
193 dma-names = "rx", "tx";
198 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
199 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>;
201 clocks = <&clks IMX6SL_CLK_SSI1>;
202 dmas = <&sdma 37 1 0>,
204 dma-names = "rx", "tx";
205 fsl,fifo-depth = <15>;
210 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
211 reg = <0x0202c000 0x4000>;
212 interrupts = <0 47 0x04>;
213 clocks = <&clks IMX6SL_CLK_SSI2>;
214 dmas = <&sdma 41 1 0>,
216 dma-names = "rx", "tx";
217 fsl,fifo-depth = <15>;
222 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
223 reg = <0x02030000 0x4000>;
224 interrupts = <0 48 0x04>;
225 clocks = <&clks IMX6SL_CLK_SSI3>;
226 dmas = <&sdma 45 1 0>,
228 dma-names = "rx", "tx";
229 fsl,fifo-depth = <15>;
233 uart3: serial@02034000 {
234 compatible = "fsl,imx6sl-uart",
235 "fsl,imx6q-uart", "fsl,imx21-uart";
236 reg = <0x02034000 0x4000>;
237 interrupts = <0 28 0x04>;
238 clocks = <&clks IMX6SL_CLK_UART>,
239 <&clks IMX6SL_CLK_UART_SERIAL>;
240 clock-names = "ipg", "per";
241 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
242 dma-names = "rx", "tx";
246 uart4: serial@02038000 {
247 compatible = "fsl,imx6sl-uart",
248 "fsl,imx6q-uart", "fsl,imx21-uart";
249 reg = <0x02038000 0x4000>;
250 interrupts = <0 29 0x04>;
251 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per";
254 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
255 dma-names = "rx", "tx";
262 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
263 reg = <0x02080000 0x4000>;
264 interrupts = <0 83 0x04>;
265 clocks = <&clks IMX6SL_CLK_PWM1>,
266 <&clks IMX6SL_CLK_PWM1>;
267 clock-names = "ipg", "per";
272 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>;
275 clocks = <&clks IMX6SL_CLK_PWM2>,
276 <&clks IMX6SL_CLK_PWM2>;
277 clock-names = "ipg", "per";
282 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
283 reg = <0x02088000 0x4000>;
284 interrupts = <0 85 0x04>;
285 clocks = <&clks IMX6SL_CLK_PWM3>,
286 <&clks IMX6SL_CLK_PWM3>;
287 clock-names = "ipg", "per";
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x0208c000 0x4000>;
294 interrupts = <0 86 0x04>;
295 clocks = <&clks IMX6SL_CLK_PWM4>,
296 <&clks IMX6SL_CLK_PWM4>;
297 clock-names = "ipg", "per";
301 compatible = "fsl,imx6sl-gpt";
302 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
304 clocks = <&clks IMX6SL_CLK_GPT>,
305 <&clks IMX6SL_CLK_GPT_SERIAL>;
306 clock-names = "ipg", "per";
309 gpio1: gpio@0209c000 {
310 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
311 reg = <0x0209c000 0x4000>;
312 interrupts = <0 66 0x04 0 67 0x04>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
319 gpio2: gpio@020a0000 {
320 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
321 reg = <0x020a0000 0x4000>;
322 interrupts = <0 68 0x04 0 69 0x04>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
329 gpio3: gpio@020a4000 {
330 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
331 reg = <0x020a4000 0x4000>;
332 interrupts = <0 70 0x04 0 71 0x04>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
339 gpio4: gpio@020a8000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x020a8000 0x4000>;
342 interrupts = <0 72 0x04 0 73 0x04>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
349 gpio5: gpio@020ac000 {
350 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
351 reg = <0x020ac000 0x4000>;
352 interrupts = <0 74 0x04 0 75 0x04>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
360 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>;
364 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>;
368 clocks = <&clks IMX6SL_CLK_DUMMY>;
371 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>;
375 clocks = <&clks IMX6SL_CLK_DUMMY>;
380 compatible = "fsl,imx6sl-ccm";
381 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>;
386 anatop: anatop@020c8000 {
387 compatible = "fsl,imx6sl-anatop",
389 "syscon", "simple-bus";
390 reg = <0x020c8000 0x1000>;
391 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
394 compatible = "fsl,anatop-regulator";
395 regulator-name = "vdd1p1";
396 regulator-min-microvolt = <800000>;
397 regulator-max-microvolt = <1375000>;
399 anatop-reg-offset = <0x110>;
400 anatop-vol-bit-shift = <8>;
401 anatop-vol-bit-width = <5>;
402 anatop-min-bit-val = <4>;
403 anatop-min-voltage = <800000>;
404 anatop-max-voltage = <1375000>;
408 compatible = "fsl,anatop-regulator";
409 regulator-name = "vdd3p0";
410 regulator-min-microvolt = <2800000>;
411 regulator-max-microvolt = <3150000>;
413 anatop-reg-offset = <0x120>;
414 anatop-vol-bit-shift = <8>;
415 anatop-vol-bit-width = <5>;
416 anatop-min-bit-val = <0>;
417 anatop-min-voltage = <2625000>;
418 anatop-max-voltage = <3400000>;
422 compatible = "fsl,anatop-regulator";
423 regulator-name = "vdd2p5";
424 regulator-min-microvolt = <2100000>;
425 regulator-max-microvolt = <2850000>;
427 anatop-reg-offset = <0x130>;
428 anatop-vol-bit-shift = <8>;
429 anatop-vol-bit-width = <5>;
430 anatop-min-bit-val = <0>;
431 anatop-min-voltage = <2100000>;
432 anatop-max-voltage = <2850000>;
435 reg_arm: regulator-vddcore@140 {
436 compatible = "fsl,anatop-regulator";
437 regulator-name = "cpu";
438 regulator-min-microvolt = <725000>;
439 regulator-max-microvolt = <1450000>;
441 anatop-reg-offset = <0x140>;
442 anatop-vol-bit-shift = <0>;
443 anatop-vol-bit-width = <5>;
444 anatop-delay-reg-offset = <0x170>;
445 anatop-delay-bit-shift = <24>;
446 anatop-delay-bit-width = <2>;
447 anatop-min-bit-val = <1>;
448 anatop-min-voltage = <725000>;
449 anatop-max-voltage = <1450000>;
452 reg_pu: regulator-vddpu@140 {
453 compatible = "fsl,anatop-regulator";
454 regulator-name = "vddpu";
455 regulator-min-microvolt = <725000>;
456 regulator-max-microvolt = <1450000>;
458 anatop-reg-offset = <0x140>;
459 anatop-vol-bit-shift = <9>;
460 anatop-vol-bit-width = <5>;
461 anatop-delay-reg-offset = <0x170>;
462 anatop-delay-bit-shift = <26>;
463 anatop-delay-bit-width = <2>;
464 anatop-min-bit-val = <1>;
465 anatop-min-voltage = <725000>;
466 anatop-max-voltage = <1450000>;
469 reg_soc: regulator-vddsoc@140 {
470 compatible = "fsl,anatop-regulator";
471 regulator-name = "vddsoc";
472 regulator-min-microvolt = <725000>;
473 regulator-max-microvolt = <1450000>;
475 anatop-reg-offset = <0x140>;
476 anatop-vol-bit-shift = <18>;
477 anatop-vol-bit-width = <5>;
478 anatop-delay-reg-offset = <0x170>;
479 anatop-delay-bit-shift = <28>;
480 anatop-delay-bit-width = <2>;
481 anatop-min-bit-val = <1>;
482 anatop-min-voltage = <725000>;
483 anatop-max-voltage = <1450000>;
487 usbphy1: usbphy@020c9000 {
488 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
489 reg = <0x020c9000 0x1000>;
490 interrupts = <0 44 0x04>;
491 clocks = <&clks IMX6SL_CLK_USBPHY1>;
494 usbphy2: usbphy@020ca000 {
495 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
496 reg = <0x020ca000 0x1000>;
497 interrupts = <0 45 0x04>;
498 clocks = <&clks IMX6SL_CLK_USBPHY2>;
502 compatible = "fsl,sec-v4.0-mon", "simple-bus";
503 #address-cells = <1>;
505 ranges = <0 0x020cc000 0x4000>;
508 compatible = "fsl,sec-v4.0-mon-rtc-lp";
510 interrupts = <0 19 0x04 0 20 0x04>;
514 epit1: epit@020d0000 {
515 reg = <0x020d0000 0x4000>;
516 interrupts = <0 56 0x04>;
519 epit2: epit@020d4000 {
520 reg = <0x020d4000 0x4000>;
521 interrupts = <0 57 0x04>;
525 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
526 reg = <0x020d8000 0x4000>;
527 interrupts = <0 91 0x04 0 96 0x04>;
532 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
533 reg = <0x020dc000 0x4000>;
534 interrupts = <0 89 0x04>;
537 gpr: iomuxc-gpr@020e0000 {
538 compatible = "fsl,imx6sl-iomuxc-gpr",
539 "fsl,imx6q-iomuxc-gpr", "syscon";
540 reg = <0x020e0000 0x38>;
543 iomuxc: iomuxc@020e0000 {
544 compatible = "fsl,imx6sl-iomuxc";
545 reg = <0x020e0000 0x4000>;
548 pinctrl_ecspi1_1: ecspi1grp-1 {
550 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
551 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
552 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
558 pinctrl_fec_1: fecgrp-1 {
560 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
561 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
562 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
563 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
564 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
565 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
566 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
567 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
568 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
574 pinctrl_uart1_1: uart1grp-1 {
576 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
577 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
583 pinctrl_usbotg1_1: usbotg1grp-1 {
585 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
589 pinctrl_usbotg1_2: usbotg1grp-2 {
591 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
595 pinctrl_usbotg1_3: usbotg1grp-3 {
597 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
601 pinctrl_usbotg1_4: usbotg1grp-4 {
603 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
607 pinctrl_usbotg1_5: usbotg1grp-5 {
609 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
615 pinctrl_usbotg2_1: usbotg2grp-1 {
617 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
621 pinctrl_usbotg2_2: usbotg2grp-2 {
623 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
627 pinctrl_usbotg2_3: usbotg2grp-3 {
629 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
633 pinctrl_usbotg2_4: usbotg2grp-4 {
635 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
641 pinctrl_usdhc1_1: usdhc1grp-1 {
643 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
644 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
645 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
646 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
647 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
648 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
649 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
650 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
651 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
652 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
656 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
658 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
659 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
660 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
661 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
662 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
663 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
664 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
665 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
666 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
667 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
671 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
673 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
674 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
675 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
676 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
677 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
678 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
679 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
680 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
681 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
682 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
690 pinctrl_usdhc2_1: usdhc2grp-1 {
692 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
693 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
694 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
695 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
696 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
697 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
701 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
703 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
704 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
705 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
706 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
707 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
708 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
712 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
714 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
715 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
716 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
717 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
718 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
719 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
726 pinctrl_usdhc3_1: usdhc3grp-1 {
728 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
729 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
730 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
731 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
732 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
733 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
737 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
739 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
740 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
741 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
742 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
743 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
744 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
748 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
750 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
751 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
752 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
753 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
754 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
755 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
762 reg = <0x020e4000 0x4000>;
763 interrupts = <0 7 0x04>;
766 spdc: spdc@020e8000 {
767 reg = <0x020e8000 0x4000>;
768 interrupts = <0 6 0x04>;
771 sdma: sdma@020ec000 {
772 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
773 reg = <0x020ec000 0x4000>;
774 interrupts = <0 2 0x04>;
775 clocks = <&clks IMX6SL_CLK_SDMA>,
776 <&clks IMX6SL_CLK_SDMA>;
777 clock-names = "ipg", "ahb";
779 /* imx6sl reuses imx6q sdma firmware */
780 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
784 reg = <0x020f0000 0x4000>;
785 interrupts = <0 98 0x04>;
788 epdc: epdc@020f4000 {
789 reg = <0x020f4000 0x4000>;
790 interrupts = <0 97 0x04>;
793 lcdif: lcdif@020f8000 {
794 reg = <0x020f8000 0x4000>;
795 interrupts = <0 39 0x04>;
799 reg = <0x020fc000 0x4000>;
800 interrupts = <0 99 0x04>;
804 aips2: aips-bus@02100000 {
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
808 reg = <0x02100000 0x100000>;
811 usbotg1: usb@02184000 {
812 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
813 reg = <0x02184000 0x200>;
814 interrupts = <0 43 0x04>;
815 clocks = <&clks IMX6SL_CLK_USBOH3>;
816 fsl,usbphy = <&usbphy1>;
817 fsl,usbmisc = <&usbmisc 0>;
821 usbotg2: usb@02184200 {
822 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
823 reg = <0x02184200 0x200>;
824 interrupts = <0 42 0x04>;
825 clocks = <&clks IMX6SL_CLK_USBOH3>;
826 fsl,usbphy = <&usbphy2>;
827 fsl,usbmisc = <&usbmisc 1>;
832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
833 reg = <0x02184400 0x200>;
834 interrupts = <0 40 0x04>;
835 clocks = <&clks IMX6SL_CLK_USBOH3>;
836 fsl,usbmisc = <&usbmisc 2>;
840 usbmisc: usbmisc@02184800 {
842 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
843 reg = <0x02184800 0x200>;
844 clocks = <&clks IMX6SL_CLK_USBOH3>;
847 fec: ethernet@02188000 {
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
849 reg = <0x02188000 0x4000>;
850 interrupts = <0 114 0x04>;
851 clocks = <&clks IMX6SL_CLK_ENET_REF>,
852 <&clks IMX6SL_CLK_ENET_REF>;
853 clock-names = "ipg", "ahb";
857 usdhc1: usdhc@02190000 {
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
859 reg = <0x02190000 0x4000>;
860 interrupts = <0 22 0x04>;
861 clocks = <&clks IMX6SL_CLK_USDHC1>,
862 <&clks IMX6SL_CLK_USDHC1>,
863 <&clks IMX6SL_CLK_USDHC1>;
864 clock-names = "ipg", "ahb", "per";
869 usdhc2: usdhc@02194000 {
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
871 reg = <0x02194000 0x4000>;
872 interrupts = <0 23 0x04>;
873 clocks = <&clks IMX6SL_CLK_USDHC2>,
874 <&clks IMX6SL_CLK_USDHC2>,
875 <&clks IMX6SL_CLK_USDHC2>;
876 clock-names = "ipg", "ahb", "per";
881 usdhc3: usdhc@02198000 {
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 0x04>;
885 clocks = <&clks IMX6SL_CLK_USDHC3>,
886 <&clks IMX6SL_CLK_USDHC3>,
887 <&clks IMX6SL_CLK_USDHC3>;
888 clock-names = "ipg", "ahb", "per";
893 usdhc4: usdhc@0219c000 {
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
895 reg = <0x0219c000 0x4000>;
896 interrupts = <0 25 0x04>;
897 clocks = <&clks IMX6SL_CLK_USDHC4>,
898 <&clks IMX6SL_CLK_USDHC4>,
899 <&clks IMX6SL_CLK_USDHC4>;
900 clock-names = "ipg", "ahb", "per";
906 #address-cells = <1>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
909 reg = <0x021a0000 0x4000>;
910 interrupts = <0 36 0x04>;
911 clocks = <&clks IMX6SL_CLK_I2C1>;
916 #address-cells = <1>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
919 reg = <0x021a4000 0x4000>;
920 interrupts = <0 37 0x04>;
921 clocks = <&clks IMX6SL_CLK_I2C2>;
926 #address-cells = <1>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
929 reg = <0x021a8000 0x4000>;
930 interrupts = <0 38 0x04>;
931 clocks = <&clks IMX6SL_CLK_I2C3>;
935 mmdc: mmdc@021b0000 {
936 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
937 reg = <0x021b0000 0x4000>;
940 rngb: rngb@021b4000 {
941 reg = <0x021b4000 0x4000>;
942 interrupts = <0 5 0x04>;
945 weim: weim@021b8000 {
946 reg = <0x021b8000 0x4000>;
947 interrupts = <0 14 0x04>;
950 ocotp: ocotp@021bc000 {
951 compatible = "fsl,imx6sl-ocotp";
952 reg = <0x021bc000 0x4000>;
955 audmux: audmux@021d8000 {
956 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
957 reg = <0x021d8000 0x4000>;