arch/arm/boot/dts/imx6sx-sabreauto.dts

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "imx6sx.dtsi"
  12
  13 / {
  14         model = "Freescale i.MX6 SoloX Sabre Auto Board";
  15         compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
  16
  17         backlight2 {
  18                 compatible = "pwm-backlight";
  19                 pwms = <&pwm4 0 5000000>;
  20                 brightness-levels = <0 4 8 16 32 64 128 255>;
  21                 default-brightness-level = <6>;
  22                 fb-names = "mxs-lcdif1";
  23         };
  24
  25         clocks {
  26                 codec_osc: anaclk2 {
  27                         #clock-cells = <0>;
  28                         compatible = "fixed-clock";
  29                         clock-frequency = <24576000>;
  30                 };
  31         };
  32
  33         max7322_reset: max7322-reset {
  34                 compatible = "gpio-reset";
  35                 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  36                 reset-delay-us = <1>;
  37                 #reset-cells = <0>;
  38         };
  39
  40         hannstar_cabc {
  41                 compatible = "hannstar,cabc";
  42
  43                 lvds0 {
  44                         gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
  45                 };
  46         };
  47
  48         max7310_reset: max7310-reset {
  49                 compatible = "gpio-reset";
  50                 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  51                 reset-delay-us = <1>;
  52                 #reset-cells = <0>;
  53         };
  54
  55         memory {
  56                 reg = <0x80000000 0x80000000>;
  57         };
  58
  59         pxp_v4l2_out {
  60                 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  61                 status = "okay";
  62         };
  63
  64         regulators {
  65                 compatible = "simple-bus";
  66
  67                 reg_audio: cs42888_supply {
  68                         compatible = "regulator-fixed";
  69                         regulator-name = "cs42888_supply";
  70                         regulator-min-microvolt = <3300000>;
  71                         regulator-max-microvolt = <3300000>;
  72                         regulator-always-on;
  73                 };
  74
  75                 si4763_vio1: vio1_tnr {
  76                         compatible = "regulator-fixed";
  77                         regulator-name = "vio1";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         regulator-always-on;
  81                 };
  82
  83                 si4763_vio2: vio2_tnr {
  84                         compatible = "regulator-fixed";
  85                         regulator-name = "vio2";
  86                         regulator-min-microvolt = <3300000>;
  87                         regulator-max-microvolt = <3300000>;
  88                         regulator-always-on;
  89                 };
  90
  91                 si4763_vd: f3v3_tnr {
  92                         compatible = "regulator-fixed";
  93                         regulator-name = "vd";
  94                         regulator-min-microvolt = <3300000>;
  95                         regulator-max-microvolt = <3300000>;
  96                         regulator-always-on;
  97                 };
  98
  99                 si4763_va: f5v_tnr {
 100                         compatible = "regulator-fixed";
 101                         regulator-name = "va";
 102                         regulator-min-microvolt = <5000000>;
 103                         regulator-max-microvolt = <5000000>;
 104                         regulator-always-on;
 105                 };
 106
 107                 reg_lcd_3v3: lcd-3v3 {
 108                         compatible = "regulator-fixed";
 109                         regulator-name = "lcd-3v3";
 110                         gpio = <&gpio3 27 0>;
 111                         enable-active-high;
 112                         status = "disabled";
 113                 };
 114
 115                 reg_sd3_vmmc: sd3_vmmc{
 116                         compatible = "regulator-fixed";
 117                         regulator-name = "VCC_SD3";
 118                         regulator-min-microvolt = <3000000>;
 119                         regulator-max-microvolt = <3000000>;
 120                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
 121                         enable-active-high;
 122                 };
 123
 124                 reg_vref_3v3: regulator@0 {
 125                         compatible = "regulator-fixed";
 126                         regulator-name = "vref-3v3";
 127                         regulator-min-microvolt = <3300000>;
 128                         regulator-max-microvolt = <3300000>;
 129                 };
 130
 131                 reg_psu_5v: psu_5v0 {
 132                         compatible = "regulator-fixed";
 133                         regulator-name = "PSU-5V0";
 134                         regulator-min-microvolt = <5000000>;
 135                         regulator-max-microvolt = <5000000>;
 136                         regulator-boot-on;
 137                 };
 138
 139                 reg_usb_otg1_vbus: usb_otg1_vbus {
 140                         compatible = "regulator-fixed";
 141                         regulator-name = "usb_otg1_vbus";
 142                         regulator-min-microvolt = <5000000>;
 143                         regulator-max-microvolt = <5000000>;
 144                         gpio = <&gpio1 9 0>;
 145                         enable-active-high;
 146                 };
 147
 148                 reg_usb_otg2_vbus: usb_otg2_vbus {
 149                         compatible = "regulator-fixed";
 150                         regulator-name = "usb_otg2_vbus";
 151                         regulator-min-microvolt = <5000000>;
 152                         regulator-max-microvolt = <5000000>;
 153                         gpio = <&gpio1 12 0>;
 154                         enable-active-high;
 155                 };
 156         };
 157
 158         sound-cs42888 {
 159                 compatible = "fsl,imx6-sabreauto-cs42888",
 160                                 "fsl,imx-audio-cs42888";
 161                 model = "imx-cs42888";
 162                 esai-controller = <&esai>;
 163                 asrc-controller = <&asrc>;
 164                 audio-codec = <&codec>;
 165         };
 166
 167         sound-fm {
 168                 compatible = "fsl,imx-audio-si476x",
 169                            "fsl,imx-tuner-si476x";
 170                 model = "imx-radio-si4763";
 171
 172                 ssi-controller = <&ssi2>;
 173                 fm-controller = <&si476x_codec>;
 174                 mux-int-port = <2>;
 175                 mux-ext-port = <5>;
 176         };
 177
 178         sound-spdif {
 179                 compatible = "fsl,imx-audio-spdif";
 180                 model = "imx-spdif";
 181                 spdif-controller = <&spdif>;
 182                 spdif-in;
 183         };
 184 };
 185
 186 &iomuxc {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_hog>;
 189
 190         imx6x-sabreauto {
 191                 pinctrl_hog: hoggrp {
 192                         fsl,pins = <
 193                                 MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x17059
 194                                 MX6SX_PAD_USB_H_DATA__GPIO7_IO_10       0x17059
 195                                 MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19      0x17059
 196                                 MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22      0x80000000
 197                                 MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24      0x80000000
 198                                 MX6SX_PAD_SD2_CLK__GPIO6_IO_6           0x80000000
 199                                 MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23      0x80000000
 200                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY    0x10b0
 201                         >;
 202                 };
 203
 204                 pinctrl_audmux_3: audmux-3 {
 205                         fsl,pins = <
 206                                 MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC    0x130b0
 207                                 MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS   0x130b0
 208                                 MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD  0x130b0
 209                         >;
 210                 };
 211
 212                 pinctrl_enet1_1: enet1grp-1 {
 213                         fsl,pins = <
 214                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 215                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 216                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
 217                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 218                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 219                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 220                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 221                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 222                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 223                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 224                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 225                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 226                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 227                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 228                         >;
 229                 };
 230
 231                 pinctrl_enet2_1: enet2grp-1 {
 232                         fsl,pins = <
 233                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 234                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 235                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 236                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 237                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 238                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 239                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 240                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 241                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 242                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 243                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 244                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 245                         >;
 246                 };
 247
 248                 pinctrl_esai_2: esaigrp-2 {
 249                         fsl,pins = <
 250                                 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
 251                                 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
 252                                 MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
 253                                 MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
 254                                 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
 255                                 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
 256                                 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
 257                                 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
 258                                 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
 259                                 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
 260                         >;
 261                 };
 262
 263                 pinctrl_flexcan1_1: flexcan1grp-1 {
 264                         fsl,pins = <
 265                                 MX6SX_PAD_QSPI1B_DQS__CAN1_TX   0x1b020
 266                                 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
 267                         >;
 268                 };
 269
 270                 pinctrl_flexcan2_1: flexcan2grp-1 {
 271                         fsl,pins = <
 272                                 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
 273                                 MX6SX_PAD_QSPI1A_DQS__CAN2_TX   0x1b020
 274                         >;
 275                 };
 276
 277                 pinctrl_gpmi_nand_1: gpmi-nand-1 {
 278                         fsl,pins = <
 279                                 MX6SX_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
 280                                 MX6SX_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
 281                                 MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
 282                                 MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
 283                                 MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
 284                                 MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
 285                                 MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
 286                                 MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
 287                                 MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
 288                                 MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
 289                                 MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
 290                                 MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
 291                                 MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
 292                                 MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
 293                                 MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
 294                                 MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
 295                         >;
 296                 };
 297
 298                 pinctrl_i2c2_1: i2c2grp-1 {
 299                         fsl,pins = <
 300                                 MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
 301                                 MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
 302                         >;
 303                 };
 304
 305                 pinctrl_i2c3_2: i2c3grp-2 {
 306                         fsl,pins = <
 307                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 308                                 MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 309                         >;
 310                 };
 311
 312                 pinctrl_mlb_2: mlbgrp-2 {
 313                         fsl,pins = <
 314                                 MX6SX_PAD_ENET2_RX_CLK__MLB_DATA        0x31
 315                                 MX6SX_PAD_ENET2_CRS__MLB_SIG            0x31
 316                                 MX6SX_PAD_ENET2_TX_CLK__MLB_CLK         0x31
 317                         >;
 318                 };
 319
 320                 pinctrl_pwm4_0: pwm4grp-0 {
 321                         fsl,pins = <
 322                                 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
 323                         >;
 324                 };
 325
 326                 pinctrl_qspi1_1: qspi1grp_1 {
 327                         fsl,pins = <
 328                                 MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  0x70a1
 329                                 MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1  0x70a1
 330                                 MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2  0x70a1
 331                                 MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3  0x70a1
 332                                 MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK     0x70a1
 333                                 MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B   0x70a1
 334                                 MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0  0x70a1
 335                                 MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1  0x70a1
 336                                 MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2  0x70a1
 337                                 MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3  0x70a1
 338                                 MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK     0x70a1
 339                                 MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B   0x70a1
 340                         >;
 341                 };
 342
 343                 pinctrl_spdif_3: spdifgrp-3 {
 344                         fsl,pins = <
 345                                 MX6SX_PAD_ENET2_COL__SPDIF_IN           0x1b0b0
 346                         >;
 347                 };
 348
 349                 pinctrl_uart1_1: uart1grp-1 {
 350                         fsl,pins = <
 351                                 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
 352                                 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
 353                         >;
 354                 };
 355
 356                 pinctrl_uart2_1: uart2grp-1 {
 357                         fsl,pins = <
 358                                 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
 359                                 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
 360                         >;
 361                 };
 362
 363                 pinctrl_uart5_1: uart5grp-1 {
 364                         fsl,pins = <
 365                                 MX6SX_PAD_KEY_ROW3__UART5_RX    0x1b0b1
 366                                 MX6SX_PAD_KEY_COL3__UART5_TX    0x1b0b1
 367                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
 368                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
 369                         >;
 370                 };
 371
 372                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 373                         fsl,pins = <
 374                                 MX6SX_PAD_KEY_ROW3__UART5_TX    0x1b0b1
 375                                 MX6SX_PAD_KEY_COL3__UART5_RX    0x1b0b1
 376                                 MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
 377                                 MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
 378                         >;
 379                 };
 380
 381                 pinctrl_usbotg1_1: usbotg1grp-1 {
 382                         fsl,pins = <
 383                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
 384                         >;
 385                 };
 386
 387                 pinctrl_usdhc3_1: usdhc3grp-1 {
 388                         fsl,pins = <
 389                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD     0x17059
 390                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK     0x10059
 391                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
 392                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
 393                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
 394                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
 395                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
 396                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
 397                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
 398                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
 399                         >;
 400                 };
 401
 402                 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
 403                         fsl,pins = <
 404                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD     0x170b9
 405                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK     0x100b9
 406                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
 407                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
 408                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
 409                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
 410                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
 411                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
 412                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
 413                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
 414                         >;
 415                 };
 416
 417                 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
 418                         fsl,pins = <
 419                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD     0x170f9
 420                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK     0x100f9
 421                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
 422                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
 423                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
 424                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
 425                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
 426                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
 427                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
 428                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
 429                         >;
 430                 };
 431
 432                 pinctrl_usdhc4_3: usdhc4grp-3 {
 433                         fsl,pins = <
 434                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17071
 435                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10071
 436                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
 437                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
 438                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
 439                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
 440                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
 441                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
 442                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
 443                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
 444                         >;
 445                 };
 446         };
 447 };
 448
 449 &adc1 {
 450         vref-supply = <&reg_vref_3v3>;
 451         status = "okay";
 452 };
 453
 454 &adc2 {
 455         vref-supply = <&reg_vref_3v3>;
 456         status = "okay";
 457 };
 458
 459 &audmux {
 460         pinctrl-names = "default";
 461         pinctrl-0 = <&pinctrl_audmux_3>;
 462         status = "okay";
 463 };
 464
 465 &clks {
 466         assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
 467                           <&clks IMX6SX_PLL4_BYPASS>,
 468                           <&clks IMX6SX_CLK_PLL4_POST_DIV>;
 469         assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
 470                                 <&clks IMX6SX_PLL4_BYPASS_SRC>;
 471         assigned-clock-rates = <0>, <0>, <24576000>;
 472 };
 473
 474 &csi2 {
 475         status = "okay";
 476         port {
 477                 csi2_ep: endpoint {
 478                         remote-endpoint = <&vadc_ep>;
 479                 };
 480         };
 481 };
 482
 483 &dcic1 {
 484         dcic_id = <0>;
 485         dcic_mux = "dcic-lcdif1";
 486         status = "okay";
 487 };
 488
 489 &dcic2 {
 490         dcic_id = <1>;
 491         dcic_mux = "dcic-lvds";
 492         status = "okay";
 493 };
 494
 495 &esai {
 496         pinctrl-names = "default";
 497         pinctrl-0 = <&pinctrl_esai_2>;
 498         assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
 499                           <&clks IMX6SX_CLK_ESAI_EXTAL>;
 500         assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
 501         assigned-clock-rates = <0>, <24576000>;
 502         status = "okay";
 503 };
 504
 505 &fec1 {
 506         pinctrl-names = "default";
 507         pinctrl-0 = <&pinctrl_enet1_1>;
 508         phy-mode = "rgmii";
 509         phy-handle = <&ethphy1>;
 510         fsl,num_tx_queues=<3>;
 511         fsl,num_rx_queues=<3>;
 512         pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
 513         fsl,magic-packet;
 514         status = "okay";
 515
 516         mdio {
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519
 520                 ethphy0: ethernet-phy@0 {
 521                         compatible = "ethernet-phy-ieee802.3-c22";
 522                         reg = <0>;
 523                 };
 524
 525                 ethphy1: ethernet-phy@1 {
 526                         compatible = "ethernet-phy-ieee802.3-c22";
 527                         reg = <1>;
 528                 };
 529         };
 530 };
 531
 532 &fec2 {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pinctrl_enet2_1>;
 535         phy-mode = "rgmii";
 536         phy-handle = <&ethphy0>;
 537         fsl,num_tx_queues=<3>;
 538         fsl,num_rx_queues=<3>;
 539         fsl,magic-packet;
 540         status = "okay";
 541 };
 542
 543 &flexcan1 {
 544         pinctrl-names = "default";
 545         pinctrl-0 = <&pinctrl_flexcan1_1>;
 546         trx-en-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
 547         trx-stby-gpio = <&max7310_b 3 GPIO_ACTIVE_HIGH>;
 548         status = "okay";
 549 };
 550
 551 &flexcan2 {
 552         pinctrl-names = "default";
 553         pinctrl-0 = <&pinctrl_flexcan2_1>;
 554         trx-en-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
 555         trx-stby-gpio = <&max7310_b 3 GPIO_ACTIVE_HIGH>;
 556         status = "okay";
 557 };
 558
 559 &i2c2 {
 560         clock-frequency = <100000>;
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pinctrl_i2c2_1>;
 563         status = "okay";
 564
 565         egalax_ts@04 {
 566                 compatible = "eeti,egalax_ts";
 567                 reg = <0x04>;
 568                 interrupt-parent = <&gpio6>;
 569                 interrupts = <22 2>;
 570                 wakeup-gpios = <&gpio6 22 0>;
 571         };
 572
 573         codec: cs42888@048 {
 574                 compatible = "cirrus,cs42888";
 575                 reg = <0x048>;
 576                 clocks = <&codec_osc 0>;
 577                 clock-names = "mclk";
 578                 VA-supply = <&reg_audio>;
 579                 VD-supply = <&reg_audio>;
 580                 VLS-supply = <&reg_audio>;
 581                 VLC-supply = <&reg_audio>;
 582         };
 583
 584         si4763: si4763@63 {
 585                 compatible = "si4761";
 586                 reg = <0x63>;
 587                 va-supply = <&si4763_va>;
 588                 vd-supply = <&si4763_vd>;
 589                 vio1-supply = <&si4763_vio1>;
 590                 vio2-supply = <&si4763_vio2>;
 591                 revision-a10; /* set to default A10 compatible command set */
 592
 593                 si476x_codec: si476x-codec {
 594                         compatible = "si476x-codec";
 595                 };
 596         };
 597
 598         max7322: gpio@68 {
 599                 compatible = "maxim,max7322";
 600                 reg = <0x68>;
 601                 gpio-controller;
 602                 #gpio-cells = <2>;
 603                 resets = <&max7322_reset>;
 604         };
 605
 606         pmic: pfuze100@08 {
 607                 compatible = "fsl,pfuze100";
 608                 reg = <0x08>;
 609
 610                 regulators {
 611                         sw1a_reg: sw1ab {
 612                                 regulator-min-microvolt = <300000>;
 613                                 regulator-max-microvolt = <1875000>;
 614                                 regulator-boot-on;
 615                                 regulator-always-on;
 616                                 regulator-ramp-delay = <6250>;
 617                         };
 618
 619                         sw1c_reg: sw1c {
 620                                 regulator-min-microvolt = <300000>;
 621                                 regulator-max-microvolt = <1875000>;
 622                                 regulator-boot-on;
 623                                 regulator-always-on;
 624                                 regulator-ramp-delay = <6250>;
 625                         };
 626
 627                         sw2_reg: sw2 {
 628                                 regulator-min-microvolt = <800000>;
 629                                 regulator-max-microvolt = <3300000>;
 630                                 regulator-boot-on;
 631                                 regulator-always-on;
 632                         };
 633
 634                         sw3a_reg: sw3a {
 635                                 regulator-min-microvolt = <400000>;
 636                                 regulator-max-microvolt = <1975000>;
 637                                 regulator-boot-on;
 638                                 regulator-always-on;
 639                         };
 640
 641                         sw3b_reg: sw3b {
 642                                 regulator-min-microvolt = <400000>;
 643                                 regulator-max-microvolt = <1975000>;
 644                                 regulator-boot-on;
 645                                 regulator-always-on;
 646                         };
 647
 648                         sw4_reg: sw4 {
 649                                 regulator-min-microvolt = <800000>;
 650                                 regulator-max-microvolt = <3300000>;
 651                         };
 652
 653                         swbst_reg: swbst {
 654                                 regulator-min-microvolt = <5000000>;
 655                                 regulator-max-microvolt = <5150000>;
 656                         };
 657
 658                         snvs_reg: vsnvs {
 659                                 regulator-min-microvolt = <1000000>;
 660                                 regulator-max-microvolt = <3000000>;
 661                                 regulator-boot-on;
 662                                 regulator-always-on;
 663                         };
 664
 665                         vref_reg: vrefddr {
 666                                 regulator-boot-on;
 667                                 regulator-always-on;
 668                         };
 669
 670                         vgen1_reg: vgen1 {
 671                                 regulator-min-microvolt = <800000>;
 672                                 regulator-max-microvolt = <1550000>;
 673                                 regulator-always-on;
 674                         };
 675
 676                         vgen2_reg: vgen2 {
 677                                 regulator-min-microvolt = <800000>;
 678                                 regulator-max-microvolt = <1550000>;
 679                         };
 680
 681                         vgen3_reg: vgen3 {
 682                                 regulator-min-microvolt = <1800000>;
 683                                 regulator-max-microvolt = <3300000>;
 684                                 regulator-always-on;
 685                         };
 686
 687                         vgen4_reg: vgen4 {
 688                                 regulator-min-microvolt = <1800000>;
 689                                 regulator-max-microvolt = <3300000>;
 690                                 regulator-always-on;
 691                         };
 692
 693                         vgen5_reg: vgen5 {
 694                                 regulator-min-microvolt = <1800000>;
 695                                 regulator-max-microvolt = <3300000>;
 696                                 regulator-always-on;
 697                         };
 698
 699                         vgen6_reg: vgen6 {
 700                                 regulator-min-microvolt = <1800000>;
 701                                 regulator-max-microvolt = <3300000>;
 702                                 regulator-always-on;
 703                         };
 704                 };
 705         };
 706 };
 707
 708 &spdif {
 709         pinctrl-names = "default";
 710         pinctrl-0 = <&pinctrl_spdif_3>;
 711         status = "okay";
 712 };
 713
 714 &ssi2 {
 715         fsl,mode = "i2s-master";
 716         status = "okay";
 717 };
 718
 719 &i2c3 {
 720         clock-frequency = <100000>;
 721         pinctrl-names = "default";
 722         pinctrl-0 = <&pinctrl_i2c3_2>;
 723         status = "okay";
 724
 725         max7310_a: gpio@30 {
 726                 compatible = "maxim,max7310";
 727                 reg = <0x30>;
 728                 gpio-controller;
 729                 #gpio-cells = <2>;
 730                 resets = <&max7310_reset>;
 731         };
 732
 733         max7310_b: gpio@32 {
 734                 compatible = "maxim,max7310";
 735                 reg = <0x32>;
 736                 gpio-controller;
 737                 #gpio-cells = <2>;
 738                 resets = <&max7310_reset>;
 739         };
 740
 741         mma8451@1c {
 742                 compatible = "fsl,mma8451";
 743                 reg = <0x1c>;
 744                 position = <7>;
 745                 interrupt-parent = <&gpio3>;
 746                 interrupts = <24 8>;
 747                 interrupt-route = <1>;
 748         };
 749
 750         mag3110@0e {
 751                 compatible = "fsl,mag3110";
 752                 reg = <0x0e>;
 753                 position = <2>;
 754                 interrupt-parent = <&gpio6>;
 755                 interrupts = <6 1>;
 756         };
 757
 758         isl29023@44 {
 759                 compatible = "fsl,isl29023";
 760                 reg = <0x44>;
 761                 rext = <499>;
 762                 interrupt-parent = <&gpio3>;
 763                 interrupts = <23 2>;
 764         };
 765 };
 766
 767 &lcdif2 {
 768         display = <&display1>;
 769         disp-dev = "ldb";
 770         status = "okay";
 771
 772         display1: display {
 773                 bits-per-pixel = <16>;
 774                 bus-width = <18>;
 775         };
 776 };
 777
 778 &ldb {
 779         status = "okay";
 780
 781         lvds-channel@0 {
 782                 fsl,data-mapping = "spwg";
 783                 fsl,data-width = <18>;
 784                 crtc = "lcdif2";
 785                 status = "okay";
 786
 787                 display-timings {
 788                         native-mode = <&timing1>;
 789                         timing1: hsd100pxn1 {
 790                                 clock-frequency = <65000000>;
 791                                 hactive = <1024>;
 792                                 vactive = <768>;
 793                                 hback-porch = <220>;
 794                                 hfront-porch = <40>;
 795                                 vback-porch = <21>;
 796                                 vfront-porch = <7>;
 797                                 hsync-len = <60>;
 798                                 vsync-len = <10>;
 799                         };
 800                 };
 801         };
 802 };
 803
 804 &mlb {
 805         pinctrl-names = "default";
 806         pinctrl-0 = <&pinctrl_mlb_2>;
 807         status = "okay";
 808 };
 809
 810 &pcie {
 811         reset-gpio = <&max7310_b 3 0>;
 812         status = "okay";
 813 };
 814
 815 &uart1 {
 816         pinctrl-names = "default";
 817         pinctrl-0 = <&pinctrl_uart1_1>;
 818         status = "okay";
 819 };
 820
 821 &uart2 {
 822         pinctrl-names = "default";
 823         pinctrl-0 = <&pinctrl_uart2_1>;
 824         status = "okay";
 825 };
 826
 827 &uart5 { /* for bluetooth */
 828         pinctrl-names = "default";
 829         pinctrl-0 = <&pinctrl_uart5_1>;
 830         fsl,uart-has-rtscts;
 831         status = "okay";
 832         /* for DTE mode, add below change */
 833         /* fsl,dte-mode;*/
 834         /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 835 };
 836
 837 &usbotg1 {
 838         vbus-supply = <&reg_usb_otg1_vbus>;
 839         pinctrl-names = "default";
 840         pinctrl-0 = <&pinctrl_usbotg1_1>;
 841         imx6-usb-charger-detection;
 842         status = "okay";
 843 };
 844
 845 &usbotg2 {
 846         vbus-supply = <&reg_usb_otg2_vbus>;
 847         dr_mode = "host";
 848         status = "okay";
 849 };
 850
 851 &usdhc3 {
 852         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 853         pinctrl-0 = <&pinctrl_usdhc3_1>;
 854         pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
 855         pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
 856         bus-width = <8>;
 857         cd-gpios = <&gpio7 10 0>;
 858         wp-gpios = <&gpio3 19 0>;
 859         keep-power-in-suspend;
 860         enable-sdio-wakeup;
 861         vmmc-supply = <&reg_sd3_vmmc>;
 862         status = "okay";
 863 };
 864
 865 &usdhc4 {
 866         pinctrl-names = "default";
 867         pinctrl-0 = <&pinctrl_usdhc4_3>;
 868         bus-width = <8>;
 869         cd-gpios = <&gpio7 11 0>;
 870         no-1-8-v;
 871         keep-power-in-suspend;
 872         enable-sdio-wakup;
 873         status = "okay";
 874 };
 875
 876 &pwm4 {
 877         pinctrl-names = "default";
 878         pinctrl-0 = <&pinctrl_pwm4_0>;
 879         status = "okay";
 880 };
 881
 882 &pxp {
 883         status = "okay";
 884 };
 885
 886 &qspi1 {
 887         pinctrl-names = "default";
 888         pinctrl-0 = <&pinctrl_qspi1_1>;
 889         /* only map 128MB */
 890         reg = <0x021e0000 0x4000>, <0x60000000 0x8000000>;
 891         status = "okay";
 892
 893         flash0: n25q256a@0 {
 894                 #address-cells = <1>;
 895                 #size-cells = <1>;
 896                 compatible = "micron,n25q256a";
 897                 spi-max-frequency = <53000000>;
 898                 reg = <0>;
 899         };
 900
 901         flash1: n25q256a@1 {
 902                 #address-cells = <1>;
 903                 #size-cells = <1>;
 904                 compatible = "micron,n25q256a";
 905                 spi-max-frequency = <53000000>;
 906                 reg = <1>;
 907         };
 908 };
 909
 910 &gpmi {
 911         pinctrl-names = "default";
 912         pinctrl-0 = <&pinctrl_gpmi_nand_1>;
 913         status = "okay";
 914 };
 915
 916 &vadc {
 917         vadc_in = <0>;
 918         csi_id = <1>;
 919         status = "okay";
 920         port {
 921                 vadc_ep: endpoint {
 922                         remote-endpoint = <&csi2_ep>;
 923                 };
 924         };
 925 };
 926