arch/arm/boot/dts/imx6sx-sdb.dts

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sx.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloX SDB Board";
  16         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x80000000 0x40000000>;
  24         };
  25
  26         backlight1 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm3 0 5000000>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 fb-names = "mxs-lcdif0";
  32         };
  33
  34         backlight2 {
  35                 compatible = "pwm-backlight";
  36                 pwms = <&pwm4 0 5000000>;
  37                 brightness-levels = <0 4 8 16 32 64 128 255>;
  38                 default-brightness-level = <6>;
  39                 fb-names = "mxs-lcdif1";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_gpio_keys>;
  46
  47                 volume-up {
  48                         label = "Volume Up";
  49                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  50                         linux,code = <KEY_VOLUMEUP>;
  51                 };
  52
  53                 volume-down {
  54                         label = "Volume Down";
  55                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_VOLUMEDOWN>;
  57                 };
  58         };
  59
  60         hannstar_cabc {
  61                 compatible = "hannstar,cabc";
  62
  63                 lvds0 {
  64                         gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  65                 };
  66         };
  67
  68         pxp_v4l2_out {
  69                 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  70                 status = "okay";
  71         };
  72
  73         regulators {
  74                 compatible = "simple-bus";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 reg_lcd_3v3: lcd-3v3 {
  79                         compatible = "regulator-fixed";
  80                         regulator-name = "lcd-3v3";
  81                         gpio = <&gpio3 27 0>;
  82                         enable-active-high;
  83                         status = "disabled";
  84                 };
  85
  86                 vcc_sd3: regulator@0 {
  87                         compatible = "regulator-fixed";
  88                         reg = <0>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_vcc_sd3>;
  91                         regulator-name = "VCC_SD3";
  92                         regulator-min-microvolt = <3000000>;
  93                         regulator-max-microvolt = <3000000>;
  94                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  95                         enable-active-high;
  96                 };
  97
  98                 reg_psu_5v: regulator@1 {
  99                         compatible = "regulator-fixed";
 100                         reg = <1>;
 101                         regulator-name = "PSU-5V0";
 102                         regulator-min-microvolt = <5000000>;
 103                         regulator-max-microvolt = <5000000>;
 104                         regulator-boot-on;
 105                 };
 106
 107                 reg_vref_3v3: regulator@2 {
 108                         compatible = "regulator-fixed";
 109                         regulator-name = "vref-3v3";
 110                         regulator-min-microvolt = <3300000>;
 111                         regulator-max-microvolt = <3300000>;
 112                 };
 113
 114                 reg_usb_otg1_vbus: regulator@3 {
 115                         compatible = "regulator-fixed";
 116                         reg = <3>;
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&pinctrl_usb_otg1>;
 119                         regulator-name = "usb_otg1_vbus";
 120                         regulator-min-microvolt = <5000000>;
 121                         regulator-max-microvolt = <5000000>;
 122                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                 };
 125
 126                 reg_usb_otg2_vbus: regulator@4 {
 127                         compatible = "regulator-fixed";
 128                         reg = <4>;
 129                         pinctrl-names = "default";
 130                         pinctrl-0 = <&pinctrl_usb_otg2>;
 131                         regulator-name = "usb_otg2_vbus";
 132                         regulator-min-microvolt = <5000000>;
 133                         regulator-max-microvolt = <5000000>;
 134                         gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 135                         enable-active-high;
 136                 };
 137
 138                 reg_pcie: regulator@5 {
 139                         compatible = "regulator-fixed";
 140                         reg = <5>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_pcie_reg>;
 143                         regulator-name = "MPCIE_3V3";
 144                         regulator-min-microvolt = <3300000>;
 145                         regulator-max-microvolt = <3300000>;
 146                         gpio = <&gpio2 1 0>;
 147                         regulator-always-on;
 148                         enable-active-high;
 149                 };
 150         };
 151
 152         sound {
 153                 compatible = "fsl,imx6q-sabresd-wm8962",
 154                            "fsl,imx-audio-wm8962";
 155                 model = "wm8962-audio";
 156                 cpu-dai = <&ssi2>;
 157                 audio-codec = <&codec>;
 158                 audio-routing =
 159                         "Headphone Jack", "HPOUTL",
 160                         "Headphone Jack", "HPOUTR",
 161                         "Ext Spk", "SPKOUTL",
 162                         "Ext Spk", "SPKOUTR",
 163                         "AMIC", "MICBIAS",
 164                         "IN3R", "AMIC";
 165                 mux-int-port = <2>;
 166                 mux-ext-port = <6>;
 167                 hp-det-gpios = <&gpio1 17 1>;
 168         };
 169
 170         sound-spdif {
 171                 compatible = "fsl,imx-audio-spdif",
 172                            "fsl,imx6sx-sdb-spdif";
 173                 model = "imx-spdif";
 174                 spdif-controller = <&spdif>;
 175                 spdif-out;
 176         };
 177 };
 178
 179 &adc1 {
 180         vref-supply = <&reg_vref_3v3>;
 181         status = "okay";
 182 };
 183
 184 &adc2 {
 185         vref-supply = <&reg_vref_3v3>;
 186         status = "okay";
 187 };
 188
 189 &audmux {
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_audmux>;
 192         status = "okay";
 193 };
 194
 195 &csi1 {
 196         status = "okay";
 197
 198         port {
 199                 csi1_ep: endpoint {
 200                         remote-endpoint = <&ov564x_ep>;
 201                 };
 202         };
 203 };
 204
 205 &csi2 {
 206         status = "okay";
 207         port {
 208                 csi2_ep: endpoint {
 209                         remote-endpoint = <&vadc_ep>;
 210                 };
 211         };
 212 };
 213
 214 &lcdif1 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_lcdif_dat
 217                      &pinctrl_lcdif_ctrl>;
 218         lcd-supply = <&reg_lcd_3v3>;
 219         display = <&display0>;
 220         status = "disabled";
 221
 222         display0: display {
 223                 bits-per-pixel = <16>;
 224                 bus-width = <24>;
 225
 226                 display-timings {
 227                         native-mode = <&timing0>;
 228                         timing0: timing0 {
 229                                 clock-frequency = <33500000>;
 230                                 hactive = <800>;
 231                                 vactive = <480>;
 232                                 hback-porch = <89>;
 233                                 hfront-porch = <164>;
 234                                 vback-porch = <23>;
 235                                 vfront-porch = <10>;
 236                                 hsync-len = <10>;
 237                                 vsync-len = <10>;
 238                                 hsync-active = <0>;
 239                                 vsync-active = <0>;
 240                                 de-active = <1>;
 241                                 pixelclk-active = <0>;
 242                         };
 243                 };
 244         };
 245 };
 246
 247 &lcdif2 {
 248         display = <&display1>;
 249         disp-dev = "ldb";
 250         status = "okay";
 251
 252         display1: display {
 253                 bits-per-pixel = <16>;
 254                 bus-width = <18>;
 255         };
 256 };
 257
 258 &ldb {
 259         status = "okay";
 260
 261         lvds-channel@0 {
 262                 fsl,data-mapping = "spwg";
 263                 fsl,data-width = <18>;
 264                 crtc = "lcdif2";
 265                 status = "okay";
 266
 267                 display-timings {
 268                         native-mode = <&timing1>;
 269                         timing1: hsd100pxn1 {
 270                                 clock-frequency = <65000000>;
 271                                 hactive = <1024>;
 272                                 vactive = <768>;
 273                                 hback-porch = <220>;
 274                                 hfront-porch = <40>;
 275                                 vback-porch = <21>;
 276                                 vfront-porch = <7>;
 277                                 hsync-len = <60>;
 278                                 vsync-len = <10>;
 279                         };
 280                 };
 281         };
 282 };
 283
 284 &pwm3 {
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_pwm3>;
 287         status = "okay";
 288 };
 289
 290 &pwm4 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_pwm4>;
 293         status = "okay";
 294 };
 295
 296 &dcic1 {
 297         dcic_id = <0>;
 298         dcic_mux = "dcic-lcdif1";
 299         status = "okay";
 300 };
 301
 302 &dcic2 {
 303         dcic_id = <1>;
 304         dcic_mux = "dcic-lvds";
 305         status = "okay";
 306 };
 307
 308 &fec1 {
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_enet1>;
 311         pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
 312         phy-mode = "rgmii";
 313         fsl,num_tx_queues=<3>;
 314         fsl,num_rx_queues=<3>;
 315         status = "okay";
 316 };
 317
 318 &fec2 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_enet2>;
 321         phy-mode = "rgmii";
 322         fsl,num_tx_queues=<3>;
 323         fsl,num_rx_queues=<3>;
 324         status = "okay";
 325 };
 326
 327 &flexcan1 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_flexcan1>;
 330         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 331         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 332         status = "okay";
 333 };
 334
 335 &flexcan2 {
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_flexcan2>;
 338         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 339         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 340         status = "okay";
 341 };
 342
 343 &pcie {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_pcie>;
 346         reset-gpio = <&gpio2 0 0>;
 347         status = "okay";
 348 };
 349
 350 &qspi2 {
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_qspi2_1>;
 353         status = "okay";
 354
 355         flash0: s25fl128s@0 {
 356                 #address-cells = <1>;
 357                 #size-cells = <1>;
 358                 compatible = "spansion,s25fl128s";
 359                 spi-max-frequency = <66000000>;
 360                 spi-nor,ddr-quad-read-dummy = <6>;
 361                 reg = <0>;
 362         };
 363
 364         flash1: s25fl128s@1 {
 365                 #address-cells = <1>;
 366                 #size-cells = <1>;
 367                 compatible = "spansion,s25fl128s";
 368                 spi-max-frequency = <66000000>;
 369                 spi-nor,ddr-quad-read-dummy = <6>;
 370                 reg = <1>;
 371         };
 372 };
 373
 374 &pxp {
 375         status = "okay";
 376 };
 377
 378 &sai1 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_sai1>;
 381         status = "disabled";
 382 };
 383
 384 &spdif {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&pinctrl_spdif>;
 387         status = "okay";
 388 };
 389
 390 &ssi2 {
 391         status = "okay";
 392 };
 393
 394 &uart1 {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_uart1>;
 397         status = "okay";
 398 };
 399
 400 &uart5 { /* for bluetooth */
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_uart5>;
 403         fsl,uart-has-rtscts;
 404         status = "okay";
 405         /* for DTE mode, add below change */
 406         /* fsl,dte-mode;*/
 407         /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 408 };
 409
 410 &usbotg1 {
 411         vbus-supply = <&reg_usb_otg1_vbus>;
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 414         status = "okay";
 415 };
 416
 417 &usbotg2 {
 418         vbus-supply = <&reg_usb_otg2_vbus>;
 419         dr_mode = "host";
 420         status = "okay";
 421 };
 422
 423 &usdhc2 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_usdhc2>;
 426         non-removable;
 427         no-1-8-v;
 428         keep-power-in-suspend;
 429         enable-sdio-wakeup;
 430         status = "okay";
 431 };
 432
 433 &usdhc3 {
 434         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 435         pinctrl-0 = <&pinctrl_usdhc3>;
 436         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 437         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 438         bus-width = <8>;
 439         cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 440         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 441         keep-power-in-suspend;
 442         enable-sdio-wakeup;
 443         vmmc-supply = <&vcc_sd3>;
 444         status = "okay";
 445 };
 446
 447 &usdhc4 {
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&pinctrl_usdhc4>;
 450         cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
 451         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 452         status = "okay";
 453 };
 454
 455 &i2c1 {
 456         clock-frequency = <100000>;
 457         pinctrl-names = "default";
 458         pinctrl-0 = <&pinctrl_i2c1>;
 459         status = "okay";
 460
 461         pmic: pfuze100@08 {
 462                 compatible = "fsl,pfuze100";
 463                 reg = <0x08>;
 464
 465                 regulators {
 466                         sw1a_reg: sw1ab {
 467                                 regulator-min-microvolt = <300000>;
 468                                 regulator-max-microvolt = <1875000>;
 469                                 regulator-boot-on;
 470                                 regulator-always-on;
 471                                 regulator-ramp-delay = <6250>;
 472                         };
 473
 474                         sw1c_reg: sw1c {
 475                                 regulator-min-microvolt = <300000>;
 476                                 regulator-max-microvolt = <1875000>;
 477                                 regulator-boot-on;
 478                                 regulator-always-on;
 479                                 regulator-ramp-delay = <6250>;
 480                         };
 481
 482                         sw2_reg: sw2 {
 483                                 regulator-min-microvolt = <800000>;
 484                                 regulator-max-microvolt = <3300000>;
 485                                 regulator-boot-on;
 486                                 regulator-always-on;
 487                         };
 488
 489                         sw3a_reg: sw3a {
 490                                 regulator-min-microvolt = <400000>;
 491                                 regulator-max-microvolt = <1975000>;
 492                                 regulator-boot-on;
 493                                 regulator-always-on;
 494                         };
 495
 496                         sw3b_reg: sw3b {
 497                                 regulator-min-microvolt = <400000>;
 498                                 regulator-max-microvolt = <1975000>;
 499                                 regulator-boot-on;
 500                                 regulator-always-on;
 501                         };
 502
 503                         sw4_reg: sw4 {
 504                                 regulator-min-microvolt = <800000>;
 505                                 regulator-max-microvolt = <3300000>;
 506                         };
 507
 508                         swbst_reg: swbst {
 509                                 regulator-min-microvolt = <5000000>;
 510                                 regulator-max-microvolt = <5150000>;
 511                         };
 512
 513                         snvs_reg: vsnvs {
 514                                 regulator-min-microvolt = <1000000>;
 515                                 regulator-max-microvolt = <3000000>;
 516                                 regulator-boot-on;
 517                                 regulator-always-on;
 518                         };
 519
 520                         vref_reg: vrefddr {
 521                                 regulator-boot-on;
 522                                 regulator-always-on;
 523                         };
 524
 525                         vgen1_reg: vgen1 {
 526                                 regulator-min-microvolt = <800000>;
 527                                 regulator-max-microvolt = <1550000>;
 528                                 regulator-always-on;
 529                         };
 530
 531                         vgen2_reg: vgen2 {
 532                                 regulator-min-microvolt = <800000>;
 533                                 regulator-max-microvolt = <1550000>;
 534                         };
 535
 536                         vgen3_reg: vgen3 {
 537                                 regulator-min-microvolt = <1800000>;
 538                                 regulator-max-microvolt = <3300000>;
 539                                 regulator-always-on;
 540                         };
 541
 542                         vgen4_reg: vgen4 {
 543                                 regulator-min-microvolt = <1800000>;
 544                                 regulator-max-microvolt = <3300000>;
 545                                 regulator-always-on;
 546                         };
 547
 548                         vgen5_reg: vgen5 {
 549                                 regulator-min-microvolt = <1800000>;
 550                                 regulator-max-microvolt = <3300000>;
 551                                 regulator-always-on;
 552                         };
 553
 554                         vgen6_reg: vgen6 {
 555                                 regulator-min-microvolt = <1800000>;
 556                                 regulator-max-microvolt = <3300000>;
 557                                 regulator-always-on;
 558                         };
 559                 };
 560         };
 561
 562         ov564x: ov564x@3c {
 563                 compatible = "ovti,ov564x";
 564                 reg = <0x3c>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&pinctrl_csi_0>;
 567                 clocks = <&clks IMX6SX_CLK_CSI>;
 568                 clock-names = "csi_mclk";
 569                 AVDD-supply = <&vgen3_reg>;  /* 2.8v */
 570                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 571                 pwn-gpios = <&gpio3 28 1>;
 572                 rst-gpios = <&gpio3 27 0>;
 573                 csi_id = <0>;
 574                 mclk = <24000000>;
 575                 mclk_source = <0>;
 576                 port {
 577                         ov564x_ep: endpoint {
 578                                 remote-endpoint = <&csi1_ep>;
 579                         };
 580                 };
 581         };
 582 };
 583
 584 &i2c2 {
 585         clock-frequency = <100000>;
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&pinctrl_i2c2>;
 588         status = "okay";
 589
 590         egalax_ts@04 {
 591                 compatible = "eeti,egalax_ts";
 592                 reg = <0x04>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&pinctrl_egalax_int>;
 595                 interrupt-parent = <&gpio4>;
 596                 interrupts = <19 2>;
 597                 wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
 598         };
 599 };
 600
 601 &i2c3 {
 602         clock-frequency = <100000>;
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&pinctrl_i2c3>;
 605         status = "okay";
 606
 607         mma8451@1c {
 608                 compatible = "fsl,mma8451";
 609                 reg = <0x1c>;
 610                 position = <1>;
 611                 interrupt-parent = <&gpio6>;
 612                 interrupts = <2 8>;
 613                 interrupt-route = <2>;
 614         };
 615
 616         mag3110@0e {
 617                 compatible = "fsl,mag3110";
 618                 reg = <0x0e>;
 619                 position = <2>;
 620                 interrupt-parent = <&gpio6>;
 621                 interrupts = <5 1>;
 622                 shared-interrupt;
 623         };
 624
 625         isl29023@44 {
 626                 compatible = "fsl,isl29023";
 627                 reg = <0x44>;
 628                 rext = <499>;
 629                 interrupt-parent = <&gpio6>;
 630                 interrupts = <5 1>;
 631                 shared-interrupt;
 632         };
 633 };
 634
 635 &i2c4 {
 636         clock-frequency = <100000>;
 637         pinctrl-names = "default";
 638         pinctrl-0 = <&pinctrl_i2c4>;
 639         status = "okay";
 640
 641         codec: wm8962@1a {
 642                 compatible = "wlf,wm8962";
 643                 reg = <0x1a>;
 644                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 645                 DCVDD-supply = <&vgen4_reg>;
 646                 DBVDD-supply = <&vgen4_reg>;
 647                 AVDD-supply = <&vgen4_reg>;
 648                 CPVDD-supply = <&vgen4_reg>;
 649                 MICVDD-supply = <&vgen3_reg>;
 650                 PLLVDD-supply = <&vgen4_reg>;
 651                 SPKVDD1-supply = <&reg_psu_5v>;
 652                 SPKVDD2-supply = <&reg_psu_5v>;
 653                 amic-mono;
 654         };
 655 };
 656
 657 &vadc {
 658         vadc_in = <0>;
 659         csi_id = <1>;
 660         status = "okay";
 661         port {
 662                 vadc_ep: endpoint {
 663                         remote-endpoint = <&csi2_ep>;
 664                 };
 665         };
 666 };
 667
 668 &iomuxc {
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_hog>;
 671
 672         imx6x-sdb {
 673                 pinctrl_hog: hoggrp {
 674                         fsl,pins = <
 675                                 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
 676                                 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
 677                                 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 678                         >;
 679                 };
 680
 681                 pinctrl_audmux: audmuxgrp {
 682                         fsl,pins = <
 683                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 684                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 685                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 686                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 687                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 688                         >;
 689                 };
 690
 691                 pinctrl_canfd1: canfd1grp-1 {
 692                         fsl,pins = <
 693                                 MX6SX_PAD_QSPI1B_DQS__CANFD_TX1         0x1b0b0
 694                                 MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1       0x1b0b0
 695                         >;
 696                 };
 697
 698                 pinctrl_canfd2: canfd2grp-1 {
 699                         fsl,pins = <
 700                                 MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2       0x1b0b0
 701                                 MX6SX_PAD_QSPI1A_DQS__CANFD_TX2         0x1b0b0
 702                         >;
 703                 };
 704
 705                 pinctrl_csi_0: csigrp-0 {
 706                         fsl,pins = <
 707                                 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK        0x110b0
 708                                 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK      0x110b0
 709                                 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC       0x110b0
 710                                 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC       0x110b0
 711                                 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0      0x110b0
 712                                 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1      0x110b0
 713                                 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2      0x110b0
 714                                 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3      0x110b0
 715                                 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4      0x110b0
 716                                 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5      0x110b0
 717                                 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6      0x110b0
 718                                 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7      0x110b0
 719                                 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8      0x110b0
 720                                 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9      0x110b0
 721                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27       0x80000000
 722                                 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28       0x80000000
 723                         >;
 724                 };
 725
 726                 pinctrl_egalax_int: egalax_intgrp {
 727                         fsl,pins = <
 728                                 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
 729                         >;
 730                 };
 731
 732                 pinctrl_enet1: enet1grp {
 733                         fsl,pins = <
 734                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 735                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 736                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
 737                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 738                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 739                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 740                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 741                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 742                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 743                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 744                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 745                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 746                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 747                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 748                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 749                                 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19     0x80000000
 750                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 751                         >;
 752                 };
 753
 754                 pinctrl_enet2: enet2grp {
 755                         fsl,pins = <
 756                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 757                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 758                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 759                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 760                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 761                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 762                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 763                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 764                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 765                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 766                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 767                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 768                         >;
 769                 };
 770
 771                 pinctrl_flexcan1: flexcan1grp {
 772                         fsl,pins = <
 773                                 MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b0b0
 774                                 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b0b0
 775                         >;
 776                 };
 777
 778                 pinctrl_flexcan2: flexcan2grp {
 779                         fsl,pins = <
 780                                 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b0b0
 781                                 MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b0b0
 782                         >;
 783                 };
 784
 785                 pinctrl_gpio_keys: gpio_keysgrp {
 786                         fsl,pins = <
 787                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 788                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 789                         >;
 790                 };
 791
 792                 pinctrl_i2c1: i2c1grp {
 793                         fsl,pins = <
 794                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
 795                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
 796                         >;
 797                 };
 798
 799                 pinctrl_i2c2: i2c2grp {
 800                         fsl,pins = <
 801                                 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
 802                                 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
 803                         >;
 804                 };
 805
 806                 pinctrl_i2c3: i2c3grp {
 807                         fsl,pins = <
 808                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
 809                                 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
 810                         >;
 811                 };
 812
 813                 pinctrl_i2c4: i2c4grp {
 814                         fsl,pins = <
 815                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
 816                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
 817                         >;
 818                 };
 819
 820                 pinctrl_lcdif_dat: lcdifdatgrp {
 821                         fsl,pins = <
 822                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 823                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 824                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 825                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 826                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 827                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 828                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 829                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 830                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 831                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 832                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 833                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 834                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 835                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 836                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 837                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 838                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 839                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 840                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 841                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 842                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 843                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 844                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 845                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 846                         >;
 847                 };
 848
 849                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 850                         fsl,pins = <
 851                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 852                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 853                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 854                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 855                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 856                         >;
 857                 };
 858
 859                 pinctrl_pwm3: pwm3grp {
 860                         fsl,pins = <
 861                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 862                         >;
 863                 };
 864
 865                 pinctrl_pwm4: pwm4grp {
 866                         fsl,pins = <
 867                                 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
 868                         >;
 869                 };
 870
 871                 pinctrl_qspi2_1: qspi2grp_1 {
 872                         fsl,pins = <
 873                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 874                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 875                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 876                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 877                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 878                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 879                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 880                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 881                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 882                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 883                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 884                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 885                         >;
 886                 };
 887
 888                 pinctrl_sai1: sai1grp {
 889                         fsl,pins = <
 890                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130b0
 891                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130b0
 892                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120b0
 893                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130b0
 894                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130b0
 895                         >;
 896                 };
 897
 898                 pinctrl_spdif: spdifgrp {
 899                         fsl,pins = <
 900                                 MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
 901                         >;
 902                 };
 903
 904                 pinctrl_pcie: pciegrp {
 905                         fsl,pins = <
 906                                 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
 907                         >;
 908                 };
 909
 910                 pinctrl_pcie_reg: pciereggrp {
 911                         fsl,pins = <
 912                                 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
 913                         >;
 914                 };
 915
 916                 pinctrl_vcc_sd3: vccsd3grp {
 917                         fsl,pins = <
 918                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 919                         >;
 920                 };
 921
 922                 pinctrl_uart1: uart1grp {
 923                         fsl,pins = <
 924                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 925                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 926                         >;
 927                 };
 928
 929                 pinctrl_uart5: uart5grp {
 930                         fsl,pins = <
 931                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 932                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 933                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 934                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 935                         >;
 936                 };
 937
 938                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 939                         fsl,pins = <
 940                                 MX6SX_PAD_KEY_ROW3__UART5_TX            0x1b0b1
 941                                 MX6SX_PAD_KEY_COL3__UART5_RX            0x1b0b1
 942                                 MX6SX_PAD_KEY_ROW2__UART5_RTS_B         0x1b0b1
 943                                 MX6SX_PAD_KEY_COL2__UART5_CTS_B         0x1b0b1
 944                         >;
 945                 };
 946
 947                 pinctrl_usb_otg1: usbotg1grp {
 948                         fsl,pins = <
 949                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 950                         >;
 951                 };
 952
 953                 pinctrl_usb_otg1_id: usbotg1idgrp {
 954                         fsl,pins = <
 955                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 956                         >;
 957                 };
 958
 959                 pinctrl_usb_otg2: usbot2ggrp {
 960                         fsl,pins = <
 961                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
 962                         >;
 963                 };
 964
 965                 pinctrl_usdhc2: usdhc2grp {
 966                         fsl,pins = <
 967                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 968                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 969                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 970                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 971                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 972                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 973                         >;
 974                 };
 975
 976                 pinctrl_usdhc3: usdhc3grp {
 977                         fsl,pins = <
 978                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 979                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 980                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 981                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 982                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 983                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 984                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 985                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 986                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 987                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 988                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 989                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 990                         >;
 991                 };
 992
 993                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 994                         fsl,pins = <
 995                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 996                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 997                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 998                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 999                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
1000                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
1001                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
1002                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
1003                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
1004                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
1005                         >;
1006                 };
1007
1008                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
1009                         fsl,pins = <
1010                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
1011                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
1012                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
1013                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
1014                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
1015                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
1016                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
1017                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
1018                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
1019                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
1020                         >;
1021                 };
1022
1023                 pinctrl_usdhc4: usdhc4grp {
1024                         fsl,pins = <
1025                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1026                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1027                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1028                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1029                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1030                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1031                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
1032                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
1033                         >;
1034                 };
1035
1036                 pinctrl_usdhc4_1: usdhc4grp-1 {
1037                         fsl,pins = <
1038                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1039                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1040                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1041                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1042                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1043                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1044                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17059
1045                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17059
1046                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17059
1047                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17059
1048                         >;
1049                 };
1050
1051                 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
1052                         fsl,pins = <
1053                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
1054                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
1055                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
1056                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
1057                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
1058                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
1059                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
1060                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
1061                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
1062                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
1063                         >;
1064                 };
1065
1066                 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
1067                         fsl,pins = <
1068                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
1069                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
1070                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
1071                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
1072                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
1073                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
1074                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
1075                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
1076                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
1077                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
1078                         >;
1079                 };
1080         };
1081 };