arch/arm/boot/dts/imx6sx-sdb.dts

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sx.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloX SDB Board";
  16         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x80000000 0x40000000>;
  24         };
  25
  26         backlight1 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm3 0 5000000>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 fb-names = "mxs-lcdif0";
  32         };
  33
  34         backlight2 {
  35                 compatible = "pwm-backlight";
  36                 pwms = <&pwm4 0 5000000>;
  37                 brightness-levels = <0 4 8 16 32 64 128 255>;
  38                 default-brightness-level = <6>;
  39                 fb-names = "mxs-lcdif1";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_gpio_keys>;
  46
  47                 volume-up {
  48                         label = "Volume Up";
  49                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  50                         linux,code = <KEY_VOLUMEUP>;
  51                 };
  52
  53                 volume-down {
  54                         label = "Volume Down";
  55                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_VOLUMEDOWN>;
  57                 };
  58         };
  59
  60         hannstar_cabc {
  61                 compatible = "hannstar,cabc";
  62
  63                 lvds0 {
  64                         gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  65                 };
  66         };
  67
  68         pxp_v4l2_out {
  69                 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  70                 status = "okay";
  71         };
  72
  73         regulators {
  74                 compatible = "simple-bus";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 reg_lcd_3v3: lcd-3v3 {
  79                         compatible = "regulator-fixed";
  80                         regulator-name = "lcd-3v3";
  81                         gpio = <&gpio3 27 0>;
  82                         enable-active-high;
  83                         status = "disabled";
  84                 };
  85
  86                 vcc_sd3: regulator@0 {
  87                         compatible = "regulator-fixed";
  88                         reg = <0>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_vcc_sd3>;
  91                         regulator-name = "VCC_SD3";
  92                         regulator-min-microvolt = <3000000>;
  93                         regulator-max-microvolt = <3000000>;
  94                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  95                         enable-active-high;
  96                 };
  97         };
  98 };
  99
 100 &lcdif1 {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_lcdif_dat
 103                      &pinctrl_lcdif_ctrl>;
 104         lcd-supply = <&reg_lcd_3v3>;
 105         display = <&display0>;
 106         status = "disabled";
 107
 108         display0: display {
 109                 bits-per-pixel = <16>;
 110                 bus-width = <24>;
 111
 112                 display-timings {
 113                         native-mode = <&timing0>;
 114                         timing0: timing0 {
 115                                 clock-frequency = <33500000>;
 116                                 hactive = <800>;
 117                                 vactive = <480>;
 118                                 hback-porch = <89>;
 119                                 hfront-porch = <164>;
 120                                 vback-porch = <23>;
 121                                 vfront-porch = <10>;
 122                                 hsync-len = <10>;
 123                                 vsync-len = <10>;
 124                                 hsync-active = <0>;
 125                                 vsync-active = <0>;
 126                                 de-active = <1>;
 127                                 pixelclk-active = <0>;
 128                         };
 129                 };
 130         };
 131 };
 132
 133 &lcdif2 {
 134         display = <&display1>;
 135         disp-dev = "ldb";
 136         status = "okay";
 137
 138         display1: display {
 139                 bits-per-pixel = <16>;
 140                 bus-width = <18>;
 141         };
 142 };
 143
 144 &ldb {
 145         status = "okay";
 146
 147         lvds-channel@0 {
 148                 fsl,data-mapping = "spwg";
 149                 fsl,data-width = <18>;
 150                 crtc = "lcdif2";
 151                 status = "okay";
 152
 153                 display-timings {
 154                         native-mode = <&timing1>;
 155                         timing1: hsd100pxn1 {
 156                                 clock-frequency = <65000000>;
 157                                 hactive = <1024>;
 158                                 vactive = <768>;
 159                                 hback-porch = <220>;
 160                                 hfront-porch = <40>;
 161                                 vback-porch = <21>;
 162                                 vfront-porch = <7>;
 163                                 hsync-len = <60>;
 164                                 vsync-len = <10>;
 165                         };
 166                 };
 167         };
 168 };
 169
 170 &pwm3 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_pwm3>;
 173         status = "okay";
 174 };
 175
 176 &pwm4 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_pwm4>;
 179         status = "okay";
 180 };
 181
 182 &dcic1 {
 183         dcic_id = <0>;
 184         dcic_mux = "dcic-lcdif1";
 185         status = "okay";
 186 };
 187
 188 &dcic2 {
 189         dcic_id = <1>;
 190         dcic_mux = "dcic-lvds";
 191         status = "okay";
 192 };
 193
 194 &fec1 {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_enet1>;
 197         phy-mode = "rgmii";
 198         status = "okay";
 199 };
 200
 201 &qspi2 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_qspi2_1>;
 204         status = "okay";
 205
 206         flash0: s25fl128s@0 {
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 compatible = "spansion,s25fl128s";
 210                 spi-max-frequency = <66000000>;
 211                 spi-nor,ddr-quad-read-dummy = <6>;
 212                 reg = <0>;
 213         };
 214
 215         flash1: s25fl128s@1 {
 216                 #address-cells = <1>;
 217                 #size-cells = <1>;
 218                 compatible = "spansion,s25fl128s";
 219                 spi-max-frequency = <66000000>;
 220                 spi-nor,ddr-quad-read-dummy = <6>;
 221                 reg = <1>;
 222         };
 223 };
 224
 225 &pxp {
 226         status = "okay";
 227 };
 228
 229 &uart1 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_uart1>;
 232         status = "okay";
 233 };
 234
 235 &uart5 { /* for bluetooth */
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_uart5>;
 238         fsl,uart-has-rtscts;
 239         status = "okay";
 240 };
 241
 242 &usdhc2 {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_usdhc2>;
 245         non-removable;
 246         no-1-8-v;
 247         keep-power-in-suspend;
 248         enable-sdio-wakeup;
 249         status = "okay";
 250 };
 251
 252 &usdhc3 {
 253         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 254         pinctrl-0 = <&pinctrl_usdhc3>;
 255         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 256         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 257         bus-width = <8>;
 258         cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 259         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 260         keep-power-in-suspend;
 261         enable-sdio-wakeup;
 262         vmmc-supply = <&vcc_sd3>;
 263         status = "okay";
 264 };
 265
 266 &usdhc4 {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_usdhc4>;
 269         cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
 270         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 271         status = "okay";
 272 };
 273
 274 &iomuxc {
 275         imx6x-sdb {
 276                 pinctrl_enet1: enet1grp {
 277                         fsl,pins = <
 278                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 279                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 280                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
 281                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 282                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 283                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 284                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 285                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 286                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 287                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 288                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 289                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 290                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 291                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 292                         >;
 293                 };
 294
 295                 pinctrl_gpio_keys: gpio_keysgrp {
 296                         fsl,pins = <
 297                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 298                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 299                         >;
 300                 };
 301
 302                 pinctrl_lcdif_dat: lcdifdatgrp {
 303                         fsl,pins = <
 304                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 305                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 306                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 307                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 308                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 309                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 310                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 311                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 312                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 313                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 314                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 315                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 316                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 317                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 318                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 319                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 320                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 321                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 322                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 323                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 324                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 325                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 326                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 327                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 328                         >;
 329                 };
 330
 331                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 332                         fsl,pins = <
 333                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 334                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 335                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 336                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 337                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 338                         >;
 339                 };
 340
 341                 pinctrl_pwm3: pwm3grp {
 342                         fsl,pins = <
 343                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 344                         >;
 345                 };
 346
 347                 pinctrl_pwm4: pwm4grp {
 348                         fsl,pins = <
 349                                 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
 350                         >;
 351                 };
 352
 353                 pinctrl_qspi2_1: qspi2grp_1 {
 354                         fsl,pins = <
 355                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 356                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 357                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 358                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 359                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 360                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 361                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 362                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 363                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 364                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 365                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 366                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 367                         >;
 368                 };
 369
 370                 pinctrl_vcc_sd3: vccsd3grp {
 371                         fsl,pins = <
 372                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 373                         >;
 374                 };
 375
 376                 pinctrl_uart1: uart1grp {
 377                         fsl,pins = <
 378                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 379                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 380                         >;
 381                 };
 382
 383                 pinctrl_uart5: uart5grp {
 384                         fsl,pins = <
 385                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 386                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 387                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 388                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 389                         >;
 390                 };
 391
 392                 pinctrl_usdhc2: usdhc2grp {
 393                         fsl,pins = <
 394                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 395                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 396                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 397                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 398                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 399                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 400                         >;
 401                 };
 402
 403                 pinctrl_usdhc3: usdhc3grp {
 404                         fsl,pins = <
 405                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 406                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 407                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 408                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 409                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 410                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 411                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 412                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 413                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 414                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 415                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 416                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 417                         >;
 418                 };
 419
 420                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 421                         fsl,pins = <
 422                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 423                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 424                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 425                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 426                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
 427                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
 428                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
 429                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
 430                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
 431                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
 432                         >;
 433                 };
 434
 435                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
 436                         fsl,pins = <
 437                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
 438                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
 439                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
 440                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
 441                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
 442                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
 443                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
 444                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
 445                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
 446                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
 447                         >;
 448                 };
 449
 450                 pinctrl_usdhc4: usdhc4grp {
 451                         fsl,pins = <
 452                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 453                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 454                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 455                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 456                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 457                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 458                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
 459                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
 460                         >;
 461                 };
 462         };
 463 };