arch/arm/boot/dts/imx6sx-sdb.dts

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/input/input.h>
  12 #include "imx6sx.dtsi"
  13
  14 / {
  15         model = "Freescale i.MX6 SoloX SDB Board";
  16         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         memory {
  23                 reg = <0x80000000 0x40000000>;
  24         };
  25
  26         backlight1 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm3 0 5000000>;
  29                 brightness-levels = <0 4 8 16 32 64 128 255>;
  30                 default-brightness-level = <6>;
  31                 fb-names = "mxs-lcdif0";
  32         };
  33
  34         backlight2 {
  35                 compatible = "pwm-backlight";
  36                 pwms = <&pwm4 0 5000000>;
  37                 brightness-levels = <0 4 8 16 32 64 128 255>;
  38                 default-brightness-level = <6>;
  39                 fb-names = "mxs-lcdif1";
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_gpio_keys>;
  46
  47                 volume-up {
  48                         label = "Volume Up";
  49                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  50                         linux,code = <KEY_VOLUMEUP>;
  51                 };
  52
  53                 volume-down {
  54                         label = "Volume Down";
  55                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_VOLUMEDOWN>;
  57                 };
  58         };
  59
  60         hannstar_cabc {
  61                 compatible = "hannstar,cabc";
  62
  63                 lvds0 {
  64                         gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  65                 };
  66         };
  67
  68         pxp_v4l2_out {
  69                 compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
  70                 status = "okay";
  71         };
  72
  73         regulators {
  74                 compatible = "simple-bus";
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 reg_lcd_3v3: lcd-3v3 {
  79                         compatible = "regulator-fixed";
  80                         regulator-name = "lcd-3v3";
  81                         gpio = <&gpio3 27 0>;
  82                         enable-active-high;
  83                         status = "disabled";
  84                 };
  85
  86                 vcc_sd3: regulator@0 {
  87                         compatible = "regulator-fixed";
  88                         reg = <0>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_vcc_sd3>;
  91                         regulator-name = "VCC_SD3";
  92                         regulator-min-microvolt = <3000000>;
  93                         regulator-max-microvolt = <3000000>;
  94                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  95                         enable-active-high;
  96                 };
  97
  98                 reg_psu_5v: regulator@1 {
  99                         compatible = "regulator-fixed";
 100                         reg = <1>;
 101                         regulator-name = "PSU-5V0";
 102                         regulator-min-microvolt = <5000000>;
 103                         regulator-max-microvolt = <5000000>;
 104                         regulator-boot-on;
 105                 };
 106
 107                 reg_vref_3v3: regulator@2 {
 108                         compatible = "regulator-fixed";
 109                         regulator-name = "vref-3v3";
 110                         regulator-min-microvolt = <3300000>;
 111                         regulator-max-microvolt = <3300000>;
 112                 };
 113
 114                 reg_usb_otg1_vbus: regulator@3 {
 115                         compatible = "regulator-fixed";
 116                         reg = <3>;
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&pinctrl_usb_otg1>;
 119                         regulator-name = "usb_otg1_vbus";
 120                         regulator-min-microvolt = <5000000>;
 121                         regulator-max-microvolt = <5000000>;
 122                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                 };
 125
 126                 reg_usb_otg2_vbus: regulator@4 {
 127                         compatible = "regulator-fixed";
 128                         reg = <4>;
 129                         pinctrl-names = "default";
 130                         pinctrl-0 = <&pinctrl_usb_otg2>;
 131                         regulator-name = "usb_otg2_vbus";
 132                         regulator-min-microvolt = <5000000>;
 133                         regulator-max-microvolt = <5000000>;
 134                         gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 135                         enable-active-high;
 136                 };
 137
 138                 reg_pcie: regulator@5 {
 139                         compatible = "regulator-fixed";
 140                         reg = <5>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_pcie_reg>;
 143                         regulator-name = "MPCIE_3V3";
 144                         regulator-min-microvolt = <3300000>;
 145                         regulator-max-microvolt = <3300000>;
 146                         gpio = <&gpio2 1 0>;
 147                         regulator-always-on;
 148                         enable-active-high;
 149                 };
 150         };
 151
 152         sound {
 153                 compatible = "fsl,imx6q-sabresd-wm8962",
 154                            "fsl,imx-audio-wm8962";
 155                 model = "wm8962-audio";
 156                 cpu-dai = <&ssi2>;
 157                 audio-codec = <&codec>;
 158                 audio-routing =
 159                         "Headphone Jack", "HPOUTL",
 160                         "Headphone Jack", "HPOUTR",
 161                         "Ext Spk", "SPKOUTL",
 162                         "Ext Spk", "SPKOUTR",
 163                         "AMIC", "MICBIAS",
 164                         "IN3R", "AMIC";
 165                 mux-int-port = <2>;
 166                 mux-ext-port = <6>;
 167                 hp-det-gpios = <&gpio1 17 1>;
 168         };
 169
 170         sound-spdif {
 171                 compatible = "fsl,imx-audio-spdif",
 172                            "fsl,imx6sx-sdb-spdif";
 173                 model = "imx-spdif";
 174                 spdif-controller = <&spdif>;
 175                 spdif-out;
 176         };
 177 };
 178
 179 &adc1 {
 180         vref-supply = <&reg_vref_3v3>;
 181         status = "okay";
 182 };
 183
 184 &adc2 {
 185         vref-supply = <&reg_vref_3v3>;
 186         status = "okay";
 187 };
 188
 189 &audmux {
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_audmux>;
 192         status = "okay";
 193 };
 194
 195 &csi1 {
 196         status = "okay";
 197
 198         port {
 199                 csi1_ep: endpoint {
 200                         remote-endpoint = <&ov5640_ep>;
 201                 };
 202         };
 203 };
 204
 205 &csi2 {
 206         status = "okay";
 207         port {
 208                 csi2_ep: endpoint {
 209                         remote-endpoint = <&vadc_ep>;
 210                 };
 211         };
 212 };
 213
 214 &cpu0 {
 215         operating-points = <
 216                 /* kHz    uV */
 217                 996000  1250000
 218                 792000  1175000
 219                 396000  1175000
 220                 >;
 221         fsl,soc-operating-points = <
 222                 /* ARM kHz      SOC uV */
 223                 996000  1250000
 224                 792000  1175000
 225                 396000  1175000
 226         >;
 227         arm-supply = <&sw1a_reg>;
 228         soc-supply = <&sw1a_reg>;
 229         fsl,arm-soc-shared = <1>;
 230 };
 231
 232 &gpc {
 233         /* use ldo-bypass, u-boot will check it and configure */
 234         fsl,ldo-bypass = <1>;
 235 };
 236
 237 &lcdif1 {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_lcdif_dat
 240                      &pinctrl_lcdif_ctrl>;
 241         lcd-supply = <&reg_lcd_3v3>;
 242         display = <&display0>;
 243         status = "disabled";
 244
 245         display0: display {
 246                 bits-per-pixel = <16>;
 247                 bus-width = <24>;
 248
 249                 display-timings {
 250                         native-mode = <&timing0>;
 251                         timing0: timing0 {
 252                                 clock-frequency = <33500000>;
 253                                 hactive = <800>;
 254                                 vactive = <480>;
 255                                 hback-porch = <89>;
 256                                 hfront-porch = <164>;
 257                                 vback-porch = <23>;
 258                                 vfront-porch = <10>;
 259                                 hsync-len = <10>;
 260                                 vsync-len = <10>;
 261                                 hsync-active = <0>;
 262                                 vsync-active = <0>;
 263                                 de-active = <1>;
 264                                 pixelclk-active = <0>;
 265                         };
 266                 };
 267         };
 268 };
 269
 270 &lcdif2 {
 271         display = <&display1>;
 272         disp-dev = "ldb";
 273         status = "okay";
 274
 275         display1: display {
 276                 bits-per-pixel = <16>;
 277                 bus-width = <18>;
 278         };
 279 };
 280
 281 &ldb {
 282         status = "okay";
 283
 284         lvds-channel@0 {
 285                 fsl,data-mapping = "spwg";
 286                 fsl,data-width = <18>;
 287                 crtc = "lcdif2";
 288                 status = "okay";
 289
 290                 display-timings {
 291                         native-mode = <&timing1>;
 292                         timing1: hsd100pxn1 {
 293                                 clock-frequency = <65000000>;
 294                                 hactive = <1024>;
 295                                 vactive = <768>;
 296                                 hback-porch = <220>;
 297                                 hfront-porch = <40>;
 298                                 vback-porch = <21>;
 299                                 vfront-porch = <7>;
 300                                 hsync-len = <60>;
 301                                 vsync-len = <10>;
 302                         };
 303                 };
 304         };
 305 };
 306
 307 &pwm3 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_pwm3>;
 310         status = "okay";
 311 };
 312
 313 &pwm4 {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_pwm4>;
 316         status = "okay";
 317 };
 318
 319 &dcic1 {
 320         dcic_id = <0>;
 321         dcic_mux = "dcic-lcdif1";
 322         status = "okay";
 323 };
 324
 325 &dcic2 {
 326         dcic_id = <1>;
 327         dcic_mux = "dcic-lvds";
 328         status = "okay";
 329 };
 330
 331 &fec1 {
 332         pinctrl-names = "default";
 333         pinctrl-0 = <&pinctrl_enet1>;
 334         pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
 335         phy-mode = "rgmii";
 336         fsl,num_tx_queues=<3>;
 337         fsl,num_rx_queues=<3>;
 338         status = "okay";
 339 };
 340
 341 &fec2 {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_enet2>;
 344         phy-mode = "rgmii";
 345         fsl,num_tx_queues=<3>;
 346         fsl,num_rx_queues=<3>;
 347         status = "okay";
 348 };
 349
 350 &flexcan1 {
 351         pinctrl-names = "default";
 352         pinctrl-0 = <&pinctrl_flexcan1>;
 353         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 354         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 355         status = "okay";
 356 };
 357
 358 &flexcan2 {
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&pinctrl_flexcan2>;
 361         trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 362         trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 363         status = "okay";
 364 };
 365
 366 &pcie {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_pcie>;
 369         reset-gpio = <&gpio2 0 0>;
 370         status = "okay";
 371 };
 372
 373 &qspi2 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_qspi2_1>;
 376         status = "okay";
 377
 378         flash0: s25fl128s@0 {
 379                 #address-cells = <1>;
 380                 #size-cells = <1>;
 381                 compatible = "spansion,s25fl128s";
 382                 spi-max-frequency = <66000000>;
 383                 spi-nor,ddr-quad-read-dummy = <6>;
 384                 reg = <0>;
 385         };
 386
 387         flash1: s25fl128s@1 {
 388                 #address-cells = <1>;
 389                 #size-cells = <1>;
 390                 compatible = "spansion,s25fl128s";
 391                 spi-max-frequency = <66000000>;
 392                 spi-nor,ddr-quad-read-dummy = <6>;
 393                 reg = <1>;
 394         };
 395 };
 396
 397 &pxp {
 398         status = "okay";
 399 };
 400
 401 &sai1 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_sai1>;
 404         status = "disabled";
 405 };
 406
 407 &spdif {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_spdif>;
 410         status = "okay";
 411 };
 412
 413 &ssi2 {
 414         status = "okay";
 415 };
 416
 417 &uart1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_uart1>;
 420         status = "okay";
 421 };
 422
 423 &uart5 { /* for bluetooth */
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_uart5>;
 426         fsl,uart-has-rtscts;
 427         status = "okay";
 428         /* for DTE mode, add below change */
 429         /* fsl,dte-mode;*/
 430         /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 431 };
 432
 433 &usbotg1 {
 434         vbus-supply = <&reg_usb_otg1_vbus>;
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 437         status = "okay";
 438 };
 439
 440 &usbotg2 {
 441         vbus-supply = <&reg_usb_otg2_vbus>;
 442         dr_mode = "host";
 443         status = "okay";
 444 };
 445
 446 &usdhc2 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_usdhc2>;
 449         non-removable;
 450         no-1-8-v;
 451         keep-power-in-suspend;
 452         enable-sdio-wakeup;
 453         status = "okay";
 454 };
 455
 456 &usdhc3 {
 457         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 458         pinctrl-0 = <&pinctrl_usdhc3>;
 459         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 460         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 461         bus-width = <8>;
 462         cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 463         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 464         keep-power-in-suspend;
 465         enable-sdio-wakeup;
 466         vmmc-supply = <&vcc_sd3>;
 467         status = "okay";
 468 };
 469
 470 &usdhc4 {
 471         pinctrl-names = "default";
 472         pinctrl-0 = <&pinctrl_usdhc4>;
 473         cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
 474         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 475         status = "okay";
 476 };
 477
 478 &i2c1 {
 479         clock-frequency = <100000>;
 480         pinctrl-names = "default";
 481         pinctrl-0 = <&pinctrl_i2c1>;
 482         status = "okay";
 483
 484         pmic: pfuze100@08 {
 485                 compatible = "fsl,pfuze200";
 486                 reg = <0x08>;
 487
 488                 regulators {
 489                         sw1a_reg: sw1ab {
 490                                 regulator-min-microvolt = <300000>;
 491                                 regulator-max-microvolt = <1875000>;
 492                                 regulator-boot-on;
 493                                 regulator-always-on;
 494                                 regulator-ramp-delay = <6250>;
 495                         };
 496
 497                         sw2_reg: sw2 {
 498                                 regulator-min-microvolt = <800000>;
 499                                 regulator-max-microvolt = <3300000>;
 500                                 regulator-boot-on;
 501                                 regulator-always-on;
 502                         };
 503
 504                         sw3a_reg: sw3a {
 505                                 regulator-min-microvolt = <400000>;
 506                                 regulator-max-microvolt = <1975000>;
 507                                 regulator-boot-on;
 508                                 regulator-always-on;
 509                         };
 510
 511                         sw3b_reg: sw3b {
 512                                 regulator-min-microvolt = <400000>;
 513                                 regulator-max-microvolt = <1975000>;
 514                                 regulator-boot-on;
 515                                 regulator-always-on;
 516                         };
 517
 518                         swbst_reg: swbst {
 519                                 regulator-min-microvolt = <5000000>;
 520                                 regulator-max-microvolt = <5150000>;
 521                         };
 522
 523                         snvs_reg: vsnvs {
 524                                 regulator-min-microvolt = <1000000>;
 525                                 regulator-max-microvolt = <3000000>;
 526                                 regulator-boot-on;
 527                                 regulator-always-on;
 528                         };
 529
 530                         vref_reg: vrefddr {
 531                                 regulator-boot-on;
 532                                 regulator-always-on;
 533                         };
 534
 535                         vgen1_reg: vgen1 {
 536                                 regulator-min-microvolt = <800000>;
 537                                 regulator-max-microvolt = <1550000>;
 538                                 regulator-always-on;
 539                         };
 540
 541                         vgen2_reg: vgen2 {
 542                                 regulator-min-microvolt = <800000>;
 543                                 regulator-max-microvolt = <1550000>;
 544                         };
 545
 546                         vgen3_reg: vgen3 {
 547                                 regulator-min-microvolt = <1800000>;
 548                                 regulator-max-microvolt = <3300000>;
 549                                 regulator-always-on;
 550                         };
 551
 552                         vgen4_reg: vgen4 {
 553                                 regulator-min-microvolt = <1800000>;
 554                                 regulator-max-microvolt = <3300000>;
 555                                 regulator-always-on;
 556                         };
 557
 558                         vgen5_reg: vgen5 {
 559                                 regulator-min-microvolt = <1800000>;
 560                                 regulator-max-microvolt = <3300000>;
 561                                 regulator-always-on;
 562                         };
 563
 564                         vgen6_reg: vgen6 {
 565                                 regulator-min-microvolt = <1800000>;
 566                                 regulator-max-microvolt = <3300000>;
 567                                 regulator-always-on;
 568                         };
 569                 };
 570         };
 571
 572         ov5640: ov5640@3c {
 573                 compatible = "ovti,ov5640";
 574                 reg = <0x3c>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&pinctrl_csi_0>;
 577                 clocks = <&clks IMX6SX_CLK_CSI>;
 578                 clock-names = "csi_mclk";
 579                 AVDD-supply = <&vgen3_reg>;  /* 2.8v */
 580                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 581                 pwn-gpios = <&gpio3 28 1>;
 582                 rst-gpios = <&gpio3 27 0>;
 583                 csi_id = <0>;
 584                 mclk = <24000000>;
 585                 mclk_source = <0>;
 586                 port {
 587                         ov5640_ep: endpoint {
 588                                 remote-endpoint = <&csi1_ep>;
 589                         };
 590                 };
 591         };
 592 };
 593
 594 &i2c2 {
 595         clock-frequency = <100000>;
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&pinctrl_i2c2>;
 598         status = "okay";
 599
 600         egalax_ts@04 {
 601                 compatible = "eeti,egalax_ts";
 602                 reg = <0x04>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&pinctrl_egalax_int>;
 605                 interrupt-parent = <&gpio4>;
 606                 interrupts = <19 2>;
 607                 wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
 608         };
 609 };
 610
 611 &i2c3 {
 612         clock-frequency = <100000>;
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&pinctrl_i2c3>;
 615         status = "okay";
 616
 617         mma8451@1c {
 618                 compatible = "fsl,mma8451";
 619                 reg = <0x1c>;
 620                 position = <1>;
 621                 interrupt-parent = <&gpio6>;
 622                 interrupts = <2 8>;
 623                 interrupt-route = <2>;
 624         };
 625
 626         mag3110@0e {
 627                 compatible = "fsl,mag3110";
 628                 reg = <0x0e>;
 629                 position = <2>;
 630                 interrupt-parent = <&gpio6>;
 631                 interrupts = <5 1>;
 632                 shared-interrupt;
 633         };
 634
 635         isl29023@44 {
 636                 compatible = "fsl,isl29023";
 637                 reg = <0x44>;
 638                 rext = <499>;
 639                 interrupt-parent = <&gpio6>;
 640                 interrupts = <5 1>;
 641                 shared-interrupt;
 642         };
 643 };
 644
 645 &i2c4 {
 646         clock-frequency = <100000>;
 647         pinctrl-names = "default";
 648         pinctrl-0 = <&pinctrl_i2c4>;
 649         status = "okay";
 650
 651         codec: wm8962@1a {
 652                 compatible = "wlf,wm8962";
 653                 reg = <0x1a>;
 654                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 655                 DCVDD-supply = <&vgen4_reg>;
 656                 DBVDD-supply = <&vgen4_reg>;
 657                 AVDD-supply = <&vgen4_reg>;
 658                 CPVDD-supply = <&vgen4_reg>;
 659                 MICVDD-supply = <&vgen3_reg>;
 660                 PLLVDD-supply = <&vgen4_reg>;
 661                 SPKVDD1-supply = <&reg_psu_5v>;
 662                 SPKVDD2-supply = <&reg_psu_5v>;
 663                 amic-mono;
 664         };
 665 };
 666
 667 &vadc {
 668         vadc_in = <0>;
 669         csi_id = <1>;
 670         status = "okay";
 671         port {
 672                 vadc_ep: endpoint {
 673                         remote-endpoint = <&csi2_ep>;
 674                 };
 675         };
 676 };
 677
 678 &iomuxc {
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&pinctrl_hog>;
 681
 682         imx6x-sdb {
 683                 pinctrl_hog: hoggrp {
 684                         fsl,pins = <
 685                                 MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
 686                                 MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
 687                                 MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
 688                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
 689                         >;
 690                 };
 691
 692                 pinctrl_audmux: audmuxgrp {
 693                         fsl,pins = <
 694                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 695                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 696                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 697                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 698                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 699                         >;
 700                 };
 701
 702                 pinctrl_canfd1: canfd1grp-1 {
 703                         fsl,pins = <
 704                                 MX6SX_PAD_QSPI1B_DQS__CANFD_TX1         0x1b0b0
 705                                 MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1       0x1b0b0
 706                         >;
 707                 };
 708
 709                 pinctrl_canfd2: canfd2grp-1 {
 710                         fsl,pins = <
 711                                 MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2       0x1b0b0
 712                                 MX6SX_PAD_QSPI1A_DQS__CANFD_TX2         0x1b0b0
 713                         >;
 714                 };
 715
 716                 pinctrl_csi_0: csigrp-0 {
 717                         fsl,pins = <
 718                                 MX6SX_PAD_LCD1_DATA07__CSI1_MCLK        0x110b0
 719                                 MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK      0x110b0
 720                                 MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC       0x110b0
 721                                 MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC       0x110b0
 722                                 MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0      0x110b0
 723                                 MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1      0x110b0
 724                                 MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2      0x110b0
 725                                 MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3      0x110b0
 726                                 MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4      0x110b0
 727                                 MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5      0x110b0
 728                                 MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6      0x110b0
 729                                 MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7      0x110b0
 730                                 MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8      0x110b0
 731                                 MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9      0x110b0
 732                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27       0x80000000
 733                                 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28       0x80000000
 734                         >;
 735                 };
 736
 737                 pinctrl_egalax_int: egalax_intgrp {
 738                         fsl,pins = <
 739                                 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
 740                         >;
 741                 };
 742
 743                 pinctrl_enet1: enet1grp {
 744                         fsl,pins = <
 745                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 746                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 747                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
 748                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 749                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 750                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 751                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 752                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 753                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 754                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 755                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 756                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 757                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 758                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 759                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 760                                 MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
 761                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 762                         >;
 763                 };
 764
 765                 pinctrl_enet2: enet2grp {
 766                         fsl,pins = <
 767                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 768                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 769                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 770                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 771                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 772                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 773                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 774                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 775                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 776                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 777                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 778                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 779                         >;
 780                 };
 781
 782                 pinctrl_flexcan1: flexcan1grp {
 783                         fsl,pins = <
 784                                 MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b0b0
 785                                 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b0b0
 786                         >;
 787                 };
 788
 789                 pinctrl_flexcan2: flexcan2grp {
 790                         fsl,pins = <
 791                                 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b0b0
 792                                 MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b0b0
 793                         >;
 794                 };
 795
 796                 pinctrl_gpio_keys: gpio_keysgrp {
 797                         fsl,pins = <
 798                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 799                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 800                         >;
 801                 };
 802
 803                 pinctrl_i2c1: i2c1grp {
 804                         fsl,pins = <
 805                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
 806                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
 807                         >;
 808                 };
 809
 810                 pinctrl_i2c2: i2c2grp {
 811                         fsl,pins = <
 812                                 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
 813                                 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
 814                         >;
 815                 };
 816
 817                 pinctrl_i2c3: i2c3grp {
 818                         fsl,pins = <
 819                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
 820                                 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
 821                         >;
 822                 };
 823
 824                 pinctrl_i2c4: i2c4grp {
 825                         fsl,pins = <
 826                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
 827                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
 828                         >;
 829                 };
 830
 831                 pinctrl_lcdif_dat: lcdifdatgrp {
 832                         fsl,pins = <
 833                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 834                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 835                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 836                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 837                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 838                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 839                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 840                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 841                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 842                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 843                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 844                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 845                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 846                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 847                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 848                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 849                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 850                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 851                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 852                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 853                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 854                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 855                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 856                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 857                         >;
 858                 };
 859
 860                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
 861                         fsl,pins = <
 862                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 863                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 864                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 865                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 866                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 867                         >;
 868                 };
 869
 870                 pinctrl_pwm3: pwm3grp {
 871                         fsl,pins = <
 872                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 873                         >;
 874                 };
 875
 876                 pinctrl_pwm4: pwm4grp {
 877                         fsl,pins = <
 878                                 MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
 879                         >;
 880                 };
 881
 882                 pinctrl_qspi2_1: qspi2grp_1 {
 883                         fsl,pins = <
 884                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 885                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 886                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 887                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 888                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 889                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 890                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 891                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 892                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 893                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 894                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 895                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 896                         >;
 897                 };
 898
 899                 pinctrl_sai1: sai1grp {
 900                         fsl,pins = <
 901                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130b0
 902                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130b0
 903                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120b0
 904                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130b0
 905                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130b0
 906                         >;
 907                 };
 908
 909                 pinctrl_spdif: spdifgrp {
 910                         fsl,pins = <
 911                                 MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
 912                         >;
 913                 };
 914
 915                 pinctrl_pcie: pciegrp {
 916                         fsl,pins = <
 917                                 MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
 918                         >;
 919                 };
 920
 921                 pinctrl_pcie_reg: pciereggrp {
 922                         fsl,pins = <
 923                                 MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
 924                         >;
 925                 };
 926
 927                 pinctrl_vcc_sd3: vccsd3grp {
 928                         fsl,pins = <
 929                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 930                         >;
 931                 };
 932
 933                 pinctrl_uart1: uart1grp {
 934                         fsl,pins = <
 935                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 936                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 937                         >;
 938                 };
 939
 940                 pinctrl_uart5: uart5grp {
 941                         fsl,pins = <
 942                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 943                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 944                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 945                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 946                         >;
 947                 };
 948
 949                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 950                         fsl,pins = <
 951                                 MX6SX_PAD_KEY_ROW3__UART5_TX            0x1b0b1
 952                                 MX6SX_PAD_KEY_COL3__UART5_RX            0x1b0b1
 953                                 MX6SX_PAD_KEY_ROW2__UART5_RTS_B         0x1b0b1
 954                                 MX6SX_PAD_KEY_COL2__UART5_CTS_B         0x1b0b1
 955                         >;
 956                 };
 957
 958                 pinctrl_usb_otg1: usbotg1grp {
 959                         fsl,pins = <
 960                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 961                         >;
 962                 };
 963
 964                 pinctrl_usb_otg1_id: usbotg1idgrp {
 965                         fsl,pins = <
 966                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 967                         >;
 968                 };
 969
 970                 pinctrl_usb_otg2: usbot2ggrp {
 971                         fsl,pins = <
 972                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
 973                         >;
 974                 };
 975
 976                 pinctrl_usdhc2: usdhc2grp {
 977                         fsl,pins = <
 978                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 979                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 980                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 981                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 982                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 983                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 984                         >;
 985                 };
 986
 987                 pinctrl_usdhc3: usdhc3grp {
 988                         fsl,pins = <
 989                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 990                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 991                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 992                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 993                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 994                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 995                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 996                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 997                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 998                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 999                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
1000                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
1001                         >;
1002                 };
1003
1004                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
1005                         fsl,pins = <
1006                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
1007                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
1008                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
1009                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
1010                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
1011                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
1012                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
1013                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
1014                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
1015                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
1016                         >;
1017                 };
1018
1019                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
1020                         fsl,pins = <
1021                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
1022                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
1023                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
1024                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
1025                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
1026                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
1027                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
1028                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
1029                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
1030                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
1031                         >;
1032                 };
1033
1034                 pinctrl_usdhc4: usdhc4grp {
1035                         fsl,pins = <
1036                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1037                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1038                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1039                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1040                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1041                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1042                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
1043                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
1044                         >;
1045                 };
1046
1047                 pinctrl_usdhc4_1: usdhc4grp-1 {
1048                         fsl,pins = <
1049                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
1050                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
1051                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
1052                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
1053                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
1054                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
1055                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17059
1056                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17059
1057                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17059
1058                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17059
1059                         >;
1060                 };
1061
1062                 pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
1063                         fsl,pins = <
1064                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
1065                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
1066                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
1067                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
1068                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
1069                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
1070                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
1071                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
1072                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
1073                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
1074                         >;
1075                 };
1076
1077                 pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
1078                         fsl,pins = <
1079                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
1080                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
1081                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
1082                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
1083                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
1084                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
1085                                 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
1086                                 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
1087                                 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
1088                                 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
1089                         >;
1090                 };
1091         };
1092 };