arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                         >;
  66                         fsl,soc-operating-points = <
  67                                 /* ARM kHz  SOC uV */
  68                                 996000      1175000
  69                                 792000      1175000
  70                                 396000      1175000
  71                         >;
  72                         clock-latency = <61036>; /* two CLK32 periods */
  73                         clocks = <&clks IMX6SX_CLK_ARM>,
  74                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6SX_CLK_STEP>,
  76                                  <&clks IMX6SX_CLK_PLL1_SW>,
  77                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  78                         clock-names = "arm", "pll2_pfd2_396m", "step",
  79                                       "pll1_sw", "pll1_sys";
  80                         arm-supply = <&reg_arm>;
  81                         soc-supply = <&reg_soc>;
  82                 };
  83         };
  84
  85         intc: interrupt-controller@00a01000 {
  86                 compatible = "arm,cortex-a9-gic";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x00a01000 0x1000>,
  90                       <0x00a00100 0x100>;
  91         };
  92
  93         clocks {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ckil: clock@0 {
  98                         compatible = "fixed-clock";
  99                         reg = <0>;
 100                         #clock-cells = <0>;
 101                         clock-frequency = <32768>;
 102                         clock-output-names = "ckil";
 103                 };
 104
 105                 osc: clock@1 {
 106                         compatible = "fixed-clock";
 107                         reg = <1>;
 108                         #clock-cells = <0>;
 109                         clock-frequency = <24000000>;
 110                         clock-output-names = "osc";
 111                 };
 112
 113                 ipp_di0: clock@2 {
 114                         compatible = "fixed-clock";
 115                         reg = <2>;
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                         clock-output-names = "ipp_di0";
 119                 };
 120
 121                 ipp_di1: clock@3 {
 122                         compatible = "fixed-clock";
 123                         reg = <3>;
 124                         #clock-cells = <0>;
 125                         clock-frequency = <0>;
 126                         clock-output-names = "ipp_di1";
 127                 };
 128         };
 129
 130         soc {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "simple-bus";
 134                 interrupt-parent = <&intc>;
 135                 ranges;
 136
 137                 busfreq {
 138                         compatible = "fsl,imx6_busfreq";
 139                         clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
 140                                 <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
 141                                 <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
 142                                 <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
 143                                 <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
 144                                 <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
 145                                 <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
 146                                 <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
 147                                 <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
 148                                 <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>,
 149                                 <&clks IMX6SX_CLK_M4>;
 150                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
 151                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
 152                                 "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", "m4";
 153                         fsl,max_ddr_freq = <400000000>;
 154                 };
 155
 156                 pmu {
 157                         compatible = "arm,cortex-a9-pmu";
 158                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 ocrams: sram@008f8000 {
 162                         compatible = "fsl,lpm-sram";
 163                         reg = <0x008f8000 0x4000>;
 164                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 165                 };
 166
 167                 ocrams_ddr: sram@00900000 {
 168                         compatible = "fsl,ddr-lpm-sram";
 169                         reg = <0x00900000 0x1000>;
 170                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 171                 };
 172
 173                 ocram: sram@00901000 {
 174                         compatible = "mmio-sram";
 175                         reg = <0x00901000 0x1F000>;
 176                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 177                 };
 178
 179                 ocram_mf: sram-mf@00900000 {
 180                         compatible = "fsl,mega-fast-sram";
 181                         reg = <0x00900000 0x20000>;
 182                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 183                 };
 184
 185                 L2: l2-cache@00a02000 {
 186                         compatible = "arm,pl310-cache";
 187                         reg = <0x00a02000 0x1000>;
 188                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 189                         cache-unified;
 190                         cache-level = <2>;
 191                         arm,tag-latency = <4 2 3>;
 192                         arm,data-latency = <4 2 3>;
 193                 };
 194
 195                 gpu: gpu@01800000 {
 196                         compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
 197                         reg = <0x01800000 0x4000>, <0x80000000 0x0>;
 198                         reg-names = "iobase_3d", "phys_baseaddr";
 199                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 200                         interrupt-names = "irq_3d";
 201                         clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
 202                                 <&clks 0>;
 203                         clock-names = "gpu3d_axi_clk", "gpu3d_clk",
 204                                 "gpu3d_shader_clk";
 205                         resets = <&src 0>;
 206                         reset-names = "gpu3d";
 207                         power-domains = <&gpc 1>;
 208                 };
 209
 210                 caam_sm: caam-sm@00100000 {
 211                         compatible = "fsl,imx6q-caam-sm";
 212                         reg = <0x00100000 0x3fff>;
 213                 };
 214
 215                 dma_apbh: dma-apbh@01804000 {
 216                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 217                         reg = <0x01804000 0x2000>;
 218                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 222                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 223                         #dma-cells = <1>;
 224                         dma-channels = <4>;
 225                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 226                 };
 227
 228                 irq_sec_vio: caam_secvio {
 229                         compatible = "fsl,imx6q-caam-secvio";
 230                         interrupts = <0 20 0x04>;
 231                         secvio_src = <0x8000001d>;
 232                 };
 233
 234                 gpmi: gpmi-nand@01806000{
 235                         compatible = "fsl,imx6sx-gpmi-nand";
 236                         #address-cells = <1>;
 237                         #size-cells = <1>;
 238                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 239                         reg-names = "gpmi-nand", "bch";
 240                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 241                         interrupt-names = "bch";
 242                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 243                                  <&clks IMX6SX_CLK_GPMI_APB>,
 244                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 245                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 246                                  <&clks IMX6SX_CLK_PER1_BCH>;
 247                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 248                                       "gpmi_bch_apb", "per1_bch";
 249                         dmas = <&dma_apbh 0>;
 250                         dma-names = "rx-tx";
 251                         status = "disabled";
 252                 };
 253
 254                 aips1: aips-bus@02000000 {
 255                         compatible = "fsl,aips-bus", "simple-bus";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         reg = <0x02000000 0x100000>;
 259                         ranges;
 260
 261                         spba-bus@02000000 {
 262                                 compatible = "fsl,spba-bus", "simple-bus";
 263                                 #address-cells = <1>;
 264                                 #size-cells = <1>;
 265                                 reg = <0x02000000 0x40000>;
 266                                 ranges;
 267
 268                                 spdif: spdif@02004000 {
 269                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 270                                         reg = <0x02004000 0x4000>;
 271                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 272                                         dmas = <&sdma 14 18 0>,
 273                                                <&sdma 15 18 0>;
 274                                         dma-names = "rx", "tx";
 275                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 276                                                  <&clks IMX6SX_CLK_OSC>,
 277                                                  <&clks IMX6SX_CLK_SPDIF>,
 278                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 279                                                  <&clks IMX6SX_CLK_IPG>,
 280                                                  <&clks 0>, <&clks 0>,
 281                                                  <&clks IMX6SX_CLK_SPBA>;
 282                                         clock-names = "core", "rxtx0",
 283                                                       "rxtx1", "rxtx2",
 284                                                       "rxtx3", "rxtx4",
 285                                                       "rxtx5", "rxtx6",
 286                                                       "rxtx7", "dma";
 287                                         status = "disabled";
 288                                 };
 289
 290                                 ecspi1: ecspi@02008000 {
 291                                         #address-cells = <1>;
 292                                         #size-cells = <0>;
 293                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 294                                         reg = <0x02008000 0x4000>;
 295                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 297                                                  <&clks IMX6SX_CLK_ECSPI1>;
 298                                         clock-names = "ipg", "per";
 299                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 300                                         dma-names = "rx", "tx";
 301                                         status = "disabled";
 302                                 };
 303
 304                                 ecspi2: ecspi@0200c000 {
 305                                         #address-cells = <1>;
 306                                         #size-cells = <0>;
 307                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 308                                         reg = <0x0200c000 0x4000>;
 309                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 310                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 311                                                  <&clks IMX6SX_CLK_ECSPI2>;
 312                                         clock-names = "ipg", "per";
 313                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 314                                         dma-names = "rx", "tx";
 315                                         status = "disabled";
 316                                 };
 317
 318                                 ecspi3: ecspi@02010000 {
 319                                         #address-cells = <1>;
 320                                         #size-cells = <0>;
 321                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 322                                         reg = <0x02010000 0x4000>;
 323                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 324                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 325                                                  <&clks IMX6SX_CLK_ECSPI3>;
 326                                         clock-names = "ipg", "per";
 327                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 328                                         dma-names = "rx", "tx";
 329                                         status = "disabled";
 330                                 };
 331
 332                                 ecspi4: ecspi@02014000 {
 333                                         #address-cells = <1>;
 334                                         #size-cells = <0>;
 335                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 336                                         reg = <0x02014000 0x4000>;
 337                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 338                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 339                                                  <&clks IMX6SX_CLK_ECSPI4>;
 340                                         clock-names = "ipg", "per";
 341                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 342                                         dma-names = "rx", "tx";
 343                                         status = "disabled";
 344                                 };
 345
 346                                 uart1: serial@02020000 {
 347                                         compatible = "fsl,imx6sx-uart",
 348                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 349                                         reg = <0x02020000 0x4000>;
 350                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 351                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 352                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 353                                         clock-names = "ipg", "per";
 354                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 355                                         dma-names = "rx", "tx";
 356                                         status = "disabled";
 357                                 };
 358
 359                                 esai: esai@02024000 {
 360                                         compatible = "fsl,imx35-esai";
 361                                         reg = <0x02024000 0x4000>;
 362                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 363                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 364                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 365                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 366                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 367                                                  <&clks IMX6SX_CLK_SPBA>;
 368                                         clock-names = "core", "mem", "extal",
 369                                                       "fsys", "dma";
 370                                         dmas = <&sdma 23 21 0>,
 371                                                <&sdma 24 21 0>;
 372                                         dma-names = "rx", "tx";
 373                                         status = "disabled";
 374                                 };
 375
 376                                 ssi1: ssi@02028000 {
 377                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 378                                         reg = <0x02028000 0x4000>;
 379                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 380                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 381                                                  <&clks IMX6SX_CLK_SSI1>;
 382                                         clock-names = "ipg", "baud";
 383                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 384                                         dma-names = "rx", "tx";
 385                                         status = "disabled";
 386                                 };
 387
 388                                 ssi2: ssi@0202c000 {
 389                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 390                                         reg = <0x0202c000 0x4000>;
 391                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 392                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 393                                                  <&clks IMX6SX_CLK_SSI2>;
 394                                         clock-names = "ipg", "baud";
 395                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 396                                         dma-names = "rx", "tx";
 397                                         status = "disabled";
 398                                 };
 399
 400                                 ssi3: ssi@02030000 {
 401                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 402                                         reg = <0x02030000 0x4000>;
 403                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 404                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 405                                                  <&clks IMX6SX_CLK_SSI3>;
 406                                         clock-names = "ipg", "baud";
 407                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 408                                         dma-names = "rx", "tx";
 409                                         status = "disabled";
 410                                 };
 411
 412                                 asrc: asrc@02034000 {
 413                                         compatible = "fsl,imx53-asrc";
 414                                         reg = <0x02034000 0x4000>;
 415                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 416                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 417                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 418                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 419                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 420                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 421                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 422                                                 <&clks IMX6SX_CLK_SPBA>;
 423                                         clock-names = "mem", "ipg", "asrck_0",
 424                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 425                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 426                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 427                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 428                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 429                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 430                                         dma-names = "rxa", "rxb", "rxc",
 431                                                     "txa", "txb", "txc";
 432                                         fsl,asrc-rate  = <48000>;
 433                                         fsl,asrc-width = <16>;
 434                                         status = "okay";
 435                                 };
 436
 437                                 asrc_p2p: asrc_p2p {
 438                                         compatible = "fsl,imx6q-asrc-p2p";
 439                                         fsl,p2p-rate  = <48000>;
 440                                         fsl,p2p-width = <16>;
 441                                         fsl,asrc-dma-rx-events = <17 18 19>;
 442                                         fsl,asrc-dma-tx-events = <20 21 22>;
 443                                         status = "okay";
 444                                 };
 445                         };
 446
 447                         pwm1: pwm@02080000 {
 448                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 449                                 reg = <0x02080000 0x4000>;
 450                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 452                                          <&clks IMX6SX_CLK_PWM1>;
 453                                 clock-names = "ipg", "per";
 454                                 #pwm-cells = <2>;
 455                         };
 456
 457                         pwm2: pwm@02084000 {
 458                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 459                                 reg = <0x02084000 0x4000>;
 460                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 462                                          <&clks IMX6SX_CLK_PWM2>;
 463                                 clock-names = "ipg", "per";
 464                                 #pwm-cells = <2>;
 465                         };
 466
 467                         pwm3: pwm@02088000 {
 468                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 469                                 reg = <0x02088000 0x4000>;
 470                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 471                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 472                                          <&clks IMX6SX_CLK_PWM3>;
 473                                 clock-names = "ipg", "per";
 474                                 #pwm-cells = <2>;
 475                         };
 476
 477                         pwm4: pwm@0208c000 {
 478                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 479                                 reg = <0x0208c000 0x4000>;
 480                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 481                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 482                                          <&clks IMX6SX_CLK_PWM4>;
 483                                 clock-names = "ipg", "per";
 484                                 #pwm-cells = <2>;
 485                         };
 486
 487                         flexcan1: can@02090000 {
 488                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 489                                 reg = <0x02090000 0x4000>;
 490                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 491                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 492                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 493                                 clock-names = "ipg", "per";
 494                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 495                                 status = "disabled";
 496                         };
 497
 498                         flexcan2: can@02094000 {
 499                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 500                                 reg = <0x02094000 0x4000>;
 501                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 503                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 504                                 clock-names = "ipg", "per";
 505                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 506                                 status = "disabled";
 507                         };
 508
 509                         gpt: gpt@02098000 {
 510                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 511                                 reg = <0x02098000 0x4000>;
 512                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 514                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 515                                 clock-names = "ipg", "per";
 516                         };
 517
 518                         gpio1: gpio@0209c000 {
 519                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 520                                 reg = <0x0209c000 0x4000>;
 521                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 522                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 523                                 gpio-controller;
 524                                 #gpio-cells = <2>;
 525                                 interrupt-controller;
 526                                 #interrupt-cells = <2>;
 527                         };
 528
 529                         gpio2: gpio@020a0000 {
 530                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 531                                 reg = <0x020a0000 0x4000>;
 532                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 533                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 534                                 gpio-controller;
 535                                 #gpio-cells = <2>;
 536                                 interrupt-controller;
 537                                 #interrupt-cells = <2>;
 538                         };
 539
 540                         gpio3: gpio@020a4000 {
 541                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 542                                 reg = <0x020a4000 0x4000>;
 543                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 544                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 545                                 gpio-controller;
 546                                 #gpio-cells = <2>;
 547                                 interrupt-controller;
 548                                 #interrupt-cells = <2>;
 549                         };
 550
 551                         gpio4: gpio@020a8000 {
 552                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 553                                 reg = <0x020a8000 0x4000>;
 554                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 555                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 556                                 gpio-controller;
 557                                 #gpio-cells = <2>;
 558                                 interrupt-controller;
 559                                 #interrupt-cells = <2>;
 560                         };
 561
 562                         gpio5: gpio@020ac000 {
 563                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 564                                 reg = <0x020ac000 0x4000>;
 565                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 566                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 567                                 gpio-controller;
 568                                 #gpio-cells = <2>;
 569                                 interrupt-controller;
 570                                 #interrupt-cells = <2>;
 571                         };
 572
 573                         gpio6: gpio@020b0000 {
 574                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 575                                 reg = <0x020b0000 0x4000>;
 576                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 577                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 578                                 gpio-controller;
 579                                 #gpio-cells = <2>;
 580                                 interrupt-controller;
 581                                 #interrupt-cells = <2>;
 582                         };
 583
 584                         gpio7: gpio@020b4000 {
 585                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 586                                 reg = <0x020b4000 0x4000>;
 587                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 588                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 589                                 gpio-controller;
 590                                 #gpio-cells = <2>;
 591                                 interrupt-controller;
 592                                 #interrupt-cells = <2>;
 593                         };
 594
 595                         kpp: kpp@020b8000 {
 596                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 597                                 reg = <0x020b8000 0x4000>;
 598                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 599                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 600                                 status = "disabled";
 601                         };
 602
 603                         wdog1: wdog@020bc000 {
 604                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 605                                 reg = <0x020bc000 0x4000>;
 606                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 607                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 608                         };
 609
 610                         wdog2: wdog@020c0000 {
 611                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 612                                 reg = <0x020c0000 0x4000>;
 613                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 615                                 status = "disabled";
 616                         };
 617
 618                         clks: ccm@020c4000 {
 619                                 compatible = "fsl,imx6sx-ccm";
 620                                 reg = <0x020c4000 0x4000>;
 621                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 622                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 623                                 #clock-cells = <1>;
 624                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 625                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 626                         };
 627
 628                         anatop: anatop@020c8000 {
 629                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 630                                              "syscon", "simple-bus";
 631                                 reg = <0x020c8000 0x1000>;
 632                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 633                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 634                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 635
 636                                 regulator-1p1@110 {
 637                                         compatible = "fsl,anatop-regulator";
 638                                         regulator-name = "vdd1p1";
 639                                         regulator-min-microvolt = <800000>;
 640                                         regulator-max-microvolt = <1375000>;
 641                                         regulator-always-on;
 642                                         anatop-reg-offset = <0x110>;
 643                                         anatop-vol-bit-shift = <8>;
 644                                         anatop-vol-bit-width = <5>;
 645                                         anatop-min-bit-val = <4>;
 646                                         anatop-min-voltage = <800000>;
 647                                         anatop-max-voltage = <1375000>;
 648                                 };
 649
 650                                 regulator-3p0@120 {
 651                                         compatible = "fsl,anatop-regulator";
 652                                         regulator-name = "vdd3p0";
 653                                         regulator-min-microvolt = <2800000>;
 654                                         regulator-max-microvolt = <3150000>;
 655                                         regulator-always-on;
 656                                         anatop-reg-offset = <0x120>;
 657                                         anatop-vol-bit-shift = <8>;
 658                                         anatop-vol-bit-width = <5>;
 659                                         anatop-min-bit-val = <0>;
 660                                         anatop-min-voltage = <2625000>;
 661                                         anatop-max-voltage = <3400000>;
 662                                 };
 663
 664                                 regulator-2p5@130 {
 665                                         compatible = "fsl,anatop-regulator";
 666                                         regulator-name = "vdd2p5";
 667                                         regulator-min-microvolt = <2100000>;
 668                                         regulator-max-microvolt = <2875000>;
 669                                         regulator-always-on;
 670                                         anatop-reg-offset = <0x130>;
 671                                         anatop-vol-bit-shift = <8>;
 672                                         anatop-vol-bit-width = <5>;
 673                                         anatop-min-bit-val = <0>;
 674                                         anatop-min-voltage = <2100000>;
 675                                         anatop-max-voltage = <2875000>;
 676                                 };
 677
 678                                 reg_arm: regulator-vddcore@140 {
 679                                         compatible = "fsl,anatop-regulator";
 680                                         regulator-name = "cpu";
 681                                         regulator-min-microvolt = <725000>;
 682                                         regulator-max-microvolt = <1450000>;
 683                                         regulator-always-on;
 684                                         anatop-reg-offset = <0x140>;
 685                                         anatop-vol-bit-shift = <0>;
 686                                         anatop-vol-bit-width = <5>;
 687                                         anatop-delay-reg-offset = <0x170>;
 688                                         anatop-delay-bit-shift = <24>;
 689                                         anatop-delay-bit-width = <2>;
 690                                         anatop-min-bit-val = <1>;
 691                                         anatop-min-voltage = <725000>;
 692                                         anatop-max-voltage = <1450000>;
 693                                 };
 694
 695                                 reg_pcie_phy: regulator-vddpcie-phy@140 {
 696                                         compatible = "fsl,anatop-regulator";
 697                                         regulator-name = "vddpcie-phy";
 698                                         regulator-min-microvolt = <725000>;
 699                                         regulator-max-microvolt = <1450000>;
 700                                         anatop-reg-offset = <0x140>;
 701                                         anatop-vol-bit-shift = <9>;
 702                                         anatop-vol-bit-width = <5>;
 703                                         anatop-delay-reg-offset = <0x170>;
 704                                         anatop-delay-bit-shift = <26>;
 705                                         anatop-delay-bit-width = <2>;
 706                                         anatop-min-bit-val = <1>;
 707                                         anatop-min-voltage = <725000>;
 708                                         anatop-max-voltage = <1450000>;
 709                                 };
 710
 711                                 reg_soc: regulator-vddsoc@140 {
 712                                         compatible = "fsl,anatop-regulator";
 713                                         regulator-name = "vddsoc";
 714                                         regulator-min-microvolt = <725000>;
 715                                         regulator-max-microvolt = <1450000>;
 716                                         regulator-always-on;
 717                                         anatop-reg-offset = <0x140>;
 718                                         anatop-vol-bit-shift = <18>;
 719                                         anatop-vol-bit-width = <5>;
 720                                         anatop-delay-reg-offset = <0x170>;
 721                                         anatop-delay-bit-shift = <28>;
 722                                         anatop-delay-bit-width = <2>;
 723                                         anatop-min-bit-val = <1>;
 724                                         anatop-min-voltage = <725000>;
 725                                         anatop-max-voltage = <1450000>;
 726                                 };
 727                         };
 728
 729                         tempmon: tempmon {
 730                                 compatible = "fsl,imx6sx-tempmon";
 731                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 732                                 fsl,tempmon = <&anatop>;
 733                                 fsl,tempmon-data = <&ocotp>;
 734                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 735                         };
 736
 737                         usbphy1: usbphy@020c9000 {
 738                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 739                                 reg = <0x020c9000 0x1000>;
 740                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 741                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 742                                 fsl,anatop = <&anatop>;
 743                         };
 744
 745                         usbphy2: usbphy@020ca000 {
 746                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 747                                 reg = <0x020ca000 0x1000>;
 748                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 749                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 750                                 fsl,anatop = <&anatop>;
 751                         };
 752
 753                         mqs: mqs {
 754                                 compatible = "fsl,imx6sx-mqs";
 755                                 gpr = <&gpr>;
 756                                 status = "disabled";
 757                         };
 758
 759                         caam_snvs: caam-snvs@020cc000 {
 760                                 compatible = "fsl,imx6q-caam-snvs";
 761                                 reg = <0x020cc000 0x4000>;
 762                         };
 763
 764                         snvs: snvs@020cc000 {
 765                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 766                                 #address-cells = <1>;
 767                                 #size-cells = <1>;
 768                                 ranges = <0 0x020cc000 0x4000>;
 769
 770                                 snvs-rtc-lp@34 {
 771                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 772                                         reg = <0x34 0x58>;
 773                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 774                                 };
 775                         };
 776
 777                         snvs-pwrkey@0x020cc000 {
 778                                 compatible = "fsl,imx6sx-snvs-pwrkey";
 779                                 reg = <0x020cc000 0x4000>;
 780                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 781                                 fsl,keycode = <116>; /* KEY_POWER */
 782                                 fsl,wakeup;
 783                         };
 784
 785                         epit1: epit@020d0000 {
 786                                 reg = <0x020d0000 0x4000>;
 787                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 788                         };
 789
 790                         epit2: epit@020d4000 {
 791                                 reg = <0x020d4000 0x4000>;
 792                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 793                         };
 794
 795                         src: src@020d8000 {
 796                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 797                                 reg = <0x020d8000 0x4000>;
 798                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 799                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 800                                 #reset-cells = <1>;
 801                         };
 802
 803                         gpc: gpc@020dc000 {
 804                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 805                                 reg = <0x020dc000 0x4000>;
 806                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 807                                 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
 808                                 clocks = <&clks IMX6SX_CLK_GPU>;
 809                                 #power-domain-cells = <1>;
 810                         };
 811
 812                         iomuxc: iomuxc@020e0000 {
 813                                 compatible = "fsl,imx6sx-iomuxc";
 814                                 reg = <0x020e0000 0x4000>;
 815                         };
 816
 817                         gpr: iomuxc-gpr@020e4000 {
 818                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 819                                 reg = <0x020e4000 0x4000>;
 820                         };
 821
 822                         canfd1: canfd@020e8000 {
 823                                 compatible = "bosch,m_can";
 824                                 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
 825                                 reg-names = "canfd", "message_ram";
 826                                 interrupts = <0 114 0x04>;
 827                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 828                                 mram-cfg = <0x0 0 0 32 0 0 0 1>;
 829                                 status = "disabled";
 830                         };
 831
 832                         canfd2: canfd@020f0000 {
 833                                 compatible = "bosch,m_can";
 834                                 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
 835                                 reg-names = "canfd", "message_ram";
 836                                 interrupts = <0 115 0x04>;
 837                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 838                                 mram-cfg = <0x400 0 0 32 0 0 0 1>;
 839                                 status = "disabled";
 840                         };
 841
 842                         ldb: ldb@020e0014 {
 843                                 #address-cells = <1>;
 844                                 #size-cells = <0>;
 845                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 846                                 gpr = <&gpr>;
 847                                 status = "disabled";
 848
 849                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 850                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 851                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 852                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 853                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 854                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 855                                 clock-names = "ldb_di0",
 856                                               "di0_sel",
 857                                               "di1_sel",
 858                                               "ldb_di0_div_3_5",
 859                                               "ldb_di0_div_7",
 860                                               "ldb_di0_div_sel";
 861
 862                                 lvds-channel@0 {
 863                                         reg = <0>;
 864                                         status = "disabled";
 865                                 };
 866                         };
 867
 868                         sdma: sdma@020ec000 {
 869                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 870                                 reg = <0x020ec000 0x4000>;
 871                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 873                                          <&clks IMX6SX_CLK_SDMA>;
 874                                 clock-names = "ipg", "ahb";
 875                                 #dma-cells = <3>;
 876                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 877                         };
 878                 };
 879
 880                 aips2: aips-bus@02100000 {
 881                         compatible = "fsl,aips-bus", "simple-bus";
 882                         #address-cells = <1>;
 883                         #size-cells = <1>;
 884                         reg = <0x02100000 0x100000>;
 885                         ranges;
 886
 887                         crypto: caam@2100000 {
 888                                 compatible = "fsl,sec-v4.0";
 889                                 #address-cells = <1>;
 890                                 #size-cells = <1>;
 891                                 reg = <0x2100000 0x40000>;
 892                                 ranges = <0 0x2100000 0x40000>;
 893                                 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
 894                                 clocks = <&clks 134>, <&clks 135>, <&clks 136> ,<&clks 213>;
 895                                 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
 896
 897                                 sec_jr0: jr0@1000 {
 898                                         compatible = "fsl,sec-v4.0-job-ring";
 899                                         reg = <0x1000 0x1000>;
 900                                         interrupt-parent = <&intc>;
 901                                         interrupts = <0 105 0x4>;
 902                                 };
 903
 904                                 sec_jr1: jr1@2000 {
 905                                         compatible = "fsl,sec-v4.0-job-ring";
 906                                         reg = <0x2000 0x1000>;
 907                                         interrupt-parent = <&intc>;
 908                                         interrupts = <0 106 0x4>;
 909                                 };
 910                         };
 911
 912                         usbotg1: usb@02184000 {
 913                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 914                                 reg = <0x02184000 0x200>;
 915                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 917                                 fsl,usbphy = <&usbphy1>;
 918                                 fsl,usbmisc = <&usbmisc 0>;
 919                                 fsl,anatop = <&anatop>;
 920                                 status = "disabled";
 921                         };
 922
 923                         usbotg2: usb@02184200 {
 924                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 925                                 reg = <0x02184200 0x200>;
 926                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 928                                 fsl,usbphy = <&usbphy2>;
 929                                 fsl,usbmisc = <&usbmisc 1>;
 930                                 status = "disabled";
 931                         };
 932
 933                         usbh: usb@02184400 {
 934                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 935                                 reg = <0x02184400 0x200>;
 936                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 937                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 938                                 fsl,usbmisc = <&usbmisc 2>;
 939                                 phy_type = "hsic";
 940                                 fsl,anatop = <&anatop>;
 941                                 status = "disabled";
 942                         };
 943
 944                         usbmisc: usbmisc@02184800 {
 945                                 #index-cells = <1>;
 946                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 947                                 reg = <0x02184800 0x200>;
 948                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 949                         };
 950
 951                         fec1: ethernet@02188000 {
 952                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 953                                 reg = <0x02188000 0x4000>;
 954                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 955                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 956                                 clocks = <&clks IMX6SX_CLK_ENET>,
 957                                          <&clks IMX6SX_CLK_ENET_AHB>,
 958                                          <&clks IMX6SX_CLK_ENET_PTP>,
 959                                          <&clks IMX6SX_CLK_ENET_REF>,
 960                                          <&clks IMX6SX_CLK_ENET_PTP>;
 961                                 clock-names = "ipg", "ahb", "ptp",
 962                                               "enet_clk_ref", "enet_out";
 963                                 fsl,num-tx-queues=<3>;
 964                                 fsl,num-rx-queues=<3>;
 965                                 status = "disabled";
 966                         };
 967
 968                         mlb: mlb@0218c000 {
 969                                 reg = <0x0218c000 0x4000>;
 970                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 971                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 972                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 973                                 clocks = <&clks IMX6SX_CLK_MLB>;
 974                                 status = "disabled";
 975                         };
 976
 977                         usdhc1: usdhc@02190000 {
 978                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 979                                 reg = <0x02190000 0x4000>;
 980                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 981                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 982                                          <&clks IMX6SX_CLK_USDHC1>,
 983                                          <&clks IMX6SX_CLK_USDHC1>;
 984                                 clock-names = "ipg", "ahb", "per";
 985                                 bus-width = <4>;
 986                                 status = "disabled";
 987                         };
 988
 989                         usdhc2: usdhc@02194000 {
 990                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 991                                 reg = <0x02194000 0x4000>;
 992                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 993                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 994                                          <&clks IMX6SX_CLK_USDHC2>,
 995                                          <&clks IMX6SX_CLK_USDHC2>;
 996                                 clock-names = "ipg", "ahb", "per";
 997                                 bus-width = <4>;
 998                                 status = "disabled";
 999                         };
1000
1001                         usdhc3: usdhc@02198000 {
1002                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1003                                 reg = <0x02198000 0x4000>;
1004                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1005                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
1006                                          <&clks IMX6SX_CLK_USDHC3>,
1007                                          <&clks IMX6SX_CLK_USDHC3>;
1008                                 clock-names = "ipg", "ahb", "per";
1009                                 bus-width = <4>;
1010                                 status = "disabled";
1011                         };
1012
1013                         usdhc4: usdhc@0219c000 {
1014                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1015                                 reg = <0x0219c000 0x4000>;
1016                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
1018                                          <&clks IMX6SX_CLK_USDHC4>,
1019                                          <&clks IMX6SX_CLK_USDHC4>;
1020                                 clock-names = "ipg", "ahb", "per";
1021                                 bus-width = <4>;
1022                                 status = "disabled";
1023                         };
1024
1025                         i2c1: i2c@021a0000 {
1026                                 #address-cells = <1>;
1027                                 #size-cells = <0>;
1028                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1029                                 reg = <0x021a0000 0x4000>;
1030                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1031                                 clocks = <&clks IMX6SX_CLK_I2C1>;
1032                                 status = "disabled";
1033                         };
1034
1035                         i2c2: i2c@021a4000 {
1036                                 #address-cells = <1>;
1037                                 #size-cells = <0>;
1038                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1039                                 reg = <0x021a4000 0x4000>;
1040                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1041                                 clocks = <&clks IMX6SX_CLK_I2C2>;
1042                                 status = "disabled";
1043                         };
1044
1045                         i2c3: i2c@021a8000 {
1046                                 #address-cells = <1>;
1047                                 #size-cells = <0>;
1048                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1049                                 reg = <0x021a8000 0x4000>;
1050                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1051                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1052                                 status = "disabled";
1053                         };
1054
1055                         mmdc: mmdc@021b0000 {
1056                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1057                                 reg = <0x021b0000 0x4000>;
1058                         };
1059
1060                         fec2: ethernet@021b4000 {
1061                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1062                                 reg = <0x021b4000 0x4000>;
1063                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1064                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clks IMX6SX_CLK_ENET>,
1066                                          <&clks IMX6SX_CLK_ENET_AHB>,
1067                                          <&clks IMX6SX_CLK_ENET_PTP>,
1068                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1069                                          <&clks IMX6SX_CLK_ENET_PTP>;
1070                                 clock-names = "ipg", "ahb", "ptp",
1071                                               "enet_clk_ref", "enet_out";
1072                                 status = "disabled";
1073                         };
1074
1075                         weim: weim@021b8000 {
1076                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1077                                 reg = <0x021b8000 0x4000>;
1078                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1079                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1080                         };
1081
1082                         ocotp: ocotp-ctrl@021bc000 {
1083                                 compatible = "syscon";
1084                                 reg = <0x021bc000 0x4000>;
1085                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1086                         };
1087
1088                         ocotp-fuse@021bc000 {
1089                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
1090                                 reg = <0x021bc000 0x4000>;
1091                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1092                         };
1093
1094                         romcp@021ac000 {
1095                                 compatible = "fsl,imx6sx-romcp", "syscon";
1096                                 reg = <0x021ac000 0x4000>;
1097                         };
1098
1099                         sai1: sai@021d4000 {
1100                                 compatible = "fsl,imx6sx-sai";
1101                                 reg = <0x021d4000 0x4000>;
1102                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1103                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1104                                          <&clks IMX6SX_CLK_SAI1>,
1105                                          <&clks 0>, <&clks 0>;
1106                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1107                                 dma-names = "rx", "tx";
1108                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
1109                                 dma-source = <&gpr 0 15 0 16>;
1110                                 status = "disabled";
1111                         };
1112
1113                         audmux: audmux@021d8000 {
1114                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1115                                 reg = <0x021d8000 0x4000>;
1116                                 status = "disabled";
1117                         };
1118
1119                         sai2: sai@021dc000 {
1120                                 compatible = "fsl,imx6sx-sai";
1121                                 reg = <0x021dc000 0x4000>;
1122                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1123                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1124                                          <&clks IMX6SX_CLK_SAI2>,
1125                                          <&clks 0>, <&clks 0>;
1126                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1127                                 dma-names = "rx", "tx";
1128                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1129                                 dma-source = <&gpr 0 17 0 18>;
1130                                 status = "disabled";
1131                         };
1132
1133                         qspi1: qspi@021e0000 {
1134                                 #address-cells = <1>;
1135                                 #size-cells = <0>;
1136                                 compatible = "fsl,imx6sx-qspi";
1137                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1138                                 reg-names = "QuadSPI", "QuadSPI-memory";
1139                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1140                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1141                                          <&clks IMX6SX_CLK_QSPI1>;
1142                                 clock-names = "qspi_en", "qspi";
1143                                 status = "disabled";
1144                         };
1145
1146                         qspi2: qspi@021e4000 {
1147                                 #address-cells = <1>;
1148                                 #size-cells = <0>;
1149                                 compatible = "fsl,imx6sx-qspi";
1150                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1151                                 reg-names = "QuadSPI", "QuadSPI-memory";
1152                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1153                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1154                                          <&clks IMX6SX_CLK_QSPI2>;
1155                                 clock-names = "qspi_en", "qspi";
1156                                 status = "disabled";
1157                         };
1158
1159                         qspi_m4: qspi-m4 {
1160                                 compatible = "fsl,imx6sx-qspi-m4-restore";
1161                                 reg = <0x021e4000 0x4000>;
1162                                 status = "disabled";
1163                         };
1164
1165                         uart2: serial@021e8000 {
1166                                 compatible = "fsl,imx6sx-uart",
1167                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1168                                 reg = <0x021e8000 0x4000>;
1169                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1170                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1171                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1172                                 clock-names = "ipg", "per";
1173                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1174                                 dma-names = "rx", "tx";
1175                                 status = "disabled";
1176                         };
1177
1178                         uart3: serial@021ec000 {
1179                                 compatible = "fsl,imx6sx-uart",
1180                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1181                                 reg = <0x021ec000 0x4000>;
1182                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1183                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1184                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1185                                 clock-names = "ipg", "per";
1186                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1187                                 dma-names = "rx", "tx";
1188                                 status = "disabled";
1189                         };
1190
1191                         uart4: serial@021f0000 {
1192                                 compatible = "fsl,imx6sx-uart",
1193                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1194                                 reg = <0x021f0000 0x4000>;
1195                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1196                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1197                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1198                                 clock-names = "ipg", "per";
1199                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1200                                 dma-names = "rx", "tx";
1201                                 status = "disabled";
1202                         };
1203
1204                         uart5: serial@021f4000 {
1205                                 compatible = "fsl,imx6sx-uart",
1206                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1207                                 reg = <0x021f4000 0x4000>;
1208                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1209                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1210                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1211                                 clock-names = "ipg", "per";
1212                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1213                                 dma-names = "rx", "tx";
1214                                 status = "disabled";
1215                         };
1216
1217                         i2c4: i2c@021f8000 {
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1221                                 reg = <0x021f8000 0x4000>;
1222                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1223                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1224                                 status = "disabled";
1225                         };
1226                 };
1227
1228                 aips3: aips-bus@02200000 {
1229                         compatible = "fsl,aips-bus", "simple-bus";
1230                         #address-cells = <1>;
1231                         #size-cells = <1>;
1232                         reg = <0x02200000 0x100000>;
1233                         ranges;
1234
1235                         spba-bus@02200000 {
1236                                 compatible = "fsl,spba-bus", "simple-bus";
1237                                 #address-cells = <1>;
1238                                 #size-cells = <1>;
1239                                 reg = <0x02240000 0x40000>;
1240                                 ranges;
1241
1242                                 dcic1: dcic@0220c000 {
1243                                         compatible = "fsl,imx6sx-dcic";
1244                                         reg = <0x0220c000 0x4000>;
1245                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1246                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1247                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1248                                         clock-names = "dcic", "disp-axi";
1249                                         gpr = <&gpr>;
1250                                         status = "disabled";
1251                                 };
1252
1253                                 dcic2: dcic@02210000 {
1254                                         compatible = "fsl,imx6sx-dcic";
1255                                         reg = <0x02210000 0x4000>;
1256                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1257                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1258                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1259                                         clock-names = "dcic", "disp-axi";
1260                                         gpr = <&gpr>;
1261                                         status = "disabled";
1262                                 };
1263
1264                                 csi1: csi@02214000 {
1265                                         compatible = "fsl,imx6s-csi";
1266                                         reg = <0x02214000 0x4000>;
1267                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1268                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1269                                                  <&clks IMX6SX_CLK_CSI>,
1270                                                  <&clks IMX6SX_CLK_DCIC1>;
1271                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1272                                         status = "disabled";
1273                                 };
1274
1275                                 pxp: pxp@02218000 {
1276                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1277                                         reg = <0x02218000 0x4000>;
1278                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1279                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1280                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1281                                         clock-names = "pxp-axi", "disp-axi";
1282                                         status = "disabled";
1283                                 };
1284
1285                                 csi2: csi@0221c000 {
1286                                         compatible = "fsl,imx6s-csi";
1287                                         reg = <0x0221c000 0x4000>;
1288                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1289                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1290                                                  <&clks IMX6SX_CLK_CSI>,
1291                                                  <&clks IMX6SX_CLK_DCIC2>;
1292                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1293                                         status = "disabled";
1294                                 };
1295
1296                                 lcdif1: lcdif@02220000 {
1297                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1298                                         reg = <0x02220000 0x4000>;
1299                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1300                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1301                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1302                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1303                                         clock-names = "pix", "axi", "disp_axi";
1304                                         status = "disabled";
1305                                 };
1306
1307                                 lcdif2: lcdif@02224000 {
1308                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1309                                         reg = <0x02224000 0x4000>;
1310                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1311                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1312                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1313                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1314                                         clock-names = "pix", "axi", "disp_axi";
1315                                         status = "disabled";
1316                                 };
1317
1318                                 vadc: vadc@02228000 {
1319                                         compatible = "fsl,imx6sx-vadc";
1320                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1321                                         reg-names = "vadc-vafe", "vadc-vdec";
1322                                         clocks = <&clks IMX6SX_CLK_VADC>,
1323                                                  <&clks IMX6SX_CLK_CSI>;
1324                                         clock-names = "vadc", "csi";
1325                                         gpr = <&gpr>;
1326                                         status = "disabled";
1327                                 };
1328                         };
1329
1330                         adc1: adc@02280000 {
1331                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1332                                 reg = <0x02280000 0x4000>;
1333                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1334                                 clocks = <&clks IMX6SX_CLK_IPG>;
1335                                 num-channels = <4>;
1336                                 clock-names = "adc";
1337                                 status = "disabled";
1338                         };
1339
1340                         adc2: adc@02284000 {
1341                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1342                                 reg = <0x02284000 0x4000>;
1343                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1344                                 clocks = <&clks IMX6SX_CLK_IPG>;
1345                                 num-channels = <4>;
1346                                 clock-names = "adc";
1347                                 status = "disabled";
1348                         };
1349
1350                         wdog3: wdog@02288000 {
1351                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1352                                 reg = <0x02288000 0x4000>;
1353                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1354                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1355                                 status = "disabled";
1356                         };
1357
1358                         ecspi5: ecspi@0228c000 {
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1362                                 reg = <0x0228c000 0x4000>;
1363                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1364                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1365                                          <&clks IMX6SX_CLK_ECSPI5>;
1366                                 clock-names = "ipg", "per";
1367                                 status = "disabled";
1368                         };
1369
1370                         sema4: sema4@02290000 { /* sema4 */
1371                                 compatible = "fsl,imx6sx-sema4";
1372                                 reg = <0x02290000 0x4000>;
1373                                 interrupts = <0 116 0x04>;
1374                                 status = "okay";
1375                         };
1376
1377                         mu: mu@02294000 { /* mu */
1378                                 compatible = "fsl,imx6sx-mu";
1379                                 reg = <0x02294000 0x4000>;
1380                                 interrupts = <0 90 0x04>;
1381                                 status = "okay";
1382                         };
1383
1384                         mcctest: mcctest{
1385                                 compatible = "fsl,imx6sx-mcc-test";
1386                                 status = "disabled";
1387                         };
1388
1389                         mcctty: mcctty{
1390                                 compatible = "fsl,imx6sx-mcc-tty";
1391                                 status = "disabled";
1392                         };
1393
1394                         uart6: serial@022a0000 {
1395                                 compatible = "fsl,imx6sx-uart",
1396                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1397                                 reg = <0x022a0000 0x4000>;
1398                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1399                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1400                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1401                                 clock-names = "ipg", "per";
1402                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1403                                 dma-names = "rx", "tx";
1404                                 status = "disabled";
1405                         };
1406
1407                         pwm5: pwm@022a4000 {
1408                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1409                                 reg = <0x022a4000 0x4000>;
1410                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1411                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1412                                          <&clks IMX6SX_CLK_PWM5>;
1413                                 clock-names = "ipg", "per";
1414                                 #pwm-cells = <2>;
1415                         };
1416
1417                         pwm6: pwm@022a8000 {
1418                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1419                                 reg = <0x022a8000 0x4000>;
1420                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1421                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1422                                          <&clks IMX6SX_CLK_PWM6>;
1423                                 clock-names = "ipg", "per";
1424                                 #pwm-cells = <2>;
1425                         };
1426
1427                         pwm7: pwm@022ac000 {
1428                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1429                                 reg = <0x022ac000 0x4000>;
1430                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1431                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1432                                          <&clks IMX6SX_CLK_PWM7>;
1433                                 clock-names = "ipg", "per";
1434                                 #pwm-cells = <2>;
1435                         };
1436
1437                         pwm8: pwm@0022b0000 {
1438                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1439                                 reg = <0x0022b0000 0x4000>;
1440                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1441                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1442                                          <&clks IMX6SX_CLK_PWM8>;
1443                                 clock-names = "ipg", "per";
1444                                 #pwm-cells = <2>;
1445                         };
1446                 };
1447
1448                 pcie: pcie@0x08000000 {
1449                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1450                         reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
1451                         reg-names = "dbi", "config";
1452                         #address-cells = <3>;
1453                         #size-cells = <2>;
1454                         device_type = "pci";
1455                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1456                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1457                         num-lanes = <1>;
1458                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1459                         interrupt-names = "msi";
1460                         #interrupt-cells = <1>;
1461                         interrupt-map-mask = <0 0 0 0x7>;
1462                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1463                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1464                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1465                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1466                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1467                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1468                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1469                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1470                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1471                         pcie-phy-supply = <&reg_pcie_phy>;
1472                         status = "disabled";
1473                 };
1474         };
1475 };