arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                         >;
  66                         fsl,soc-operating-points = <
  67                                 /* ARM kHz  SOC uV */
  68                                 996000      1175000
  69                                 792000      1175000
  70                                 396000      1175000
  71                         >;
  72                         clock-latency = <61036>; /* two CLK32 periods */
  73                         clocks = <&clks IMX6SX_CLK_ARM>,
  74                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6SX_CLK_STEP>,
  76                                  <&clks IMX6SX_CLK_PLL1_SW>,
  77                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  78                         clock-names = "arm", "pll2_pfd2_396m", "step",
  79                                       "pll1_sw", "pll1_sys";
  80                         arm-supply = <&reg_arm>;
  81                         soc-supply = <&reg_soc>;
  82                 };
  83         };
  84
  85         intc: interrupt-controller@00a01000 {
  86                 compatible = "arm,cortex-a9-gic";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x00a01000 0x1000>,
  90                       <0x00a00100 0x100>;
  91         };
  92
  93         clocks {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ckil: clock@0 {
  98                         compatible = "fixed-clock";
  99                         reg = <0>;
 100                         #clock-cells = <0>;
 101                         clock-frequency = <32768>;
 102                         clock-output-names = "ckil";
 103                 };
 104
 105                 osc: clock@1 {
 106                         compatible = "fixed-clock";
 107                         reg = <1>;
 108                         #clock-cells = <0>;
 109                         clock-frequency = <24000000>;
 110                         clock-output-names = "osc";
 111                 };
 112
 113                 ipp_di0: clock@2 {
 114                         compatible = "fixed-clock";
 115                         reg = <2>;
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                         clock-output-names = "ipp_di0";
 119                 };
 120
 121                 ipp_di1: clock@3 {
 122                         compatible = "fixed-clock";
 123                         reg = <3>;
 124                         #clock-cells = <0>;
 125                         clock-frequency = <0>;
 126                         clock-output-names = "ipp_di1";
 127                 };
 128         };
 129
 130         soc {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "simple-bus";
 134                 interrupt-parent = <&intc>;
 135                 ranges;
 136
 137                 pmu {
 138                         compatible = "arm,cortex-a9-pmu";
 139                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 140                 };
 141
 142                 ocram: sram@00900000 {
 143                         compatible = "mmio-sram";
 144                         reg = <0x00900000 0x20000>;
 145                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 146                 };
 147
 148                 L2: l2-cache@00a02000 {
 149                         compatible = "arm,pl310-cache";
 150                         reg = <0x00a02000 0x1000>;
 151                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 152                         cache-unified;
 153                         cache-level = <2>;
 154                         arm,tag-latency = <4 2 3>;
 155                         arm,data-latency = <4 2 3>;
 156                 };
 157
 158                 dma_apbh: dma-apbh@01804000 {
 159                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 160                         reg = <0x01804000 0x2000>;
 161                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 162                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 165                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 166                         #dma-cells = <1>;
 167                         dma-channels = <4>;
 168                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 169                 };
 170
 171                 gpmi: gpmi-nand@01806000{
 172                         compatible = "fsl,imx6sx-gpmi-nand";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 176                         reg-names = "gpmi-nand", "bch";
 177                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 178                         interrupt-names = "bch";
 179                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 180                                  <&clks IMX6SX_CLK_GPMI_APB>,
 181                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 182                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 183                                  <&clks IMX6SX_CLK_PER1_BCH>;
 184                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 185                                       "gpmi_bch_apb", "per1_bch";
 186                         dmas = <&dma_apbh 0>;
 187                         dma-names = "rx-tx";
 188                         status = "disabled";
 189                 };
 190
 191                 aips1: aips-bus@02000000 {
 192                         compatible = "fsl,aips-bus", "simple-bus";
 193                         #address-cells = <1>;
 194                         #size-cells = <1>;
 195                         reg = <0x02000000 0x100000>;
 196                         ranges;
 197
 198                         spba-bus@02000000 {
 199                                 compatible = "fsl,spba-bus", "simple-bus";
 200                                 #address-cells = <1>;
 201                                 #size-cells = <1>;
 202                                 reg = <0x02000000 0x40000>;
 203                                 ranges;
 204
 205                                 spdif: spdif@02004000 {
 206                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 207                                         reg = <0x02004000 0x4000>;
 208                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 209                                         dmas = <&sdma 14 18 0>,
 210                                                <&sdma 15 18 0>;
 211                                         dma-names = "rx", "tx";
 212                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 213                                                  <&clks IMX6SX_CLK_OSC>,
 214                                                  <&clks IMX6SX_CLK_SPDIF>,
 215                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 216                                                  <&clks IMX6SX_CLK_IPG>,
 217                                                  <&clks 0>, <&clks 0>,
 218                                                  <&clks IMX6SX_CLK_SPBA>;
 219                                         clock-names = "core", "rxtx0",
 220                                                       "rxtx1", "rxtx2",
 221                                                       "rxtx3", "rxtx4",
 222                                                       "rxtx5", "rxtx6",
 223                                                       "rxtx7", "dma";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi1: ecspi@02008000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x02008000 0x4000>;
 232                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 234                                                  <&clks IMX6SX_CLK_ECSPI1>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 ecspi2: ecspi@0200c000 {
 240                                         #address-cells = <1>;
 241                                         #size-cells = <0>;
 242                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 243                                         reg = <0x0200c000 0x4000>;
 244                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 245                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 246                                                  <&clks IMX6SX_CLK_ECSPI2>;
 247                                         clock-names = "ipg", "per";
 248                                         status = "disabled";
 249                                 };
 250
 251                                 ecspi3: ecspi@02010000 {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 255                                         reg = <0x02010000 0x4000>;
 256                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 257                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 258                                                  <&clks IMX6SX_CLK_ECSPI3>;
 259                                         clock-names = "ipg", "per";
 260                                         status = "disabled";
 261                                 };
 262
 263                                 ecspi4: ecspi@02014000 {
 264                                         #address-cells = <1>;
 265                                         #size-cells = <0>;
 266                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 267                                         reg = <0x02014000 0x4000>;
 268                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 270                                                  <&clks IMX6SX_CLK_ECSPI4>;
 271                                         clock-names = "ipg", "per";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 uart1: serial@02020000 {
 276                                         compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
 277                                         reg = <0x02020000 0x4000>;
 278                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 280                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 281                                         clock-names = "ipg", "per";
 282                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 283                                         dma-names = "rx", "tx";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 esai: esai@02024000 {
 288                                         reg = <0x02024000 0x4000>;
 289                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 290                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 291                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 292                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 293                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 294                                                  <&clks IMX6SX_CLK_SPBA>;
 295                                         clock-names = "core", "mem", "extal",
 296                                                       "fsys", "dma";
 297                                         status = "disabled";
 298                                 };
 299
 300                                 ssi1: ssi@02028000 {
 301                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 302                                         reg = <0x02028000 0x4000>;
 303                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 305                                                  <&clks IMX6SX_CLK_SSI1>;
 306                                         clock-names = "ipg", "baud";
 307                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 308                                         dma-names = "rx", "tx";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 ssi2: ssi@0202c000 {
 313                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 314                                         reg = <0x0202c000 0x4000>;
 315                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 316                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 317                                                  <&clks IMX6SX_CLK_SSI2>;
 318                                         clock-names = "ipg", "baud";
 319                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 320                                         dma-names = "rx", "tx";
 321                                         status = "disabled";
 322                                 };
 323
 324                                 ssi3: ssi@02030000 {
 325                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 326                                         reg = <0x02030000 0x4000>;
 327                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 328                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 329                                                  <&clks IMX6SX_CLK_SSI3>;
 330                                         clock-names = "ipg", "baud";
 331                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 332                                         dma-names = "rx", "tx";
 333                                         status = "disabled";
 334                                 };
 335
 336                                 asrc: asrc@02034000 {
 337                                         reg = <0x02034000 0x4000>;
 338                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 339                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 340                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 341                                                  <&clks IMX6SX_CLK_SPDIF>,
 342                                                  <&clks IMX6SX_CLK_SPBA>;
 343                                         clock-names = "mem", "ipg", "asrck", "dma";
 344                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 345                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 346                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 347                                         dma-names = "rxa", "rxb", "rxc",
 348                                                     "txa", "txb", "txc";
 349                                         status = "okay";
 350                                 };
 351                         };
 352
 353                         pwm1: pwm@02080000 {
 354                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 355                                 reg = <0x02080000 0x4000>;
 356                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 358                                          <&clks IMX6SX_CLK_PWM1>;
 359                                 clock-names = "ipg", "per";
 360                                 #pwm-cells = <2>;
 361                         };
 362
 363                         pwm2: pwm@02084000 {
 364                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 365                                 reg = <0x02084000 0x4000>;
 366                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 368                                          <&clks IMX6SX_CLK_PWM2>;
 369                                 clock-names = "ipg", "per";
 370                                 #pwm-cells = <2>;
 371                         };
 372
 373                         pwm3: pwm@02088000 {
 374                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 375                                 reg = <0x02088000 0x4000>;
 376                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 377                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 378                                          <&clks IMX6SX_CLK_PWM3>;
 379                                 clock-names = "ipg", "per";
 380                                 #pwm-cells = <2>;
 381                         };
 382
 383                         pwm4: pwm@0208c000 {
 384                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 385                                 reg = <0x0208c000 0x4000>;
 386                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 388                                          <&clks IMX6SX_CLK_PWM4>;
 389                                 clock-names = "ipg", "per";
 390                                 #pwm-cells = <2>;
 391                         };
 392
 393                         flexcan1: can@02090000 {
 394                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 395                                 reg = <0x02090000 0x4000>;
 396                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 397                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 398                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 399                                 clock-names = "ipg", "per";
 400                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 401                                 status = "disabled";
 402                         };
 403
 404                         flexcan2: can@02094000 {
 405                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 406                                 reg = <0x02094000 0x4000>;
 407                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 409                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 410                                 clock-names = "ipg", "per";
 411                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 412                                 status = "disabled";
 413                         };
 414
 415                         gpt: gpt@02098000 {
 416                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 417                                 reg = <0x02098000 0x4000>;
 418                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 419                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 420                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 421                                 clock-names = "ipg", "per";
 422                         };
 423
 424                         gpio1: gpio@0209c000 {
 425                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 426                                 reg = <0x0209c000 0x4000>;
 427                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 429                                 gpio-controller;
 430                                 #gpio-cells = <2>;
 431                                 interrupt-controller;
 432                                 #interrupt-cells = <2>;
 433                         };
 434
 435                         gpio2: gpio@020a0000 {
 436                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 437                                 reg = <0x020a0000 0x4000>;
 438                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 439                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 440                                 gpio-controller;
 441                                 #gpio-cells = <2>;
 442                                 interrupt-controller;
 443                                 #interrupt-cells = <2>;
 444                         };
 445
 446                         gpio3: gpio@020a4000 {
 447                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 448                                 reg = <0x020a4000 0x4000>;
 449                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 450                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 451                                 gpio-controller;
 452                                 #gpio-cells = <2>;
 453                                 interrupt-controller;
 454                                 #interrupt-cells = <2>;
 455                         };
 456
 457                         gpio4: gpio@020a8000 {
 458                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 459                                 reg = <0x020a8000 0x4000>;
 460                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 461                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 462                                 gpio-controller;
 463                                 #gpio-cells = <2>;
 464                                 interrupt-controller;
 465                                 #interrupt-cells = <2>;
 466                         };
 467
 468                         gpio5: gpio@020ac000 {
 469                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 470                                 reg = <0x020ac000 0x4000>;
 471                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 472                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 473                                 gpio-controller;
 474                                 #gpio-cells = <2>;
 475                                 interrupt-controller;
 476                                 #interrupt-cells = <2>;
 477                         };
 478
 479                         gpio6: gpio@020b0000 {
 480                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 481                                 reg = <0x020b0000 0x4000>;
 482                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 483                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 484                                 gpio-controller;
 485                                 #gpio-cells = <2>;
 486                                 interrupt-controller;
 487                                 #interrupt-cells = <2>;
 488                         };
 489
 490                         gpio7: gpio@020b4000 {
 491                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 492                                 reg = <0x020b4000 0x4000>;
 493                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 494                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 495                                 gpio-controller;
 496                                 #gpio-cells = <2>;
 497                                 interrupt-controller;
 498                                 #interrupt-cells = <2>;
 499                         };
 500
 501                         kpp: kpp@020b8000 {
 502                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 503                                 reg = <0x020b8000 0x4000>;
 504                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 505                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 506                                 status = "disabled";
 507                         };
 508
 509                         wdog1: wdog@020bc000 {
 510                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 511                                 reg = <0x020bc000 0x4000>;
 512                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 513                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 514                         };
 515
 516                         wdog2: wdog@020c0000 {
 517                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 518                                 reg = <0x020c0000 0x4000>;
 519                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 520                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 521                                 status = "disabled";
 522                         };
 523
 524                         clks: ccm@020c4000 {
 525                                 compatible = "fsl,imx6sx-ccm";
 526                                 reg = <0x020c4000 0x4000>;
 527                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 528                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 529                                 #clock-cells = <1>;
 530                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 531                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 532                         };
 533
 534                         anatop: anatop@020c8000 {
 535                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 536                                              "syscon", "simple-bus";
 537                                 reg = <0x020c8000 0x1000>;
 538                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 539                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 541
 542                                 regulator-1p1@110 {
 543                                         compatible = "fsl,anatop-regulator";
 544                                         regulator-name = "vdd1p1";
 545                                         regulator-min-microvolt = <800000>;
 546                                         regulator-max-microvolt = <1375000>;
 547                                         regulator-always-on;
 548                                         anatop-reg-offset = <0x110>;
 549                                         anatop-vol-bit-shift = <8>;
 550                                         anatop-vol-bit-width = <5>;
 551                                         anatop-min-bit-val = <4>;
 552                                         anatop-min-voltage = <800000>;
 553                                         anatop-max-voltage = <1375000>;
 554                                 };
 555
 556                                 regulator-3p0@120 {
 557                                         compatible = "fsl,anatop-regulator";
 558                                         regulator-name = "vdd3p0";
 559                                         regulator-min-microvolt = <2800000>;
 560                                         regulator-max-microvolt = <3150000>;
 561                                         regulator-always-on;
 562                                         anatop-reg-offset = <0x120>;
 563                                         anatop-vol-bit-shift = <8>;
 564                                         anatop-vol-bit-width = <5>;
 565                                         anatop-min-bit-val = <0>;
 566                                         anatop-min-voltage = <2625000>;
 567                                         anatop-max-voltage = <3400000>;
 568                                 };
 569
 570                                 regulator-2p5@130 {
 571                                         compatible = "fsl,anatop-regulator";
 572                                         regulator-name = "vdd2p5";
 573                                         regulator-min-microvolt = <2100000>;
 574                                         regulator-max-microvolt = <2875000>;
 575                                         regulator-always-on;
 576                                         anatop-reg-offset = <0x130>;
 577                                         anatop-vol-bit-shift = <8>;
 578                                         anatop-vol-bit-width = <5>;
 579                                         anatop-min-bit-val = <0>;
 580                                         anatop-min-voltage = <2100000>;
 581                                         anatop-max-voltage = <2875000>;
 582                                 };
 583
 584                                 reg_arm: regulator-vddcore@140 {
 585                                         compatible = "fsl,anatop-regulator";
 586                                         regulator-name = "cpu";
 587                                         regulator-min-microvolt = <725000>;
 588                                         regulator-max-microvolt = <1450000>;
 589                                         regulator-always-on;
 590                                         anatop-reg-offset = <0x140>;
 591                                         anatop-vol-bit-shift = <0>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-delay-reg-offset = <0x170>;
 594                                         anatop-delay-bit-shift = <24>;
 595                                         anatop-delay-bit-width = <2>;
 596                                         anatop-min-bit-val = <1>;
 597                                         anatop-min-voltage = <725000>;
 598                                         anatop-max-voltage = <1450000>;
 599                                 };
 600
 601                                 reg_pcie: regulator-vddpcie@140 {
 602                                         compatible = "fsl,anatop-regulator";
 603                                         regulator-name = "vddpcie";
 604                                         regulator-min-microvolt = <725000>;
 605                                         regulator-max-microvolt = <1450000>;
 606                                         anatop-reg-offset = <0x140>;
 607                                         anatop-vol-bit-shift = <9>;
 608                                         anatop-vol-bit-width = <5>;
 609                                         anatop-delay-reg-offset = <0x170>;
 610                                         anatop-delay-bit-shift = <26>;
 611                                         anatop-delay-bit-width = <2>;
 612                                         anatop-min-bit-val = <1>;
 613                                         anatop-min-voltage = <725000>;
 614                                         anatop-max-voltage = <1450000>;
 615                                 };
 616
 617                                 reg_soc: regulator-vddsoc@140 {
 618                                         compatible = "fsl,anatop-regulator";
 619                                         regulator-name = "vddsoc";
 620                                         regulator-min-microvolt = <725000>;
 621                                         regulator-max-microvolt = <1450000>;
 622                                         regulator-always-on;
 623                                         anatop-reg-offset = <0x140>;
 624                                         anatop-vol-bit-shift = <18>;
 625                                         anatop-vol-bit-width = <5>;
 626                                         anatop-delay-reg-offset = <0x170>;
 627                                         anatop-delay-bit-shift = <28>;
 628                                         anatop-delay-bit-width = <2>;
 629                                         anatop-min-bit-val = <1>;
 630                                         anatop-min-voltage = <725000>;
 631                                         anatop-max-voltage = <1450000>;
 632                                 };
 633                         };
 634
 635                         tempmon: tempmon {
 636                                 compatible = "fsl,imx6sx-tempmon";
 637                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 638                                 fsl,tempmon = <&anatop>;
 639                                 fsl,tempmon-data = <&ocotp>;
 640                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 641                         };
 642
 643                         usbphy1: usbphy@020c9000 {
 644                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 645                                 reg = <0x020c9000 0x1000>;
 646                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 648                                 fsl,anatop = <&anatop>;
 649                         };
 650
 651                         usbphy2: usbphy@020ca000 {
 652                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 653                                 reg = <0x020ca000 0x1000>;
 654                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 655                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 656                                 fsl,anatop = <&anatop>;
 657                         };
 658
 659                         snvs: snvs@020cc000 {
 660                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 661                                 #address-cells = <1>;
 662                                 #size-cells = <1>;
 663                                 ranges = <0 0x020cc000 0x4000>;
 664
 665                                 snvs-rtc-lp@34 {
 666                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 667                                         reg = <0x34 0x58>;
 668                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 669                                 };
 670                         };
 671
 672                         epit1: epit@020d0000 {
 673                                 reg = <0x020d0000 0x4000>;
 674                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 675                         };
 676
 677                         epit2: epit@020d4000 {
 678                                 reg = <0x020d4000 0x4000>;
 679                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 680                         };
 681
 682                         src: src@020d8000 {
 683                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 684                                 reg = <0x020d8000 0x4000>;
 685                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 686                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 687                                 #reset-cells = <1>;
 688                         };
 689
 690                         gpc: gpc@020dc000 {
 691                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 692                                 reg = <0x020dc000 0x4000>;
 693                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 694                         };
 695
 696                         iomuxc: iomuxc@020e0000 {
 697                                 compatible = "fsl,imx6sx-iomuxc";
 698                                 reg = <0x020e0000 0x4000>;
 699                         };
 700
 701                         gpr: iomuxc-gpr@020e4000 {
 702                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 703                                 reg = <0x020e4000 0x4000>;
 704                         };
 705
 706                         canfd1: canfd@020e8000 {
 707                                 compatible = "bosch,m_can";
 708                                 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
 709                                 reg-names = "canfd", "message_ram";
 710                                 interrupts = <0 114 0x04>;
 711                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 712                                 mram-cfg = <0x0 0 0 32 0 0 0 1>;
 713                                 status = "disabled";
 714                         };
 715
 716                         canfd2: canfd@020f0000 {
 717                                 compatible = "bosch,m_can";
 718                                 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
 719                                 reg-names = "canfd", "message_ram";
 720                                 interrupts = <0 115 0x04>;
 721                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 722                                 mram-cfg = <0x400 0 0 32 0 0 0 1>;
 723                                 status = "disabled";
 724                         };
 725
 726                         ldb: ldb@020e0014 {
 727                                 #address-cells = <1>;
 728                                 #size-cells = <0>;
 729                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 730                                 gpr = <&gpr>;
 731                                 status = "disabled";
 732
 733                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 734                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 735                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 736                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 737                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 738                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 739                                 clock-names = "ldb_di0",
 740                                               "di0_sel",
 741                                               "di1_sel",
 742                                               "ldb_di0_div_3_5",
 743                                               "ldb_di0_div_7",
 744                                               "ldb_di0_div_sel";
 745
 746                                 lvds-channel@0 {
 747                                         reg = <0>;
 748                                         status = "disabled";
 749                                 };
 750                         };
 751
 752                         sdma: sdma@020ec000 {
 753                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 754                                 reg = <0x020ec000 0x4000>;
 755                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 757                                          <&clks IMX6SX_CLK_SDMA>;
 758                                 clock-names = "ipg", "ahb";
 759                                 #dma-cells = <3>;
 760                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 761                         };
 762                 };
 763
 764                 aips2: aips-bus@02100000 {
 765                         compatible = "fsl,aips-bus", "simple-bus";
 766                         #address-cells = <1>;
 767                         #size-cells = <1>;
 768                         reg = <0x02100000 0x100000>;
 769                         ranges;
 770
 771                         usbotg1: usb@02184000 {
 772                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 773                                 reg = <0x02184000 0x200>;
 774                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 775                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 776                                 fsl,usbphy = <&usbphy1>;
 777                                 fsl,usbmisc = <&usbmisc 0>;
 778                                 fsl,anatop = <&anatop>;
 779                                 status = "disabled";
 780                         };
 781
 782                         usbotg2: usb@02184200 {
 783                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 784                                 reg = <0x02184200 0x200>;
 785                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 787                                 fsl,usbphy = <&usbphy2>;
 788                                 fsl,usbmisc = <&usbmisc 1>;
 789                                 status = "disabled";
 790                         };
 791
 792                         usbh: usb@02184400 {
 793                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 794                                 reg = <0x02184400 0x200>;
 795                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 796                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 797                                 fsl,usbmisc = <&usbmisc 2>;
 798                                 phy_type = "hsic";
 799                                 fsl,anatop = <&anatop>;
 800                                 status = "disabled";
 801                         };
 802
 803                         usbmisc: usbmisc@02184800 {
 804                                 #index-cells = <1>;
 805                                 compatible = "fsl,imx6sx-usbmisc";
 806                                 reg = <0x02184800 0x200>;
 807                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 808                         };
 809
 810                         fec1: ethernet@02188000 {
 811                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 812                                 reg = <0x02188000 0x4000>;
 813                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 814                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6SX_CLK_ENET>,
 816                                          <&clks IMX6SX_CLK_ENET_AHB>,
 817                                          <&clks IMX6SX_CLK_ENET_PTP>,
 818                                          <&clks IMX6SX_CLK_ENET_REF>,
 819                                          <&clks IMX6SX_CLK_ENET_PTP>;
 820                                 clock-names = "ipg", "ahb", "ptp",
 821                                               "enet_clk_ref", "enet_out";
 822                                 fsl,num-tx-queues=<3>;
 823                                 fsl,num-rx-queues=<3>;
 824                                 status = "disabled";
 825                         };
 826
 827                         mlb: mlb@0218c000 {
 828                                 reg = <0x0218c000 0x4000>;
 829                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 830                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 831                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clks IMX6SX_CLK_MLB>;
 833                                 status = "disabled";
 834                         };
 835
 836                         usdhc1: usdhc@02190000 {
 837                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 838                                 reg = <0x02190000 0x4000>;
 839                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 841                                          <&clks IMX6SX_CLK_USDHC1>,
 842                                          <&clks IMX6SX_CLK_USDHC1>;
 843                                 clock-names = "ipg", "ahb", "per";
 844                                 bus-width = <4>;
 845                                 status = "disabled";
 846                         };
 847
 848                         usdhc2: usdhc@02194000 {
 849                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 850                                 reg = <0x02194000 0x4000>;
 851                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 853                                          <&clks IMX6SX_CLK_USDHC2>,
 854                                          <&clks IMX6SX_CLK_USDHC2>;
 855                                 clock-names = "ipg", "ahb", "per";
 856                                 bus-width = <4>;
 857                                 status = "disabled";
 858                         };
 859
 860                         usdhc3: usdhc@02198000 {
 861                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 862                                 reg = <0x02198000 0x4000>;
 863                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 865                                          <&clks IMX6SX_CLK_USDHC3>,
 866                                          <&clks IMX6SX_CLK_USDHC3>;
 867                                 clock-names = "ipg", "ahb", "per";
 868                                 bus-width = <4>;
 869                                 status = "disabled";
 870                         };
 871
 872                         usdhc4: usdhc@0219c000 {
 873                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 874                                 reg = <0x0219c000 0x4000>;
 875                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 876                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 877                                          <&clks IMX6SX_CLK_USDHC4>,
 878                                          <&clks IMX6SX_CLK_USDHC4>;
 879                                 clock-names = "ipg", "ahb", "per";
 880                                 bus-width = <4>;
 881                                 status = "disabled";
 882                         };
 883
 884                         i2c1: i2c@021a0000 {
 885                                 #address-cells = <1>;
 886                                 #size-cells = <0>;
 887                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 888                                 reg = <0x021a0000 0x4000>;
 889                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 890                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 891                                 status = "disabled";
 892                         };
 893
 894                         i2c2: i2c@021a4000 {
 895                                 #address-cells = <1>;
 896                                 #size-cells = <0>;
 897                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 898                                 reg = <0x021a4000 0x4000>;
 899                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 900                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 901                                 status = "disabled";
 902                         };
 903
 904                         i2c3: i2c@021a8000 {
 905                                 #address-cells = <1>;
 906                                 #size-cells = <0>;
 907                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 908                                 reg = <0x021a8000 0x4000>;
 909                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 910                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 911                                 status = "disabled";
 912                         };
 913
 914                         mmdc: mmdc@021b0000 {
 915                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 916                                 reg = <0x021b0000 0x4000>;
 917                         };
 918
 919                         fec2: ethernet@021b4000 {
 920                                 compatible = "fsl,imx6sx-fec";
 921                                 reg = <0x021b4000 0x4000>;
 922                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 923                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clks IMX6SX_CLK_ENET>,
 925                                          <&clks IMX6SX_CLK_ENET_AHB>,
 926                                          <&clks IMX6SX_CLK_ENET_PTP>,
 927                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
 928                                          <&clks IMX6SX_CLK_ENET_PTP>;
 929                                 clock-names = "ipg", "ahb", "ptp",
 930                                               "enet_clk_ref", "enet_out";
 931                                 status = "disabled";
 932                         };
 933
 934                         weim: weim@021b8000 {
 935                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
 936                                 reg = <0x021b8000 0x4000>;
 937                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 938                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
 939                         };
 940
 941                         ocotp: ocotp-ctrl@021bc000 {
 942                                 compatible = "syscon";
 943                                 reg = <0x021bc000 0x4000>;
 944                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 945                         };
 946
 947                         ocotp-fuse@021bc000 {
 948                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
 949                                 reg = <0x021bc000 0x4000>;
 950                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 951                         };
 952
 953                         sai1: sai@021d4000 {
 954                                 compatible = "fsl,imx6sx-sai";
 955                                 reg = <0x021d4000 0x4000>;
 956                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 957                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
 958                                          <&clks IMX6SX_CLK_SAI1>,
 959                                          <&clks 0>, <&clks 0>;
 960                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 961                                 dma-names = "rx", "tx";
 962                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
 963                                 dma-source = <&gpr 0 15 0 16>;
 964                                 status = "disabled";
 965                         };
 966
 967                         audmux: audmux@021d8000 {
 968                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
 969                                 reg = <0x021d8000 0x4000>;
 970                                 status = "disabled";
 971                         };
 972
 973                         sai2: sai@021dc000 {
 974                                 compatible = "fsl,imx6sx-sai";
 975                                 reg = <0x021dc000 0x4000>;
 976                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 977                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
 978                                          <&clks IMX6SX_CLK_SAI2>,
 979                                          <&clks 0>, <&clks 0>;
 980                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 981                                 dma-names = "rx", "tx";
 982                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
 983                                 dma-source = <&gpr 0 17 0 18>;
 984                                 status = "disabled";
 985                         };
 986
 987                         qspi1: qspi@021e0000 {
 988                                 #address-cells = <1>;
 989                                 #size-cells = <0>;
 990                                 compatible = "fsl,imx6sx-qspi";
 991                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 992                                 reg-names = "QuadSPI", "QuadSPI-memory";
 993                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 994                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
 995                                          <&clks IMX6SX_CLK_QSPI1>;
 996                                 clock-names = "qspi_en", "qspi";
 997                                 status = "disabled";
 998                         };
 999
1000                         qspi2: qspi@021e4000 {
1001                                 #address-cells = <1>;
1002                                 #size-cells = <0>;
1003                                 compatible = "fsl,imx6sx-qspi";
1004                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1005                                 reg-names = "QuadSPI", "QuadSPI-memory";
1006                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1007                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1008                                          <&clks IMX6SX_CLK_QSPI2>;
1009                                 clock-names = "qspi_en", "qspi";
1010                                 status = "disabled";
1011                         };
1012
1013                         uart2: serial@021e8000 {
1014                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1015                                 reg = <0x021e8000 0x4000>;
1016                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1018                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1019                                 clock-names = "ipg", "per";
1020                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1021                                 dma-names = "rx", "tx";
1022                                 status = "disabled";
1023                         };
1024
1025                         uart3: serial@021ec000 {
1026                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1027                                 reg = <0x021ec000 0x4000>;
1028                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1029                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1030                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1031                                 clock-names = "ipg", "per";
1032                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1033                                 dma-names = "rx", "tx";
1034                                 status = "disabled";
1035                         };
1036
1037                         uart4: serial@021f0000 {
1038                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1039                                 reg = <0x021f0000 0x4000>;
1040                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1041                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1042                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1043                                 clock-names = "ipg", "per";
1044                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1045                                 dma-names = "rx", "tx";
1046                                 status = "disabled";
1047                         };
1048
1049                         uart5: serial@021f4000 {
1050                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1051                                 reg = <0x021f4000 0x4000>;
1052                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1053                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1054                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1055                                 clock-names = "ipg", "per";
1056                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1057                                 dma-names = "rx", "tx";
1058                                 status = "disabled";
1059                         };
1060
1061                         i2c4: i2c@021f8000 {
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1065                                 reg = <0x021f8000 0x4000>;
1066                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1067                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1068                                 status = "disabled";
1069                         };
1070                 };
1071
1072                 aips3: aips-bus@02200000 {
1073                         compatible = "fsl,aips-bus", "simple-bus";
1074                         #address-cells = <1>;
1075                         #size-cells = <1>;
1076                         reg = <0x02200000 0x100000>;
1077                         ranges;
1078
1079                         spba-bus@02200000 {
1080                                 compatible = "fsl,spba-bus", "simple-bus";
1081                                 #address-cells = <1>;
1082                                 #size-cells = <1>;
1083                                 reg = <0x02240000 0x40000>;
1084                                 ranges;
1085
1086                                 dcic1: dcic@0220c000 {
1087                                         compatible = "fsl,imx6sx-dcic";
1088                                         reg = <0x0220c000 0x4000>;
1089                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1090                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1091                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1092                                         clock-names = "dcic", "disp-axi";
1093                                         gpr = <&gpr>;
1094                                         status = "disabled";
1095                                 };
1096
1097                                 dcic2: dcic@02210000 {
1098                                         compatible = "fsl,imx6sx-dcic";
1099                                         reg = <0x02210000 0x4000>;
1100                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1101                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1102                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1103                                         clock-names = "dcic", "disp-axi";
1104                                         gpr = <&gpr>;
1105                                         status = "disabled";
1106                                 };
1107
1108                                 csi1: csi@02214000 {
1109                                         reg = <0x02214000 0x4000>;
1110                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1111                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1112                                                  <&clks IMX6SX_CLK_CSI>,
1113                                                  <&clks IMX6SX_CLK_DCIC1>;
1114                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1115                                         status = "disabled";
1116                                 };
1117
1118                                 pxp: pxp@02218000 {
1119                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1120                                         reg = <0x02218000 0x4000>;
1121                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1122                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1123                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1124                                         clock-names = "pxp-axi", "disp-axi";
1125                                         status = "disabled";
1126                                 };
1127
1128                                 csi2: csi@0221c000 {
1129                                         reg = <0x0221c000 0x4000>;
1130                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1131                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1132                                                  <&clks IMX6SX_CLK_CSI>,
1133                                                  <&clks IMX6SX_CLK_DCIC2>;
1134                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1135                                         status = "disabled";
1136                                 };
1137
1138                                 lcdif1: lcdif@02220000 {
1139                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1140                                         reg = <0x02220000 0x4000>;
1141                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1142                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1143                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1144                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1145                                         clock-names = "pix", "axi", "disp_axi";
1146                                         status = "disabled";
1147                                 };
1148
1149                                 lcdif2: lcdif@02224000 {
1150                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1151                                         reg = <0x02224000 0x4000>;
1152                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1153                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1154                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1155                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1156                                         clock-names = "pix", "axi", "disp_axi";
1157                                         status = "disabled";
1158                                 };
1159
1160                                 vadc: vadc@02228000 {
1161                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1162                                         reg-names = "vadc-vafe", "vadc-vdec";
1163                                         clocks = <&clks IMX6SX_CLK_VADC>,
1164                                                  <&clks IMX6SX_CLK_CSI>;
1165                                         clock-names = "vadc", "csi";
1166                                         status = "disabled";
1167                                 };
1168                         };
1169
1170                         adc1: adc@02280000 {
1171                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1172                                 reg = <0x02280000 0x4000>;
1173                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1174                                 clocks = <&clks IMX6SX_CLK_IPG>;
1175                                 num-channels = <4>;
1176                                 clock-names = "adc";
1177                                 status = "disabled";
1178                         };
1179
1180                         adc2: adc@02284000 {
1181                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1182                                 reg = <0x02284000 0x4000>;
1183                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1184                                 clocks = <&clks IMX6SX_CLK_IPG>;
1185                                 num-channels = <4>;
1186                                 clock-names = "adc";
1187                                 status = "disabled";
1188                         };
1189
1190                         wdog3: wdog@02288000 {
1191                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1192                                 reg = <0x02288000 0x4000>;
1193                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1194                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1195                                 status = "disabled";
1196                         };
1197
1198                         ecspi5: ecspi@0228c000 {
1199                                 #address-cells = <1>;
1200                                 #size-cells = <0>;
1201                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1202                                 reg = <0x0228c000 0x4000>;
1203                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1204                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1205                                          <&clks IMX6SX_CLK_ECSPI5>;
1206                                 clock-names = "ipg", "per";
1207                                 status = "disabled";
1208                         };
1209
1210                         uart6: serial@022a0000 {
1211                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1212                                 reg = <0x022a0000 0x4000>;
1213                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1214                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1215                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1216                                 clock-names = "ipg", "per";
1217                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1218                                 dma-names = "rx", "tx";
1219                                 status = "disabled";
1220                         };
1221
1222                         pwm5: pwm@022a4000 {
1223                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1224                                 reg = <0x022a4000 0x4000>;
1225                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1226                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1227                                          <&clks IMX6SX_CLK_PWM5>;
1228                                 clock-names = "ipg", "per";
1229                                 #pwm-cells = <2>;
1230                         };
1231
1232                         pwm6: pwm@022a8000 {
1233                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1234                                 reg = <0x022a8000 0x4000>;
1235                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1236                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1237                                          <&clks IMX6SX_CLK_PWM6>;
1238                                 clock-names = "ipg", "per";
1239                                 #pwm-cells = <2>;
1240                         };
1241
1242                         pwm7: pwm@022ac000 {
1243                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1244                                 reg = <0x022ac000 0x4000>;
1245                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1246                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1247                                          <&clks IMX6SX_CLK_PWM7>;
1248                                 clock-names = "ipg", "per";
1249                                 #pwm-cells = <2>;
1250                         };
1251
1252                         pwm8: pwm@0022b0000 {
1253                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1254                                 reg = <0x0022b0000 0x4000>;
1255                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1256                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1257                                          <&clks IMX6SX_CLK_PWM8>;
1258                                 clock-names = "ipg", "per";
1259                                 #pwm-cells = <2>;
1260                         };
1261                 };
1262
1263                 pcie: pcie@0x08000000 {
1264                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1265                         reg = <0x08ffc000 0x4000>; /* DBI */
1266                         #address-cells = <3>;
1267                         #size-cells = <2>;
1268                         device_type = "pci";
1269                                   /* configuration space */
1270                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1271                                   /* downstream I/O */
1272                                   0x81000000 0 0          0x08f80000 0 0x00010000
1273                                   /* non-prefetchable memory */
1274                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1275                         num-lanes = <1>;
1276                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1277                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1278                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1279                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1280                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1281                         clock-names = "pcie_ref_125m", "pcie_axi",
1282                                       "lvds_gate", "display_axi";
1283                         status = "disabled";
1284                 };
1285         };
1286 };