2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sx-pinfunc.h"
13 #include "skeleton.dtsi"
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
66 fsl,soc-operating-points = <
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <®_arm>;
81 soc-supply = <®_soc>;
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
89 reg = <0x00a01000 0x1000>,
98 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
114 compatible = "fixed-clock";
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
122 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
195 reg = <0x02000000 0x100000>;
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
202 reg = <0x02000000 0x40000>;
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
301 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
313 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
314 reg = <0x0202c000 0x4000>;
315 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
317 <&clks IMX6SX_CLK_SSI2>;
318 clock-names = "ipg", "baud";
319 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
320 dma-names = "rx", "tx";
325 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
326 reg = <0x02030000 0x4000>;
327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
329 <&clks IMX6SX_CLK_SSI3>;
330 clock-names = "ipg", "baud";
331 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
332 dma-names = "rx", "tx";
336 asrc: asrc@02034000 {
337 reg = <0x02034000 0x4000>;
338 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
340 <&clks IMX6SX_CLK_ASRC_IPG>,
341 <&clks IMX6SX_CLK_SPDIF>,
342 <&clks IMX6SX_CLK_SPBA>;
343 clock-names = "mem", "ipg", "asrck", "dma";
344 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
345 <&sdma 19 20 1>, <&sdma 20 20 1>,
346 <&sdma 21 20 1>, <&sdma 22 20 1>;
347 dma-names = "rxa", "rxb", "rxc",
354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
355 reg = <0x02080000 0x4000>;
356 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6SX_CLK_PWM1>,
358 <&clks IMX6SX_CLK_PWM1>;
359 clock-names = "ipg", "per";
364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
365 reg = <0x02084000 0x4000>;
366 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6SX_CLK_PWM2>,
368 <&clks IMX6SX_CLK_PWM2>;
369 clock-names = "ipg", "per";
374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
375 reg = <0x02088000 0x4000>;
376 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6SX_CLK_PWM3>,
378 <&clks IMX6SX_CLK_PWM3>;
379 clock-names = "ipg", "per";
384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385 reg = <0x0208c000 0x4000>;
386 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6SX_CLK_PWM4>,
388 <&clks IMX6SX_CLK_PWM4>;
389 clock-names = "ipg", "per";
393 flexcan1: can@02090000 {
394 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
395 reg = <0x02090000 0x4000>;
396 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
398 <&clks IMX6SX_CLK_CAN1_SERIAL>;
399 clock-names = "ipg", "per";
403 flexcan2: can@02094000 {
404 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
405 reg = <0x02094000 0x4000>;
406 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
408 <&clks IMX6SX_CLK_CAN2_SERIAL>;
409 clock-names = "ipg", "per";
414 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
415 reg = <0x02098000 0x4000>;
416 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
418 <&clks IMX6SX_CLK_GPT_SERIAL>;
419 clock-names = "ipg", "per";
422 gpio1: gpio@0209c000 {
423 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
424 reg = <0x0209c000 0x4000>;
425 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
433 gpio2: gpio@020a0000 {
434 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
435 reg = <0x020a0000 0x4000>;
436 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
444 gpio3: gpio@020a4000 {
445 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
446 reg = <0x020a4000 0x4000>;
447 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
455 gpio4: gpio@020a8000 {
456 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
457 reg = <0x020a8000 0x4000>;
458 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
466 gpio5: gpio@020ac000 {
467 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
468 reg = <0x020ac000 0x4000>;
469 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
477 gpio6: gpio@020b0000 {
478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479 reg = <0x020b0000 0x4000>;
480 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
488 gpio7: gpio@020b4000 {
489 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
490 reg = <0x020b4000 0x4000>;
491 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
500 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
501 reg = <0x020b8000 0x4000>;
502 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6SX_CLK_DUMMY>;
507 wdog1: wdog@020bc000 {
508 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
509 reg = <0x020bc000 0x4000>;
510 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6SX_CLK_DUMMY>;
514 wdog2: wdog@020c0000 {
515 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
516 reg = <0x020c0000 0x4000>;
517 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6SX_CLK_DUMMY>;
523 compatible = "fsl,imx6sx-ccm";
524 reg = <0x020c4000 0x4000>;
525 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
529 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
532 anatop: anatop@020c8000 {
533 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
534 "syscon", "simple-bus";
535 reg = <0x020c8000 0x1000>;
536 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "vdd1p1";
543 regulator-min-microvolt = <800000>;
544 regulator-max-microvolt = <1375000>;
546 anatop-reg-offset = <0x110>;
547 anatop-vol-bit-shift = <8>;
548 anatop-vol-bit-width = <5>;
549 anatop-min-bit-val = <4>;
550 anatop-min-voltage = <800000>;
551 anatop-max-voltage = <1375000>;
555 compatible = "fsl,anatop-regulator";
556 regulator-name = "vdd3p0";
557 regulator-min-microvolt = <2800000>;
558 regulator-max-microvolt = <3150000>;
560 anatop-reg-offset = <0x120>;
561 anatop-vol-bit-shift = <8>;
562 anatop-vol-bit-width = <5>;
563 anatop-min-bit-val = <0>;
564 anatop-min-voltage = <2625000>;
565 anatop-max-voltage = <3400000>;
569 compatible = "fsl,anatop-regulator";
570 regulator-name = "vdd2p5";
571 regulator-min-microvolt = <2100000>;
572 regulator-max-microvolt = <2875000>;
574 anatop-reg-offset = <0x130>;
575 anatop-vol-bit-shift = <8>;
576 anatop-vol-bit-width = <5>;
577 anatop-min-bit-val = <0>;
578 anatop-min-voltage = <2100000>;
579 anatop-max-voltage = <2875000>;
582 reg_arm: regulator-vddcore@140 {
583 compatible = "fsl,anatop-regulator";
584 regulator-name = "cpu";
585 regulator-min-microvolt = <725000>;
586 regulator-max-microvolt = <1450000>;
588 anatop-reg-offset = <0x140>;
589 anatop-vol-bit-shift = <0>;
590 anatop-vol-bit-width = <5>;
591 anatop-delay-reg-offset = <0x170>;
592 anatop-delay-bit-shift = <24>;
593 anatop-delay-bit-width = <2>;
594 anatop-min-bit-val = <1>;
595 anatop-min-voltage = <725000>;
596 anatop-max-voltage = <1450000>;
599 reg_pcie: regulator-vddpcie@140 {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vddpcie";
602 regulator-min-microvolt = <725000>;
603 regulator-max-microvolt = <1450000>;
604 anatop-reg-offset = <0x140>;
605 anatop-vol-bit-shift = <9>;
606 anatop-vol-bit-width = <5>;
607 anatop-delay-reg-offset = <0x170>;
608 anatop-delay-bit-shift = <26>;
609 anatop-delay-bit-width = <2>;
610 anatop-min-bit-val = <1>;
611 anatop-min-voltage = <725000>;
612 anatop-max-voltage = <1450000>;
615 reg_soc: regulator-vddsoc@140 {
616 compatible = "fsl,anatop-regulator";
617 regulator-name = "vddsoc";
618 regulator-min-microvolt = <725000>;
619 regulator-max-microvolt = <1450000>;
621 anatop-reg-offset = <0x140>;
622 anatop-vol-bit-shift = <18>;
623 anatop-vol-bit-width = <5>;
624 anatop-delay-reg-offset = <0x170>;
625 anatop-delay-bit-shift = <28>;
626 anatop-delay-bit-width = <2>;
627 anatop-min-bit-val = <1>;
628 anatop-min-voltage = <725000>;
629 anatop-max-voltage = <1450000>;
634 compatible = "fsl,imx6sx-tempmon";
635 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
636 fsl,tempmon = <&anatop>;
637 fsl,tempmon-data = <&ocotp>;
638 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
641 usbphy1: usbphy@020c9000 {
642 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
643 reg = <0x020c9000 0x1000>;
644 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clks IMX6SX_CLK_USBPHY1>;
646 fsl,anatop = <&anatop>;
649 usbphy2: usbphy@020ca000 {
650 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
651 reg = <0x020ca000 0x1000>;
652 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6SX_CLK_USBPHY2>;
654 fsl,anatop = <&anatop>;
657 snvs: snvs@020cc000 {
658 compatible = "fsl,sec-v4.0-mon", "simple-bus";
659 #address-cells = <1>;
661 ranges = <0 0x020cc000 0x4000>;
664 compatible = "fsl,sec-v4.0-mon-rtc-lp";
666 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
670 epit1: epit@020d0000 {
671 reg = <0x020d0000 0x4000>;
672 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
675 epit2: epit@020d4000 {
676 reg = <0x020d4000 0x4000>;
677 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
681 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
682 reg = <0x020d8000 0x4000>;
683 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
689 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
690 reg = <0x020dc000 0x4000>;
691 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
694 iomuxc: iomuxc@020e0000 {
695 compatible = "fsl,imx6sx-iomuxc";
696 reg = <0x020e0000 0x4000>;
699 gpr: iomuxc-gpr@020e4000 {
700 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
701 reg = <0x020e4000 0x4000>;
705 #address-cells = <1>;
707 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
711 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
712 <&clks IMX6SX_CLK_LCDIF1_SEL>,
713 <&clks IMX6SX_CLK_LCDIF2_SEL>,
714 <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
715 <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
716 <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
717 clock-names = "ldb_di0",
730 sdma: sdma@020ec000 {
731 compatible = "fsl,imx6sx-sdma";
732 reg = <0x020ec000 0x4000>;
733 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX6SX_CLK_SDMA>,
735 <&clks IMX6SX_CLK_SDMA>;
736 clock-names = "ipg", "ahb";
741 aips2: aips-bus@02100000 {
742 compatible = "fsl,aips-bus", "simple-bus";
743 #address-cells = <1>;
745 reg = <0x02100000 0x100000>;
748 usbotg1: usb@02184000 {
749 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
750 reg = <0x02184000 0x200>;
751 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clks IMX6SX_CLK_USBOH3>;
753 fsl,usbphy = <&usbphy1>;
754 fsl,usbmisc = <&usbmisc 0>;
755 fsl,anatop = <&anatop>;
759 usbotg2: usb@02184200 {
760 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
761 reg = <0x02184200 0x200>;
762 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX6SX_CLK_USBOH3>;
764 fsl,usbphy = <&usbphy2>;
765 fsl,usbmisc = <&usbmisc 1>;
770 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
771 reg = <0x02184400 0x200>;
772 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&clks IMX6SX_CLK_USBOH3>;
774 fsl,usbmisc = <&usbmisc 2>;
776 fsl,anatop = <&anatop>;
780 usbmisc: usbmisc@02184800 {
782 compatible = "fsl,imx6sx-usbmisc";
783 reg = <0x02184800 0x200>;
784 clocks = <&clks IMX6SX_CLK_USBOH3>;
787 fec1: ethernet@02188000 {
788 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
789 reg = <0x02188000 0x4000>;
790 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6SX_CLK_ENET>,
793 <&clks IMX6SX_CLK_ENET_AHB>,
794 <&clks IMX6SX_CLK_ENET_PTP>,
795 <&clks IMX6SX_CLK_ENET_REF>,
796 <&clks IMX6SX_CLK_ENET_PTP>;
797 clock-names = "ipg", "ahb", "ptp",
798 "enet_clk_ref", "enet_out";
803 reg = <0x0218c000 0x4000>;
804 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6SX_CLK_MLB>;
811 usdhc1: usdhc@02190000 {
812 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
813 reg = <0x02190000 0x4000>;
814 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SX_CLK_USDHC1>,
816 <&clks IMX6SX_CLK_USDHC1>,
817 <&clks IMX6SX_CLK_USDHC1>;
818 clock-names = "ipg", "ahb", "per";
823 usdhc2: usdhc@02194000 {
824 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
825 reg = <0x02194000 0x4000>;
826 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&clks IMX6SX_CLK_USDHC2>,
828 <&clks IMX6SX_CLK_USDHC2>,
829 <&clks IMX6SX_CLK_USDHC2>;
830 clock-names = "ipg", "ahb", "per";
835 usdhc3: usdhc@02198000 {
836 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
837 reg = <0x02198000 0x4000>;
838 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6SX_CLK_USDHC3>,
840 <&clks IMX6SX_CLK_USDHC3>,
841 <&clks IMX6SX_CLK_USDHC3>;
842 clock-names = "ipg", "ahb", "per";
847 usdhc4: usdhc@0219c000 {
848 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
849 reg = <0x0219c000 0x4000>;
850 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6SX_CLK_USDHC4>,
852 <&clks IMX6SX_CLK_USDHC4>,
853 <&clks IMX6SX_CLK_USDHC4>;
854 clock-names = "ipg", "ahb", "per";
860 #address-cells = <1>;
862 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
863 reg = <0x021a0000 0x4000>;
864 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6SX_CLK_I2C1>;
870 #address-cells = <1>;
872 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
873 reg = <0x021a4000 0x4000>;
874 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6SX_CLK_I2C2>;
880 #address-cells = <1>;
882 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
883 reg = <0x021a8000 0x4000>;
884 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SX_CLK_I2C3>;
889 mmdc: mmdc@021b0000 {
890 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
891 reg = <0x021b0000 0x4000>;
894 fec2: ethernet@021b4000 {
895 compatible = "fsl,imx6sx-fec";
896 reg = <0x021b4000 0x4000>;
897 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX6SX_CLK_ENET>,
900 <&clks IMX6SX_CLK_ENET_AHB>,
901 <&clks IMX6SX_CLK_ENET_PTP>,
902 <&clks IMX6SX_CLK_ENET2_REF_125M>,
903 <&clks IMX6SX_CLK_ENET_PTP>;
904 clock-names = "ipg", "ahb", "ptp",
905 "enet_clk_ref", "enet_out";
909 weim: weim@021b8000 {
910 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
911 reg = <0x021b8000 0x4000>;
912 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
916 ocotp: ocotp@021bc000 {
917 compatible = "fsl,imx6sx-ocotp", "syscon";
918 reg = <0x021bc000 0x4000>;
919 clocks = <&clks IMX6SX_CLK_OCOTP>;
923 compatible = "fsl,imx6sx-sai";
924 reg = <0x021d4000 0x4000>;
925 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
927 <&clks IMX6SX_CLK_SAI1>,
928 <&clks 0>, <&clks 0>;
929 clock-names = "bus", "mclk1", "mclk2", "mclk3";
930 dma-names = "rx", "tx";
931 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
932 dma-source = <&gpr 0 15 0 16>;
936 audmux: audmux@021d8000 {
937 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
938 reg = <0x021d8000 0x4000>;
943 compatible = "fsl,imx6sx-sai";
944 reg = <0x021dc000 0x4000>;
945 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
947 <&clks IMX6SX_CLK_SAI2>,
948 <&clks 0>, <&clks 0>;
949 clock-names = "bus", "mclk1", "mclk2", "mclk3";
950 dma-names = "rx", "tx";
951 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
952 dma-source = <&gpr 0 17 0 18>;
956 qspi1: qspi@021e0000 {
957 #address-cells = <1>;
959 compatible = "fsl,imx6sx-qspi";
960 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
961 reg-names = "QuadSPI", "QuadSPI-memory";
962 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clks IMX6SX_CLK_QSPI1>,
964 <&clks IMX6SX_CLK_QSPI1>;
965 clock-names = "qspi_en", "qspi";
969 qspi2: qspi@021e4000 {
970 #address-cells = <1>;
972 compatible = "fsl,imx6sx-qspi";
973 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
974 reg-names = "QuadSPI", "QuadSPI-memory";
975 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&clks IMX6SX_CLK_QSPI2>,
977 <&clks IMX6SX_CLK_QSPI2>;
978 clock-names = "qspi_en", "qspi";
982 uart2: serial@021e8000 {
983 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
984 reg = <0x021e8000 0x4000>;
985 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clks IMX6SX_CLK_UART_IPG>,
987 <&clks IMX6SX_CLK_UART_SERIAL>;
988 clock-names = "ipg", "per";
989 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
990 dma-names = "rx", "tx";
994 uart3: serial@021ec000 {
995 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
996 reg = <0x021ec000 0x4000>;
997 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&clks IMX6SX_CLK_UART_IPG>,
999 <&clks IMX6SX_CLK_UART_SERIAL>;
1000 clock-names = "ipg", "per";
1001 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1002 dma-names = "rx", "tx";
1003 status = "disabled";
1006 uart4: serial@021f0000 {
1007 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1008 reg = <0x021f0000 0x4000>;
1009 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1011 <&clks IMX6SX_CLK_UART_SERIAL>;
1012 clock-names = "ipg", "per";
1013 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1014 dma-names = "rx", "tx";
1015 status = "disabled";
1018 uart5: serial@021f4000 {
1019 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1020 reg = <0x021f4000 0x4000>;
1021 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1023 <&clks IMX6SX_CLK_UART_SERIAL>;
1024 clock-names = "ipg", "per";
1025 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1026 dma-names = "rx", "tx";
1027 status = "disabled";
1030 i2c4: i2c@021f8000 {
1031 #address-cells = <1>;
1033 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1034 reg = <0x021f8000 0x4000>;
1035 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6SX_CLK_I2C4>;
1037 status = "disabled";
1041 aips3: aips-bus@02200000 {
1042 compatible = "fsl,aips-bus", "simple-bus";
1043 #address-cells = <1>;
1045 reg = <0x02200000 0x100000>;
1049 compatible = "fsl,spba-bus", "simple-bus";
1050 #address-cells = <1>;
1052 reg = <0x02240000 0x40000>;
1055 dcic1: dcic@0220c000 {
1056 compatible = "fsl,imx6sx-dcic";
1057 reg = <0x0220c000 0x4000>;
1058 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&clks IMX6SX_CLK_DCIC1>,
1060 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1061 clock-names = "dcic", "disp-axi";
1063 status = "disabled";
1066 dcic2: dcic@02210000 {
1067 compatible = "fsl,imx6sx-dcic";
1068 reg = <0x02210000 0x4000>;
1069 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6SX_CLK_DCIC2>,
1071 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1072 clock-names = "dcic", "disp-axi";
1074 status = "disabled";
1077 csi1: csi@02214000 {
1078 reg = <0x02214000 0x4000>;
1079 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1081 <&clks IMX6SX_CLK_CSI>,
1082 <&clks IMX6SX_CLK_DCIC1>;
1083 clock-names = "disp-axi", "csi_mclk", "dcic";
1084 status = "disabled";
1088 compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1089 reg = <0x02218000 0x4000>;
1090 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1092 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1093 clock-names = "pxp-axi", "disp-axi";
1094 status = "disabled";
1097 csi2: csi@0221c000 {
1098 reg = <0x0221c000 0x4000>;
1099 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1101 <&clks IMX6SX_CLK_CSI>,
1102 <&clks IMX6SX_CLK_DCIC2>;
1103 clock-names = "disp-axi", "csi_mclk", "dcic";
1104 status = "disabled";
1107 lcdif1: lcdif@02220000 {
1108 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1109 reg = <0x02220000 0x4000>;
1110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1112 <&clks IMX6SX_CLK_LCDIF_APB>,
1113 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1114 clock-names = "pix", "axi", "disp_axi";
1115 status = "disabled";
1118 lcdif2: lcdif@02224000 {
1119 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1120 reg = <0x02224000 0x4000>;
1121 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1123 <&clks IMX6SX_CLK_LCDIF_APB>,
1124 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1125 clock-names = "pix", "axi", "disp_axi";
1126 status = "disabled";
1129 vadc: vadc@02228000 {
1130 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1131 reg-names = "vadc-vafe", "vadc-vdec";
1132 clocks = <&clks IMX6SX_CLK_VADC>,
1133 <&clks IMX6SX_CLK_CSI>;
1134 clock-names = "vadc", "csi";
1135 status = "disabled";
1139 adc1: adc@02280000 {
1140 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1141 reg = <0x02280000 0x4000>;
1142 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&clks IMX6SX_CLK_IPG>;
1144 clock-names = "adc";
1145 status = "disabled";
1148 adc2: adc@02284000 {
1149 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1150 reg = <0x02284000 0x4000>;
1151 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&clks IMX6SX_CLK_IPG>;
1153 clock-names = "adc";
1154 status = "disabled";
1157 wdog3: wdog@02288000 {
1158 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1159 reg = <0x02288000 0x4000>;
1160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&clks IMX6SX_CLK_DUMMY>;
1162 status = "disabled";
1165 ecspi5: ecspi@0228c000 {
1166 #address-cells = <1>;
1168 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1169 reg = <0x0228c000 0x4000>;
1170 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1172 <&clks IMX6SX_CLK_ECSPI5>;
1173 clock-names = "ipg", "per";
1174 status = "disabled";
1177 uart6: serial@022a0000 {
1178 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1179 reg = <0x022a0000 0x4000>;
1180 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1182 <&clks IMX6SX_CLK_UART_SERIAL>;
1183 clock-names = "ipg", "per";
1184 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1185 dma-names = "rx", "tx";
1186 status = "disabled";
1189 pwm5: pwm@022a4000 {
1190 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1191 reg = <0x022a4000 0x4000>;
1192 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_PWM5>,
1194 <&clks IMX6SX_CLK_PWM5>;
1195 clock-names = "ipg", "per";
1199 pwm6: pwm@022a8000 {
1200 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1201 reg = <0x022a8000 0x4000>;
1202 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6SX_CLK_PWM6>,
1204 <&clks IMX6SX_CLK_PWM6>;
1205 clock-names = "ipg", "per";
1209 pwm7: pwm@022ac000 {
1210 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1211 reg = <0x022ac000 0x4000>;
1212 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX6SX_CLK_PWM7>,
1214 <&clks IMX6SX_CLK_PWM7>;
1215 clock-names = "ipg", "per";
1219 pwm8: pwm@0022b0000 {
1220 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1221 reg = <0x0022b0000 0x4000>;
1222 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clks IMX6SX_CLK_PWM8>,
1224 <&clks IMX6SX_CLK_PWM8>;
1225 clock-names = "ipg", "per";
1230 pcie: pcie@0x08000000 {
1231 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1232 reg = <0x08ffc000 0x4000>; /* DBI */
1233 #address-cells = <3>;
1235 device_type = "pci";
1236 /* configuration space */
1237 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1238 /* downstream I/O */
1239 0x81000000 0 0 0x08f80000 0 0x00010000
1240 /* non-prefetchable memory */
1241 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1243 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1245 <&clks IMX6SX_CLK_PCIE_AXI>,
1246 <&clks IMX6SX_CLK_LVDS1_OUT>,
1247 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1248 clock-names = "pcie_ref_125m", "pcie_axi",
1249 "lvds_gate", "display_axi";
1250 status = "disabled";