2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sx-pinfunc.h"
13 #include "skeleton.dtsi"
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
66 fsl,soc-operating-points = <
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <®_arm>;
81 soc-supply = <®_soc>;
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
89 reg = <0x00a01000 0x1000>,
98 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
114 compatible = "fixed-clock";
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
122 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
138 compatible = "fsl,imx6_busfreq";
139 clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
140 <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
141 <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
142 <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
143 <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
144 <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
145 <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
146 <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
147 <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
148 <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>,
149 <&clks IMX6SX_CLK_M4>;
150 clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
151 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
152 "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", "m4";
153 fsl,max_ddr_freq = <400000000>;
157 compatible = "arm,cortex-a9-pmu";
158 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
161 ocrams: sram@008f8000 {
162 compatible = "fsl,lpm-sram";
163 reg = <0x008f8000 0x4000>;
164 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
167 ocrams_ddr: sram@00900000 {
168 compatible = "fsl,ddr-lpm-sram";
169 reg = <0x00900000 0x1000>;
170 clocks = <&clks IMX6SX_CLK_OCRAM>;
173 ocram: sram@00901000 {
174 compatible = "mmio-sram";
175 reg = <0x00901000 0x1F000>;
176 clocks = <&clks IMX6SX_CLK_OCRAM>;
179 ocram_mf: sram-mf@00900000 {
180 compatible = "fsl,mega-fast-sram";
181 reg = <0x00900000 0x20000>;
182 clocks = <&clks IMX6SX_CLK_OCRAM>;
185 L2: l2-cache@00a02000 {
186 compatible = "arm,pl310-cache";
187 reg = <0x00a02000 0x1000>;
188 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
191 arm,tag-latency = <4 2 3>;
192 arm,data-latency = <4 2 3>;
196 compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
197 reg = <0x01800000 0x4000>, <0x80000000 0x0>;
198 reg-names = "iobase_3d", "phys_baseaddr";
199 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
200 interrupt-names = "irq_3d";
201 clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
203 clock-names = "gpu3d_axi_clk", "gpu3d_clk",
206 reset-names = "gpu3d";
207 power-domains = <&gpc 1>;
210 dma_apbh: dma-apbh@01804000 {
211 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
212 reg = <0x01804000 0x2000>;
213 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
220 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
223 gpmi: gpmi-nand@01806000{
224 compatible = "fsl,imx6sx-gpmi-nand";
225 #address-cells = <1>;
227 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
228 reg-names = "gpmi-nand", "bch";
229 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "bch";
231 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
232 <&clks IMX6SX_CLK_GPMI_APB>,
233 <&clks IMX6SX_CLK_GPMI_BCH>,
234 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
235 <&clks IMX6SX_CLK_PER1_BCH>;
236 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
237 "gpmi_bch_apb", "per1_bch";
238 dmas = <&dma_apbh 0>;
243 aips1: aips-bus@02000000 {
244 compatible = "fsl,aips-bus", "simple-bus";
245 #address-cells = <1>;
247 reg = <0x02000000 0x100000>;
251 compatible = "fsl,spba-bus", "simple-bus";
252 #address-cells = <1>;
254 reg = <0x02000000 0x40000>;
257 spdif: spdif@02004000 {
258 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
259 reg = <0x02004000 0x4000>;
260 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
261 dmas = <&sdma 14 18 0>,
263 dma-names = "rx", "tx";
264 clocks = <&clks IMX6SX_CLK_SPDIF>,
265 <&clks IMX6SX_CLK_OSC>,
266 <&clks IMX6SX_CLK_SPDIF>,
267 <&clks 0>, <&clks 0>, <&clks 0>,
268 <&clks IMX6SX_CLK_IPG>,
269 <&clks 0>, <&clks 0>,
270 <&clks IMX6SX_CLK_SPBA>;
271 clock-names = "core", "rxtx0",
279 ecspi1: ecspi@02008000 {
280 #address-cells = <1>;
282 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
283 reg = <0x02008000 0x4000>;
284 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6SX_CLK_ECSPI1>,
286 <&clks IMX6SX_CLK_ECSPI1>;
287 clock-names = "ipg", "per";
291 ecspi2: ecspi@0200c000 {
292 #address-cells = <1>;
294 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
295 reg = <0x0200c000 0x4000>;
296 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clks IMX6SX_CLK_ECSPI2>,
298 <&clks IMX6SX_CLK_ECSPI2>;
299 clock-names = "ipg", "per";
303 ecspi3: ecspi@02010000 {
304 #address-cells = <1>;
306 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
307 reg = <0x02010000 0x4000>;
308 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clks IMX6SX_CLK_ECSPI3>,
310 <&clks IMX6SX_CLK_ECSPI3>;
311 clock-names = "ipg", "per";
315 ecspi4: ecspi@02014000 {
316 #address-cells = <1>;
318 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
319 reg = <0x02014000 0x4000>;
320 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clks IMX6SX_CLK_ECSPI4>,
322 <&clks IMX6SX_CLK_ECSPI4>;
323 clock-names = "ipg", "per";
327 uart1: serial@02020000 {
328 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
329 reg = <0x02020000 0x4000>;
330 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6SX_CLK_UART_IPG>,
332 <&clks IMX6SX_CLK_UART_SERIAL>;
333 clock-names = "ipg", "per";
334 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
335 dma-names = "rx", "tx";
339 esai: esai@02024000 {
340 compatible = "fsl,imx35-esai";
341 reg = <0x02024000 0x4000>;
342 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
344 <&clks IMX6SX_CLK_ESAI_MEM>,
345 <&clks IMX6SX_CLK_ESAI_EXTAL>,
346 <&clks IMX6SX_CLK_ESAI_IPG>,
347 <&clks IMX6SX_CLK_SPBA>;
348 clock-names = "core", "mem", "extal",
350 dmas = <&sdma 23 21 0>,
352 dma-names = "rx", "tx";
357 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
358 reg = <0x02028000 0x4000>;
359 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
361 <&clks IMX6SX_CLK_SSI1>;
362 clock-names = "ipg", "baud";
363 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
364 dma-names = "rx", "tx";
369 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
370 reg = <0x0202c000 0x4000>;
371 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
373 <&clks IMX6SX_CLK_SSI2>;
374 clock-names = "ipg", "baud";
375 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
376 dma-names = "rx", "tx";
381 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
382 reg = <0x02030000 0x4000>;
383 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
385 <&clks IMX6SX_CLK_SSI3>;
386 clock-names = "ipg", "baud";
387 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
388 dma-names = "rx", "tx";
392 asrc: asrc@02034000 {
393 compatible = "fsl,imx53-asrc";
394 reg = <0x02034000 0x4000>;
395 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
397 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
399 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
400 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
401 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
402 <&clks IMX6SX_CLK_SPBA>;
403 clock-names = "mem", "ipg", "asrck_0",
404 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
405 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
406 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
407 "asrck_d", "asrck_e", "asrck_f", "dma";
408 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
409 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
410 dma-names = "rxa", "rxb", "rxc",
412 fsl,asrc-rate = <48000>;
413 fsl,asrc-width = <16>;
418 compatible = "fsl,imx6q-asrc-p2p";
419 fsl,p2p-rate = <48000>;
420 fsl,p2p-width = <16>;
421 fsl,asrc-dma-rx-events = <17 18 19>;
422 fsl,asrc-dma-tx-events = <20 21 22>;
428 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
429 reg = <0x02080000 0x4000>;
430 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks IMX6SX_CLK_PWM1>,
432 <&clks IMX6SX_CLK_PWM1>;
433 clock-names = "ipg", "per";
438 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
439 reg = <0x02084000 0x4000>;
440 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX6SX_CLK_PWM2>,
442 <&clks IMX6SX_CLK_PWM2>;
443 clock-names = "ipg", "per";
448 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
449 reg = <0x02088000 0x4000>;
450 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX6SX_CLK_PWM3>,
452 <&clks IMX6SX_CLK_PWM3>;
453 clock-names = "ipg", "per";
458 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
459 reg = <0x0208c000 0x4000>;
460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6SX_CLK_PWM4>,
462 <&clks IMX6SX_CLK_PWM4>;
463 clock-names = "ipg", "per";
467 flexcan1: can@02090000 {
468 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
469 reg = <0x02090000 0x4000>;
470 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
472 <&clks IMX6SX_CLK_CAN1_SERIAL>;
473 clock-names = "ipg", "per";
474 stop-mode = <&gpr 0x10 1 0x10 17>;
478 flexcan2: can@02094000 {
479 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
480 reg = <0x02094000 0x4000>;
481 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
483 <&clks IMX6SX_CLK_CAN2_SERIAL>;
484 clock-names = "ipg", "per";
485 stop-mode = <&gpr 0x10 2 0x10 18>;
490 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
491 reg = <0x02098000 0x4000>;
492 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
494 <&clks IMX6SX_CLK_GPT_SERIAL>;
495 clock-names = "ipg", "per";
498 gpio1: gpio@0209c000 {
499 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
500 reg = <0x0209c000 0x4000>;
501 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
509 gpio2: gpio@020a0000 {
510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
511 reg = <0x020a0000 0x4000>;
512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
520 gpio3: gpio@020a4000 {
521 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
522 reg = <0x020a4000 0x4000>;
523 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gpio4: gpio@020a8000 {
532 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
533 reg = <0x020a8000 0x4000>;
534 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
542 gpio5: gpio@020ac000 {
543 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
544 reg = <0x020ac000 0x4000>;
545 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
553 gpio6: gpio@020b0000 {
554 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
555 reg = <0x020b0000 0x4000>;
556 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
564 gpio7: gpio@020b4000 {
565 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
566 reg = <0x020b4000 0x4000>;
567 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
576 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
577 reg = <0x020b8000 0x4000>;
578 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clks IMX6SX_CLK_DUMMY>;
583 wdog1: wdog@020bc000 {
584 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
585 reg = <0x020bc000 0x4000>;
586 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clks IMX6SX_CLK_DUMMY>;
590 wdog2: wdog@020c0000 {
591 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
592 reg = <0x020c0000 0x4000>;
593 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clks IMX6SX_CLK_DUMMY>;
599 compatible = "fsl,imx6sx-ccm";
600 reg = <0x020c4000 0x4000>;
601 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
605 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
608 anatop: anatop@020c8000 {
609 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
610 "syscon", "simple-bus";
611 reg = <0x020c8000 0x1000>;
612 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
617 compatible = "fsl,anatop-regulator";
618 regulator-name = "vdd1p1";
619 regulator-min-microvolt = <800000>;
620 regulator-max-microvolt = <1375000>;
622 anatop-reg-offset = <0x110>;
623 anatop-vol-bit-shift = <8>;
624 anatop-vol-bit-width = <5>;
625 anatop-min-bit-val = <4>;
626 anatop-min-voltage = <800000>;
627 anatop-max-voltage = <1375000>;
631 compatible = "fsl,anatop-regulator";
632 regulator-name = "vdd3p0";
633 regulator-min-microvolt = <2800000>;
634 regulator-max-microvolt = <3150000>;
636 anatop-reg-offset = <0x120>;
637 anatop-vol-bit-shift = <8>;
638 anatop-vol-bit-width = <5>;
639 anatop-min-bit-val = <0>;
640 anatop-min-voltage = <2625000>;
641 anatop-max-voltage = <3400000>;
645 compatible = "fsl,anatop-regulator";
646 regulator-name = "vdd2p5";
647 regulator-min-microvolt = <2100000>;
648 regulator-max-microvolt = <2875000>;
650 anatop-reg-offset = <0x130>;
651 anatop-vol-bit-shift = <8>;
652 anatop-vol-bit-width = <5>;
653 anatop-min-bit-val = <0>;
654 anatop-min-voltage = <2100000>;
655 anatop-max-voltage = <2875000>;
658 reg_arm: regulator-vddcore@140 {
659 compatible = "fsl,anatop-regulator";
660 regulator-name = "cpu";
661 regulator-min-microvolt = <725000>;
662 regulator-max-microvolt = <1450000>;
664 anatop-reg-offset = <0x140>;
665 anatop-vol-bit-shift = <0>;
666 anatop-vol-bit-width = <5>;
667 anatop-delay-reg-offset = <0x170>;
668 anatop-delay-bit-shift = <24>;
669 anatop-delay-bit-width = <2>;
670 anatop-min-bit-val = <1>;
671 anatop-min-voltage = <725000>;
672 anatop-max-voltage = <1450000>;
675 reg_pcie: regulator-vddpcie@140 {
676 compatible = "fsl,anatop-regulator";
677 regulator-name = "vddpcie";
678 regulator-min-microvolt = <725000>;
679 regulator-max-microvolt = <1450000>;
680 anatop-reg-offset = <0x140>;
681 anatop-vol-bit-shift = <9>;
682 anatop-vol-bit-width = <5>;
683 anatop-delay-reg-offset = <0x170>;
684 anatop-delay-bit-shift = <26>;
685 anatop-delay-bit-width = <2>;
686 anatop-min-bit-val = <1>;
687 anatop-min-voltage = <725000>;
688 anatop-max-voltage = <1450000>;
691 reg_soc: regulator-vddsoc@140 {
692 compatible = "fsl,anatop-regulator";
693 regulator-name = "vddsoc";
694 regulator-min-microvolt = <725000>;
695 regulator-max-microvolt = <1450000>;
697 anatop-reg-offset = <0x140>;
698 anatop-vol-bit-shift = <18>;
699 anatop-vol-bit-width = <5>;
700 anatop-delay-reg-offset = <0x170>;
701 anatop-delay-bit-shift = <28>;
702 anatop-delay-bit-width = <2>;
703 anatop-min-bit-val = <1>;
704 anatop-min-voltage = <725000>;
705 anatop-max-voltage = <1450000>;
710 compatible = "fsl,imx6sx-tempmon";
711 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
712 fsl,tempmon = <&anatop>;
713 fsl,tempmon-data = <&ocotp>;
714 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
717 usbphy1: usbphy@020c9000 {
718 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
719 reg = <0x020c9000 0x1000>;
720 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clks IMX6SX_CLK_USBPHY1>;
722 fsl,anatop = <&anatop>;
725 usbphy2: usbphy@020ca000 {
726 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
727 reg = <0x020ca000 0x1000>;
728 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clks IMX6SX_CLK_USBPHY2>;
730 fsl,anatop = <&anatop>;
734 compatible = "fsl,imx6sx-mqs";
739 snvs: snvs@020cc000 {
740 compatible = "fsl,sec-v4.0-mon", "simple-bus";
741 #address-cells = <1>;
743 ranges = <0 0x020cc000 0x4000>;
746 compatible = "fsl,sec-v4.0-mon-rtc-lp";
748 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
752 snvs-pwrkey@0x020cc000 {
753 compatible = "fsl,imx6sx-snvs-pwrkey";
754 reg = <0x020cc000 0x4000>;
755 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
756 fsl,keycode = <116>; /* KEY_POWER */
760 epit1: epit@020d0000 {
761 reg = <0x020d0000 0x4000>;
762 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
765 epit2: epit@020d4000 {
766 reg = <0x020d4000 0x4000>;
767 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
771 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
772 reg = <0x020d8000 0x4000>;
773 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
779 compatible = "fsl,imx6sx-gpc",
780 "fsl,imx6q-gpc", "syscon";
781 reg = <0x020dc000 0x4000>;
782 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
783 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400200>;
784 clocks = <&clks IMX6SX_CLK_GPU>;
785 #power-domain-cells = <1>;
788 iomuxc: iomuxc@020e0000 {
789 compatible = "fsl,imx6sx-iomuxc";
790 reg = <0x020e0000 0x4000>;
793 gpr: iomuxc-gpr@020e4000 {
794 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
795 reg = <0x020e4000 0x4000>;
798 canfd1: canfd@020e8000 {
799 compatible = "bosch,m_can";
800 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
801 reg-names = "canfd", "message_ram";
802 interrupts = <0 114 0x04>;
803 clocks = <&clks IMX6SX_CLK_CANFD>;
804 mram-cfg = <0x0 0 0 32 0 0 0 1>;
808 canfd2: canfd@020f0000 {
809 compatible = "bosch,m_can";
810 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
811 reg-names = "canfd", "message_ram";
812 interrupts = <0 115 0x04>;
813 clocks = <&clks IMX6SX_CLK_CANFD>;
814 mram-cfg = <0x400 0 0 32 0 0 0 1>;
819 #address-cells = <1>;
821 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
825 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
826 <&clks IMX6SX_CLK_LCDIF1_SEL>,
827 <&clks IMX6SX_CLK_LCDIF2_SEL>,
828 <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
829 <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
830 <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
831 clock-names = "ldb_di0",
844 sdma: sdma@020ec000 {
845 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
846 reg = <0x020ec000 0x4000>;
847 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clks IMX6SX_CLK_SDMA>,
849 <&clks IMX6SX_CLK_SDMA>;
850 clock-names = "ipg", "ahb";
852 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
856 aips2: aips-bus@02100000 {
857 compatible = "fsl,aips-bus", "simple-bus";
858 #address-cells = <1>;
860 reg = <0x02100000 0x100000>;
863 usbotg1: usb@02184000 {
864 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
865 reg = <0x02184000 0x200>;
866 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clks IMX6SX_CLK_USBOH3>;
868 fsl,usbphy = <&usbphy1>;
869 fsl,usbmisc = <&usbmisc 0>;
870 fsl,anatop = <&anatop>;
874 usbotg2: usb@02184200 {
875 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
876 reg = <0x02184200 0x200>;
877 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&clks IMX6SX_CLK_USBOH3>;
879 fsl,usbphy = <&usbphy2>;
880 fsl,usbmisc = <&usbmisc 1>;
885 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
886 reg = <0x02184400 0x200>;
887 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks IMX6SX_CLK_USBOH3>;
889 fsl,usbmisc = <&usbmisc 2>;
891 fsl,anatop = <&anatop>;
895 usbmisc: usbmisc@02184800 {
897 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
898 reg = <0x02184800 0x200>;
899 clocks = <&clks IMX6SX_CLK_USBOH3>;
902 fec1: ethernet@02188000 {
903 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
904 reg = <0x02188000 0x4000>;
905 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6SX_CLK_ENET>,
908 <&clks IMX6SX_CLK_ENET_AHB>,
909 <&clks IMX6SX_CLK_ENET_PTP>,
910 <&clks IMX6SX_CLK_ENET_REF>,
911 <&clks IMX6SX_CLK_ENET_PTP>;
912 clock-names = "ipg", "ahb", "ptp",
913 "enet_clk_ref", "enet_out";
914 fsl,num-tx-queues=<3>;
915 fsl,num-rx-queues=<3>;
920 reg = <0x0218c000 0x4000>;
921 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clks IMX6SX_CLK_MLB>;
928 usdhc1: usdhc@02190000 {
929 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
930 reg = <0x02190000 0x4000>;
931 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clks IMX6SX_CLK_USDHC1>,
933 <&clks IMX6SX_CLK_USDHC1>,
934 <&clks IMX6SX_CLK_USDHC1>;
935 clock-names = "ipg", "ahb", "per";
940 usdhc2: usdhc@02194000 {
941 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
942 reg = <0x02194000 0x4000>;
943 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX6SX_CLK_USDHC2>,
945 <&clks IMX6SX_CLK_USDHC2>,
946 <&clks IMX6SX_CLK_USDHC2>;
947 clock-names = "ipg", "ahb", "per";
952 usdhc3: usdhc@02198000 {
953 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
954 reg = <0x02198000 0x4000>;
955 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6SX_CLK_USDHC3>,
957 <&clks IMX6SX_CLK_USDHC3>,
958 <&clks IMX6SX_CLK_USDHC3>;
959 clock-names = "ipg", "ahb", "per";
964 usdhc4: usdhc@0219c000 {
965 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
966 reg = <0x0219c000 0x4000>;
967 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&clks IMX6SX_CLK_USDHC4>,
969 <&clks IMX6SX_CLK_USDHC4>,
970 <&clks IMX6SX_CLK_USDHC4>;
971 clock-names = "ipg", "ahb", "per";
977 #address-cells = <1>;
979 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
980 reg = <0x021a0000 0x4000>;
981 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&clks IMX6SX_CLK_I2C1>;
987 #address-cells = <1>;
989 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
990 reg = <0x021a4000 0x4000>;
991 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6SX_CLK_I2C2>;
997 #address-cells = <1>;
999 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1000 reg = <0x021a8000 0x4000>;
1001 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX6SX_CLK_I2C3>;
1003 status = "disabled";
1006 mmdc: mmdc@021b0000 {
1007 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1008 reg = <0x021b0000 0x4000>;
1011 fec2: ethernet@021b4000 {
1012 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1013 reg = <0x021b4000 0x4000>;
1014 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6SX_CLK_ENET>,
1017 <&clks IMX6SX_CLK_ENET_AHB>,
1018 <&clks IMX6SX_CLK_ENET_PTP>,
1019 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1020 <&clks IMX6SX_CLK_ENET_PTP>;
1021 clock-names = "ipg", "ahb", "ptp",
1022 "enet_clk_ref", "enet_out";
1023 status = "disabled";
1026 weim: weim@021b8000 {
1027 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1028 reg = <0x021b8000 0x4000>;
1029 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1033 ocotp: ocotp-ctrl@021bc000 {
1034 compatible = "syscon";
1035 reg = <0x021bc000 0x4000>;
1036 clocks = <&clks IMX6SX_CLK_OCOTP>;
1039 ocotp-fuse@021bc000 {
1040 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
1041 reg = <0x021bc000 0x4000>;
1042 clocks = <&clks IMX6SX_CLK_OCOTP>;
1046 compatible = "fsl,imx6sx-romcp", "syscon";
1047 reg = <0x021ac000 0x4000>;
1050 sai1: sai@021d4000 {
1051 compatible = "fsl,imx6sx-sai";
1052 reg = <0x021d4000 0x4000>;
1053 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1055 <&clks IMX6SX_CLK_SAI1>,
1056 <&clks 0>, <&clks 0>;
1057 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1058 dma-names = "rx", "tx";
1059 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
1060 dma-source = <&gpr 0 15 0 16>;
1061 status = "disabled";
1064 audmux: audmux@021d8000 {
1065 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1066 reg = <0x021d8000 0x4000>;
1067 status = "disabled";
1070 sai2: sai@021dc000 {
1071 compatible = "fsl,imx6sx-sai";
1072 reg = <0x021dc000 0x4000>;
1073 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1075 <&clks IMX6SX_CLK_SAI2>,
1076 <&clks 0>, <&clks 0>;
1077 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1078 dma-names = "rx", "tx";
1079 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1080 dma-source = <&gpr 0 17 0 18>;
1081 status = "disabled";
1084 qspi1: qspi@021e0000 {
1085 #address-cells = <1>;
1087 compatible = "fsl,imx6sx-qspi";
1088 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1089 reg-names = "QuadSPI", "QuadSPI-memory";
1090 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clks IMX6SX_CLK_QSPI1>,
1092 <&clks IMX6SX_CLK_QSPI1>;
1093 clock-names = "qspi_en", "qspi";
1094 status = "disabled";
1097 qspi2: qspi@021e4000 {
1098 #address-cells = <1>;
1100 compatible = "fsl,imx6sx-qspi";
1101 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1102 reg-names = "QuadSPI", "QuadSPI-memory";
1103 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&clks IMX6SX_CLK_QSPI2>,
1105 <&clks IMX6SX_CLK_QSPI2>;
1106 clock-names = "qspi_en", "qspi";
1107 status = "disabled";
1111 compatible = "fsl,imx6sx-qspi-m4-restore";
1112 reg = <0x021e4000 0x4000>;
1113 status = "disabled";
1116 uart2: serial@021e8000 {
1117 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1118 reg = <0x021e8000 0x4000>;
1119 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1121 <&clks IMX6SX_CLK_UART_SERIAL>;
1122 clock-names = "ipg", "per";
1123 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1124 dma-names = "rx", "tx";
1125 status = "disabled";
1128 uart3: serial@021ec000 {
1129 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1130 reg = <0x021ec000 0x4000>;
1131 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1133 <&clks IMX6SX_CLK_UART_SERIAL>;
1134 clock-names = "ipg", "per";
1135 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1136 dma-names = "rx", "tx";
1137 status = "disabled";
1140 uart4: serial@021f0000 {
1141 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1142 reg = <0x021f0000 0x4000>;
1143 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1145 <&clks IMX6SX_CLK_UART_SERIAL>;
1146 clock-names = "ipg", "per";
1147 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1148 dma-names = "rx", "tx";
1149 status = "disabled";
1152 uart5: serial@021f4000 {
1153 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1154 reg = <0x021f4000 0x4000>;
1155 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1157 <&clks IMX6SX_CLK_UART_SERIAL>;
1158 clock-names = "ipg", "per";
1159 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1160 dma-names = "rx", "tx";
1161 status = "disabled";
1164 i2c4: i2c@021f8000 {
1165 #address-cells = <1>;
1167 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1168 reg = <0x021f8000 0x4000>;
1169 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&clks IMX6SX_CLK_I2C4>;
1171 status = "disabled";
1175 aips3: aips-bus@02200000 {
1176 compatible = "fsl,aips-bus", "simple-bus";
1177 #address-cells = <1>;
1179 reg = <0x02200000 0x100000>;
1183 compatible = "fsl,spba-bus", "simple-bus";
1184 #address-cells = <1>;
1186 reg = <0x02240000 0x40000>;
1189 dcic1: dcic@0220c000 {
1190 compatible = "fsl,imx6sx-dcic";
1191 reg = <0x0220c000 0x4000>;
1192 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_DCIC1>,
1194 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1195 clock-names = "dcic", "disp-axi";
1197 status = "disabled";
1200 dcic2: dcic@02210000 {
1201 compatible = "fsl,imx6sx-dcic";
1202 reg = <0x02210000 0x4000>;
1203 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&clks IMX6SX_CLK_DCIC2>,
1205 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1206 clock-names = "dcic", "disp-axi";
1208 status = "disabled";
1211 csi1: csi@02214000 {
1212 compatible = "fsl,imx6s-csi";
1213 reg = <0x02214000 0x4000>;
1214 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1216 <&clks IMX6SX_CLK_CSI>,
1217 <&clks IMX6SX_CLK_DCIC1>;
1218 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1219 status = "disabled";
1223 compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1224 reg = <0x02218000 0x4000>;
1225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1227 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1228 clock-names = "pxp-axi", "disp-axi";
1229 status = "disabled";
1232 csi2: csi@0221c000 {
1233 compatible = "fsl,imx6s-csi";
1234 reg = <0x0221c000 0x4000>;
1235 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1237 <&clks IMX6SX_CLK_CSI>,
1238 <&clks IMX6SX_CLK_DCIC2>;
1239 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1240 status = "disabled";
1243 lcdif1: lcdif@02220000 {
1244 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1245 reg = <0x02220000 0x4000>;
1246 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1248 <&clks IMX6SX_CLK_LCDIF_APB>,
1249 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1250 clock-names = "pix", "axi", "disp_axi";
1251 status = "disabled";
1254 lcdif2: lcdif@02224000 {
1255 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1256 reg = <0x02224000 0x4000>;
1257 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1259 <&clks IMX6SX_CLK_LCDIF_APB>,
1260 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1261 clock-names = "pix", "axi", "disp_axi";
1262 status = "disabled";
1265 vadc: vadc@02228000 {
1266 compatible = "fsl,imx6sx-vadc";
1267 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1268 reg-names = "vadc-vafe", "vadc-vdec";
1269 clocks = <&clks IMX6SX_CLK_VADC>,
1270 <&clks IMX6SX_CLK_CSI>;
1271 clock-names = "vadc", "csi";
1273 status = "disabled";
1277 adc1: adc@02280000 {
1278 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1279 reg = <0x02280000 0x4000>;
1280 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clks IMX6SX_CLK_IPG>;
1283 clock-names = "adc";
1284 status = "disabled";
1287 adc2: adc@02284000 {
1288 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1289 reg = <0x02284000 0x4000>;
1290 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1291 clocks = <&clks IMX6SX_CLK_IPG>;
1293 clock-names = "adc";
1294 status = "disabled";
1297 wdog3: wdog@02288000 {
1298 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1299 reg = <0x02288000 0x4000>;
1300 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1301 clocks = <&clks IMX6SX_CLK_DUMMY>;
1302 status = "disabled";
1305 ecspi5: ecspi@0228c000 {
1306 #address-cells = <1>;
1308 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1309 reg = <0x0228c000 0x4000>;
1310 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1312 <&clks IMX6SX_CLK_ECSPI5>;
1313 clock-names = "ipg", "per";
1314 status = "disabled";
1317 sema4: sema4@02290000 { /* sema4 */
1318 compatible = "fsl,imx6sx-sema4";
1319 reg = <0x02290000 0x4000>;
1320 interrupts = <0 116 0x04>;
1324 mu: mu@02294000 { /* mu */
1325 compatible = "fsl,imx6sx-mu";
1326 reg = <0x02294000 0x4000>;
1327 interrupts = <0 90 0x04>;
1331 uart6: serial@022a0000 {
1332 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1333 reg = <0x022a0000 0x4000>;
1334 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1336 <&clks IMX6SX_CLK_UART_SERIAL>;
1337 clock-names = "ipg", "per";
1338 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1339 dma-names = "rx", "tx";
1340 status = "disabled";
1343 pwm5: pwm@022a4000 {
1344 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1345 reg = <0x022a4000 0x4000>;
1346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&clks IMX6SX_CLK_PWM5>,
1348 <&clks IMX6SX_CLK_PWM5>;
1349 clock-names = "ipg", "per";
1353 pwm6: pwm@022a8000 {
1354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1355 reg = <0x022a8000 0x4000>;
1356 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&clks IMX6SX_CLK_PWM6>,
1358 <&clks IMX6SX_CLK_PWM6>;
1359 clock-names = "ipg", "per";
1363 pwm7: pwm@022ac000 {
1364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1365 reg = <0x022ac000 0x4000>;
1366 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1367 clocks = <&clks IMX6SX_CLK_PWM7>,
1368 <&clks IMX6SX_CLK_PWM7>;
1369 clock-names = "ipg", "per";
1373 pwm8: pwm@0022b0000 {
1374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1375 reg = <0x0022b0000 0x4000>;
1376 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1377 clocks = <&clks IMX6SX_CLK_PWM8>,
1378 <&clks IMX6SX_CLK_PWM8>;
1379 clock-names = "ipg", "per";
1384 pcie: pcie@0x08000000 {
1385 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1386 reg = <0x08ffc000 0x4000>; /* DBI */
1387 #address-cells = <3>;
1389 device_type = "pci";
1390 /* configuration space */
1391 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1392 /* downstream I/O */
1393 0x81000000 0 0 0x08f80000 0 0x00010000
1394 /* non-prefetchable memory */
1395 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1397 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1398 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1399 <&clks IMX6SX_CLK_PCIE_AXI>,
1400 <&clks IMX6SX_CLK_LVDS1_OUT>,
1401 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1402 clock-names = "pcie_ref_125m", "pcie_axi",
1403 "lvds_gate", "display_axi";
1404 status = "disabled";