2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sx-pinfunc.h"
13 #include "skeleton.dtsi"
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
66 fsl,soc-operating-points = <
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <®_arm>;
81 soc-supply = <®_soc>;
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
89 reg = <0x00a01000 0x1000>,
98 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
114 compatible = "fixed-clock";
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
122 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
195 reg = <0x02000000 0x100000>;
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
202 reg = <0x02000000 0x40000>;
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
301 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
313 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
314 reg = <0x0202c000 0x4000>;
315 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
317 <&clks IMX6SX_CLK_SSI2>;
318 clock-names = "ipg", "baud";
319 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
320 dma-names = "rx", "tx";
325 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
326 reg = <0x02030000 0x4000>;
327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
329 <&clks IMX6SX_CLK_SSI3>;
330 clock-names = "ipg", "baud";
331 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
332 dma-names = "rx", "tx";
336 asrc: asrc@02034000 {
337 reg = <0x02034000 0x4000>;
338 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
340 <&clks IMX6SX_CLK_ASRC_IPG>,
341 <&clks IMX6SX_CLK_SPDIF>,
342 <&clks IMX6SX_CLK_SPBA>;
343 clock-names = "mem", "ipg", "asrck", "dma";
344 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
345 <&sdma 19 20 1>, <&sdma 20 20 1>,
346 <&sdma 21 20 1>, <&sdma 22 20 1>;
347 dma-names = "rxa", "rxb", "rxc",
354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
355 reg = <0x02080000 0x4000>;
356 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6SX_CLK_PWM1>,
358 <&clks IMX6SX_CLK_PWM1>;
359 clock-names = "ipg", "per";
364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
365 reg = <0x02084000 0x4000>;
366 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6SX_CLK_PWM2>,
368 <&clks IMX6SX_CLK_PWM2>;
369 clock-names = "ipg", "per";
374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
375 reg = <0x02088000 0x4000>;
376 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6SX_CLK_PWM3>,
378 <&clks IMX6SX_CLK_PWM3>;
379 clock-names = "ipg", "per";
384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
385 reg = <0x0208c000 0x4000>;
386 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6SX_CLK_PWM4>,
388 <&clks IMX6SX_CLK_PWM4>;
389 clock-names = "ipg", "per";
393 flexcan1: can@02090000 {
394 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
395 reg = <0x02090000 0x4000>;
396 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
398 <&clks IMX6SX_CLK_CAN1_SERIAL>;
399 clock-names = "ipg", "per";
400 stop-mode = <&gpr 0x10 1 0x10 17>;
404 flexcan2: can@02094000 {
405 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
406 reg = <0x02094000 0x4000>;
407 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
409 <&clks IMX6SX_CLK_CAN2_SERIAL>;
410 clock-names = "ipg", "per";
411 stop-mode = <&gpr 0x10 2 0x10 18>;
416 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
417 reg = <0x02098000 0x4000>;
418 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
420 <&clks IMX6SX_CLK_GPT_SERIAL>;
421 clock-names = "ipg", "per";
424 gpio1: gpio@0209c000 {
425 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
426 reg = <0x0209c000 0x4000>;
427 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
435 gpio2: gpio@020a0000 {
436 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
437 reg = <0x020a0000 0x4000>;
438 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
446 gpio3: gpio@020a4000 {
447 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
448 reg = <0x020a4000 0x4000>;
449 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
457 gpio4: gpio@020a8000 {
458 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
459 reg = <0x020a8000 0x4000>;
460 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
468 gpio5: gpio@020ac000 {
469 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
470 reg = <0x020ac000 0x4000>;
471 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
479 gpio6: gpio@020b0000 {
480 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
481 reg = <0x020b0000 0x4000>;
482 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
490 gpio7: gpio@020b4000 {
491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
492 reg = <0x020b4000 0x4000>;
493 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
502 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
503 reg = <0x020b8000 0x4000>;
504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX6SX_CLK_DUMMY>;
509 wdog1: wdog@020bc000 {
510 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
511 reg = <0x020bc000 0x4000>;
512 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clks IMX6SX_CLK_DUMMY>;
516 wdog2: wdog@020c0000 {
517 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
518 reg = <0x020c0000 0x4000>;
519 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&clks IMX6SX_CLK_DUMMY>;
525 compatible = "fsl,imx6sx-ccm";
526 reg = <0x020c4000 0x4000>;
527 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
531 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
534 anatop: anatop@020c8000 {
535 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
536 "syscon", "simple-bus";
537 reg = <0x020c8000 0x1000>;
538 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
543 compatible = "fsl,anatop-regulator";
544 regulator-name = "vdd1p1";
545 regulator-min-microvolt = <800000>;
546 regulator-max-microvolt = <1375000>;
548 anatop-reg-offset = <0x110>;
549 anatop-vol-bit-shift = <8>;
550 anatop-vol-bit-width = <5>;
551 anatop-min-bit-val = <4>;
552 anatop-min-voltage = <800000>;
553 anatop-max-voltage = <1375000>;
557 compatible = "fsl,anatop-regulator";
558 regulator-name = "vdd3p0";
559 regulator-min-microvolt = <2800000>;
560 regulator-max-microvolt = <3150000>;
562 anatop-reg-offset = <0x120>;
563 anatop-vol-bit-shift = <8>;
564 anatop-vol-bit-width = <5>;
565 anatop-min-bit-val = <0>;
566 anatop-min-voltage = <2625000>;
567 anatop-max-voltage = <3400000>;
571 compatible = "fsl,anatop-regulator";
572 regulator-name = "vdd2p5";
573 regulator-min-microvolt = <2100000>;
574 regulator-max-microvolt = <2875000>;
576 anatop-reg-offset = <0x130>;
577 anatop-vol-bit-shift = <8>;
578 anatop-vol-bit-width = <5>;
579 anatop-min-bit-val = <0>;
580 anatop-min-voltage = <2100000>;
581 anatop-max-voltage = <2875000>;
584 reg_arm: regulator-vddcore@140 {
585 compatible = "fsl,anatop-regulator";
586 regulator-name = "cpu";
587 regulator-min-microvolt = <725000>;
588 regulator-max-microvolt = <1450000>;
590 anatop-reg-offset = <0x140>;
591 anatop-vol-bit-shift = <0>;
592 anatop-vol-bit-width = <5>;
593 anatop-delay-reg-offset = <0x170>;
594 anatop-delay-bit-shift = <24>;
595 anatop-delay-bit-width = <2>;
596 anatop-min-bit-val = <1>;
597 anatop-min-voltage = <725000>;
598 anatop-max-voltage = <1450000>;
601 reg_pcie: regulator-vddpcie@140 {
602 compatible = "fsl,anatop-regulator";
603 regulator-name = "vddpcie";
604 regulator-min-microvolt = <725000>;
605 regulator-max-microvolt = <1450000>;
606 anatop-reg-offset = <0x140>;
607 anatop-vol-bit-shift = <9>;
608 anatop-vol-bit-width = <5>;
609 anatop-delay-reg-offset = <0x170>;
610 anatop-delay-bit-shift = <26>;
611 anatop-delay-bit-width = <2>;
612 anatop-min-bit-val = <1>;
613 anatop-min-voltage = <725000>;
614 anatop-max-voltage = <1450000>;
617 reg_soc: regulator-vddsoc@140 {
618 compatible = "fsl,anatop-regulator";
619 regulator-name = "vddsoc";
620 regulator-min-microvolt = <725000>;
621 regulator-max-microvolt = <1450000>;
623 anatop-reg-offset = <0x140>;
624 anatop-vol-bit-shift = <18>;
625 anatop-vol-bit-width = <5>;
626 anatop-delay-reg-offset = <0x170>;
627 anatop-delay-bit-shift = <28>;
628 anatop-delay-bit-width = <2>;
629 anatop-min-bit-val = <1>;
630 anatop-min-voltage = <725000>;
631 anatop-max-voltage = <1450000>;
636 compatible = "fsl,imx6sx-tempmon";
637 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
638 fsl,tempmon = <&anatop>;
639 fsl,tempmon-data = <&ocotp>;
640 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
643 usbphy1: usbphy@020c9000 {
644 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
645 reg = <0x020c9000 0x1000>;
646 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&clks IMX6SX_CLK_USBPHY1>;
648 fsl,anatop = <&anatop>;
651 usbphy2: usbphy@020ca000 {
652 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
653 reg = <0x020ca000 0x1000>;
654 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&clks IMX6SX_CLK_USBPHY2>;
656 fsl,anatop = <&anatop>;
659 snvs: snvs@020cc000 {
660 compatible = "fsl,sec-v4.0-mon", "simple-bus";
661 #address-cells = <1>;
663 ranges = <0 0x020cc000 0x4000>;
666 compatible = "fsl,sec-v4.0-mon-rtc-lp";
668 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
672 epit1: epit@020d0000 {
673 reg = <0x020d0000 0x4000>;
674 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
677 epit2: epit@020d4000 {
678 reg = <0x020d4000 0x4000>;
679 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
683 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
684 reg = <0x020d8000 0x4000>;
685 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
691 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
692 reg = <0x020dc000 0x4000>;
693 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
696 iomuxc: iomuxc@020e0000 {
697 compatible = "fsl,imx6sx-iomuxc";
698 reg = <0x020e0000 0x4000>;
701 gpr: iomuxc-gpr@020e4000 {
702 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
703 reg = <0x020e4000 0x4000>;
706 canfd1: canfd@020e8000 {
707 compatible = "bosch,m_can";
708 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
709 reg-names = "canfd", "message_ram";
710 interrupts = <0 114 0x04>;
711 clocks = <&clks IMX6SX_CLK_CANFD>;
712 mram-cfg = <0x0 0 0 32 0 0 0 1>;
716 canfd2: canfd@020f0000 {
717 compatible = "bosch,m_can";
718 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
719 reg-names = "canfd", "message_ram";
720 interrupts = <0 115 0x04>;
721 clocks = <&clks IMX6SX_CLK_CANFD>;
722 mram-cfg = <0x400 0 0 32 0 0 0 1>;
727 #address-cells = <1>;
729 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
733 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
734 <&clks IMX6SX_CLK_LCDIF1_SEL>,
735 <&clks IMX6SX_CLK_LCDIF2_SEL>,
736 <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
737 <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
738 <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
739 clock-names = "ldb_di0",
752 sdma: sdma@020ec000 {
753 compatible = "fsl,imx6sx-sdma";
754 reg = <0x020ec000 0x4000>;
755 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX6SX_CLK_SDMA>,
757 <&clks IMX6SX_CLK_SDMA>;
758 clock-names = "ipg", "ahb";
763 aips2: aips-bus@02100000 {
764 compatible = "fsl,aips-bus", "simple-bus";
765 #address-cells = <1>;
767 reg = <0x02100000 0x100000>;
770 usbotg1: usb@02184000 {
771 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
772 reg = <0x02184000 0x200>;
773 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX6SX_CLK_USBOH3>;
775 fsl,usbphy = <&usbphy1>;
776 fsl,usbmisc = <&usbmisc 0>;
777 fsl,anatop = <&anatop>;
781 usbotg2: usb@02184200 {
782 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
783 reg = <0x02184200 0x200>;
784 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clks IMX6SX_CLK_USBOH3>;
786 fsl,usbphy = <&usbphy2>;
787 fsl,usbmisc = <&usbmisc 1>;
792 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
793 reg = <0x02184400 0x200>;
794 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX6SX_CLK_USBOH3>;
796 fsl,usbmisc = <&usbmisc 2>;
798 fsl,anatop = <&anatop>;
802 usbmisc: usbmisc@02184800 {
804 compatible = "fsl,imx6sx-usbmisc";
805 reg = <0x02184800 0x200>;
806 clocks = <&clks IMX6SX_CLK_USBOH3>;
809 fec1: ethernet@02188000 {
810 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
811 reg = <0x02188000 0x4000>;
812 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&clks IMX6SX_CLK_ENET>,
815 <&clks IMX6SX_CLK_ENET_AHB>,
816 <&clks IMX6SX_CLK_ENET_PTP>,
817 <&clks IMX6SX_CLK_ENET_REF>,
818 <&clks IMX6SX_CLK_ENET_PTP>;
819 clock-names = "ipg", "ahb", "ptp",
820 "enet_clk_ref", "enet_out";
825 reg = <0x0218c000 0x4000>;
826 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX6SX_CLK_MLB>;
833 usdhc1: usdhc@02190000 {
834 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
835 reg = <0x02190000 0x4000>;
836 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&clks IMX6SX_CLK_USDHC1>,
838 <&clks IMX6SX_CLK_USDHC1>,
839 <&clks IMX6SX_CLK_USDHC1>;
840 clock-names = "ipg", "ahb", "per";
845 usdhc2: usdhc@02194000 {
846 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
847 reg = <0x02194000 0x4000>;
848 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clks IMX6SX_CLK_USDHC2>,
850 <&clks IMX6SX_CLK_USDHC2>,
851 <&clks IMX6SX_CLK_USDHC2>;
852 clock-names = "ipg", "ahb", "per";
857 usdhc3: usdhc@02198000 {
858 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
859 reg = <0x02198000 0x4000>;
860 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SX_CLK_USDHC3>,
862 <&clks IMX6SX_CLK_USDHC3>,
863 <&clks IMX6SX_CLK_USDHC3>;
864 clock-names = "ipg", "ahb", "per";
869 usdhc4: usdhc@0219c000 {
870 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
871 reg = <0x0219c000 0x4000>;
872 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SX_CLK_USDHC4>,
874 <&clks IMX6SX_CLK_USDHC4>,
875 <&clks IMX6SX_CLK_USDHC4>;
876 clock-names = "ipg", "ahb", "per";
882 #address-cells = <1>;
884 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
885 reg = <0x021a0000 0x4000>;
886 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX6SX_CLK_I2C1>;
892 #address-cells = <1>;
894 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
895 reg = <0x021a4000 0x4000>;
896 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SX_CLK_I2C2>;
902 #address-cells = <1>;
904 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
905 reg = <0x021a8000 0x4000>;
906 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6SX_CLK_I2C3>;
911 mmdc: mmdc@021b0000 {
912 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
913 reg = <0x021b0000 0x4000>;
916 fec2: ethernet@021b4000 {
917 compatible = "fsl,imx6sx-fec";
918 reg = <0x021b4000 0x4000>;
919 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SX_CLK_ENET>,
922 <&clks IMX6SX_CLK_ENET_AHB>,
923 <&clks IMX6SX_CLK_ENET_PTP>,
924 <&clks IMX6SX_CLK_ENET2_REF_125M>,
925 <&clks IMX6SX_CLK_ENET_PTP>;
926 clock-names = "ipg", "ahb", "ptp",
927 "enet_clk_ref", "enet_out";
931 weim: weim@021b8000 {
932 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
933 reg = <0x021b8000 0x4000>;
934 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
938 ocotp: ocotp-ctrl@021bc000 {
939 compatible = "syscon";
940 reg = <0x021bc000 0x4000>;
941 clocks = <&clks IMX6SX_CLK_OCOTP>;
944 ocotp-fuse@021bc000 {
945 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
946 reg = <0x021bc000 0x4000>;
947 clocks = <&clks IMX6SX_CLK_OCOTP>;
951 compatible = "fsl,imx6sx-sai";
952 reg = <0x021d4000 0x4000>;
953 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
955 <&clks IMX6SX_CLK_SAI1>,
956 <&clks 0>, <&clks 0>;
957 clock-names = "bus", "mclk1", "mclk2", "mclk3";
958 dma-names = "rx", "tx";
959 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
960 dma-source = <&gpr 0 15 0 16>;
964 audmux: audmux@021d8000 {
965 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
966 reg = <0x021d8000 0x4000>;
971 compatible = "fsl,imx6sx-sai";
972 reg = <0x021dc000 0x4000>;
973 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
975 <&clks IMX6SX_CLK_SAI2>,
976 <&clks 0>, <&clks 0>;
977 clock-names = "bus", "mclk1", "mclk2", "mclk3";
978 dma-names = "rx", "tx";
979 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
980 dma-source = <&gpr 0 17 0 18>;
984 qspi1: qspi@021e0000 {
985 #address-cells = <1>;
987 compatible = "fsl,imx6sx-qspi";
988 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
989 reg-names = "QuadSPI", "QuadSPI-memory";
990 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&clks IMX6SX_CLK_QSPI1>,
992 <&clks IMX6SX_CLK_QSPI1>;
993 clock-names = "qspi_en", "qspi";
997 qspi2: qspi@021e4000 {
998 #address-cells = <1>;
1000 compatible = "fsl,imx6sx-qspi";
1001 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1002 reg-names = "QuadSPI", "QuadSPI-memory";
1003 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&clks IMX6SX_CLK_QSPI2>,
1005 <&clks IMX6SX_CLK_QSPI2>;
1006 clock-names = "qspi_en", "qspi";
1007 status = "disabled";
1010 uart2: serial@021e8000 {
1011 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1012 reg = <0x021e8000 0x4000>;
1013 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1015 <&clks IMX6SX_CLK_UART_SERIAL>;
1016 clock-names = "ipg", "per";
1017 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1018 dma-names = "rx", "tx";
1019 status = "disabled";
1022 uart3: serial@021ec000 {
1023 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1024 reg = <0x021ec000 0x4000>;
1025 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1027 <&clks IMX6SX_CLK_UART_SERIAL>;
1028 clock-names = "ipg", "per";
1029 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1030 dma-names = "rx", "tx";
1031 status = "disabled";
1034 uart4: serial@021f0000 {
1035 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1036 reg = <0x021f0000 0x4000>;
1037 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1039 <&clks IMX6SX_CLK_UART_SERIAL>;
1040 clock-names = "ipg", "per";
1041 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1042 dma-names = "rx", "tx";
1043 status = "disabled";
1046 uart5: serial@021f4000 {
1047 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1048 reg = <0x021f4000 0x4000>;
1049 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1051 <&clks IMX6SX_CLK_UART_SERIAL>;
1052 clock-names = "ipg", "per";
1053 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1054 dma-names = "rx", "tx";
1055 status = "disabled";
1058 i2c4: i2c@021f8000 {
1059 #address-cells = <1>;
1061 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1062 reg = <0x021f8000 0x4000>;
1063 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6SX_CLK_I2C4>;
1065 status = "disabled";
1069 aips3: aips-bus@02200000 {
1070 compatible = "fsl,aips-bus", "simple-bus";
1071 #address-cells = <1>;
1073 reg = <0x02200000 0x100000>;
1077 compatible = "fsl,spba-bus", "simple-bus";
1078 #address-cells = <1>;
1080 reg = <0x02240000 0x40000>;
1083 dcic1: dcic@0220c000 {
1084 compatible = "fsl,imx6sx-dcic";
1085 reg = <0x0220c000 0x4000>;
1086 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&clks IMX6SX_CLK_DCIC1>,
1088 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1089 clock-names = "dcic", "disp-axi";
1091 status = "disabled";
1094 dcic2: dcic@02210000 {
1095 compatible = "fsl,imx6sx-dcic";
1096 reg = <0x02210000 0x4000>;
1097 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX6SX_CLK_DCIC2>,
1099 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1100 clock-names = "dcic", "disp-axi";
1102 status = "disabled";
1105 csi1: csi@02214000 {
1106 reg = <0x02214000 0x4000>;
1107 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1109 <&clks IMX6SX_CLK_CSI>,
1110 <&clks IMX6SX_CLK_DCIC1>;
1111 clock-names = "disp-axi", "csi_mclk", "dcic";
1112 status = "disabled";
1116 compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1117 reg = <0x02218000 0x4000>;
1118 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1120 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1121 clock-names = "pxp-axi", "disp-axi";
1122 status = "disabled";
1125 csi2: csi@0221c000 {
1126 reg = <0x0221c000 0x4000>;
1127 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1129 <&clks IMX6SX_CLK_CSI>,
1130 <&clks IMX6SX_CLK_DCIC2>;
1131 clock-names = "disp-axi", "csi_mclk", "dcic";
1132 status = "disabled";
1135 lcdif1: lcdif@02220000 {
1136 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1137 reg = <0x02220000 0x4000>;
1138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1140 <&clks IMX6SX_CLK_LCDIF_APB>,
1141 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1142 clock-names = "pix", "axi", "disp_axi";
1143 status = "disabled";
1146 lcdif2: lcdif@02224000 {
1147 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1148 reg = <0x02224000 0x4000>;
1149 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1151 <&clks IMX6SX_CLK_LCDIF_APB>,
1152 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1153 clock-names = "pix", "axi", "disp_axi";
1154 status = "disabled";
1157 vadc: vadc@02228000 {
1158 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1159 reg-names = "vadc-vafe", "vadc-vdec";
1160 clocks = <&clks IMX6SX_CLK_VADC>,
1161 <&clks IMX6SX_CLK_CSI>;
1162 clock-names = "vadc", "csi";
1163 status = "disabled";
1167 adc1: adc@02280000 {
1168 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1169 reg = <0x02280000 0x4000>;
1170 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&clks IMX6SX_CLK_IPG>;
1172 clock-names = "adc";
1173 status = "disabled";
1176 adc2: adc@02284000 {
1177 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1178 reg = <0x02284000 0x4000>;
1179 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&clks IMX6SX_CLK_IPG>;
1181 clock-names = "adc";
1182 status = "disabled";
1185 wdog3: wdog@02288000 {
1186 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1187 reg = <0x02288000 0x4000>;
1188 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&clks IMX6SX_CLK_DUMMY>;
1190 status = "disabled";
1193 ecspi5: ecspi@0228c000 {
1194 #address-cells = <1>;
1196 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1197 reg = <0x0228c000 0x4000>;
1198 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1200 <&clks IMX6SX_CLK_ECSPI5>;
1201 clock-names = "ipg", "per";
1202 status = "disabled";
1205 uart6: serial@022a0000 {
1206 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1207 reg = <0x022a0000 0x4000>;
1208 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1210 <&clks IMX6SX_CLK_UART_SERIAL>;
1211 clock-names = "ipg", "per";
1212 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1213 dma-names = "rx", "tx";
1214 status = "disabled";
1217 pwm5: pwm@022a4000 {
1218 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1219 reg = <0x022a4000 0x4000>;
1220 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX6SX_CLK_PWM5>,
1222 <&clks IMX6SX_CLK_PWM5>;
1223 clock-names = "ipg", "per";
1227 pwm6: pwm@022a8000 {
1228 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1229 reg = <0x022a8000 0x4000>;
1230 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clks IMX6SX_CLK_PWM6>,
1232 <&clks IMX6SX_CLK_PWM6>;
1233 clock-names = "ipg", "per";
1237 pwm7: pwm@022ac000 {
1238 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1239 reg = <0x022ac000 0x4000>;
1240 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&clks IMX6SX_CLK_PWM7>,
1242 <&clks IMX6SX_CLK_PWM7>;
1243 clock-names = "ipg", "per";
1247 pwm8: pwm@0022b0000 {
1248 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1249 reg = <0x0022b0000 0x4000>;
1250 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&clks IMX6SX_CLK_PWM8>,
1252 <&clks IMX6SX_CLK_PWM8>;
1253 clock-names = "ipg", "per";
1258 pcie: pcie@0x08000000 {
1259 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1260 reg = <0x08ffc000 0x4000>; /* DBI */
1261 #address-cells = <3>;
1263 device_type = "pci";
1264 /* configuration space */
1265 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1266 /* downstream I/O */
1267 0x81000000 0 0 0x08f80000 0 0x00010000
1268 /* non-prefetchable memory */
1269 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1271 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1272 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1273 <&clks IMX6SX_CLK_PCIE_AXI>,
1274 <&clks IMX6SX_CLK_LVDS1_OUT>,
1275 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1276 clock-names = "pcie_ref_125m", "pcie_axi",
1277 "lvds_gate", "display_axi";
1278 status = "disabled";