arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                         >;
  66                         fsl,soc-operating-points = <
  67                                 /* ARM kHz  SOC uV */
  68                                 996000      1175000
  69                                 792000      1175000
  70                                 396000      1175000
  71                         >;
  72                         clock-latency = <61036>; /* two CLK32 periods */
  73                         clocks = <&clks IMX6SX_CLK_ARM>,
  74                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6SX_CLK_STEP>,
  76                                  <&clks IMX6SX_CLK_PLL1_SW>,
  77                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  78                         clock-names = "arm", "pll2_pfd2_396m", "step",
  79                                       "pll1_sw", "pll1_sys";
  80                         arm-supply = <&reg_arm>;
  81                         soc-supply = <&reg_soc>;
  82                 };
  83         };
  84
  85         intc: interrupt-controller@00a01000 {
  86                 compatible = "arm,cortex-a9-gic";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x00a01000 0x1000>,
  90                       <0x00a00100 0x100>;
  91         };
  92
  93         clocks {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ckil: clock@0 {
  98                         compatible = "fixed-clock";
  99                         reg = <0>;
 100                         #clock-cells = <0>;
 101                         clock-frequency = <32768>;
 102                         clock-output-names = "ckil";
 103                 };
 104
 105                 osc: clock@1 {
 106                         compatible = "fixed-clock";
 107                         reg = <1>;
 108                         #clock-cells = <0>;
 109                         clock-frequency = <24000000>;
 110                         clock-output-names = "osc";
 111                 };
 112
 113                 ipp_di0: clock@2 {
 114                         compatible = "fixed-clock";
 115                         reg = <2>;
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                         clock-output-names = "ipp_di0";
 119                 };
 120
 121                 ipp_di1: clock@3 {
 122                         compatible = "fixed-clock";
 123                         reg = <3>;
 124                         #clock-cells = <0>;
 125                         clock-frequency = <0>;
 126                         clock-output-names = "ipp_di1";
 127                 };
 128         };
 129
 130         soc {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "simple-bus";
 134                 interrupt-parent = <&intc>;
 135                 ranges;
 136
 137                 pmu {
 138                         compatible = "arm,cortex-a9-pmu";
 139                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 140                 };
 141
 142                 ocram: sram@00900000 {
 143                         compatible = "mmio-sram";
 144                         reg = <0x00900000 0x20000>;
 145                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 146                 };
 147
 148                 L2: l2-cache@00a02000 {
 149                         compatible = "arm,pl310-cache";
 150                         reg = <0x00a02000 0x1000>;
 151                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 152                         cache-unified;
 153                         cache-level = <2>;
 154                         arm,tag-latency = <4 2 3>;
 155                         arm,data-latency = <4 2 3>;
 156                 };
 157
 158                 dma_apbh: dma-apbh@01804000 {
 159                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 160                         reg = <0x01804000 0x2000>;
 161                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 162                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 165                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 166                         #dma-cells = <1>;
 167                         dma-channels = <4>;
 168                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 169                 };
 170
 171                 gpmi: gpmi-nand@01806000{
 172                         compatible = "fsl,imx6sx-gpmi-nand";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 176                         reg-names = "gpmi-nand", "bch";
 177                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 178                         interrupt-names = "bch";
 179                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 180                                  <&clks IMX6SX_CLK_GPMI_APB>,
 181                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 182                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 183                                  <&clks IMX6SX_CLK_PER1_BCH>;
 184                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 185                                       "gpmi_bch_apb", "per1_bch";
 186                         dmas = <&dma_apbh 0>;
 187                         dma-names = "rx-tx";
 188                         status = "disabled";
 189                 };
 190
 191                 aips1: aips-bus@02000000 {
 192                         compatible = "fsl,aips-bus", "simple-bus";
 193                         #address-cells = <1>;
 194                         #size-cells = <1>;
 195                         reg = <0x02000000 0x100000>;
 196                         ranges;
 197
 198                         spba-bus@02000000 {
 199                                 compatible = "fsl,spba-bus", "simple-bus";
 200                                 #address-cells = <1>;
 201                                 #size-cells = <1>;
 202                                 reg = <0x02000000 0x40000>;
 203                                 ranges;
 204
 205                                 spdif: spdif@02004000 {
 206                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 207                                         reg = <0x02004000 0x4000>;
 208                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 209                                         dmas = <&sdma 14 18 0>,
 210                                                <&sdma 15 18 0>;
 211                                         dma-names = "rx", "tx";
 212                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 213                                                  <&clks IMX6SX_CLK_OSC>,
 214                                                  <&clks IMX6SX_CLK_SPDIF>,
 215                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 216                                                  <&clks IMX6SX_CLK_IPG>,
 217                                                  <&clks 0>, <&clks 0>,
 218                                                  <&clks IMX6SX_CLK_SPBA>;
 219                                         clock-names = "core", "rxtx0",
 220                                                       "rxtx1", "rxtx2",
 221                                                       "rxtx3", "rxtx4",
 222                                                       "rxtx5", "rxtx6",
 223                                                       "rxtx7", "dma";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi1: ecspi@02008000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x02008000 0x4000>;
 232                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 234                                                  <&clks IMX6SX_CLK_ECSPI1>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 ecspi2: ecspi@0200c000 {
 240                                         #address-cells = <1>;
 241                                         #size-cells = <0>;
 242                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 243                                         reg = <0x0200c000 0x4000>;
 244                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 245                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 246                                                  <&clks IMX6SX_CLK_ECSPI2>;
 247                                         clock-names = "ipg", "per";
 248                                         status = "disabled";
 249                                 };
 250
 251                                 ecspi3: ecspi@02010000 {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 255                                         reg = <0x02010000 0x4000>;
 256                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 257                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 258                                                  <&clks IMX6SX_CLK_ECSPI3>;
 259                                         clock-names = "ipg", "per";
 260                                         status = "disabled";
 261                                 };
 262
 263                                 ecspi4: ecspi@02014000 {
 264                                         #address-cells = <1>;
 265                                         #size-cells = <0>;
 266                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 267                                         reg = <0x02014000 0x4000>;
 268                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 269                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 270                                                  <&clks IMX6SX_CLK_ECSPI4>;
 271                                         clock-names = "ipg", "per";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 uart1: serial@02020000 {
 276                                         compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
 277                                         reg = <0x02020000 0x4000>;
 278                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 279                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 280                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 281                                         clock-names = "ipg", "per";
 282                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 283                                         dma-names = "rx", "tx";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 esai: esai@02024000 {
 288                                         reg = <0x02024000 0x4000>;
 289                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 290                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 291                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 292                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 293                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 294                                                  <&clks IMX6SX_CLK_SPBA>;
 295                                         clock-names = "core", "mem", "extal",
 296                                                       "fsys", "dma";
 297                                         status = "disabled";
 298                                 };
 299
 300                                 ssi1: ssi@02028000 {
 301                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 302                                         reg = <0x02028000 0x4000>;
 303                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 305                                                  <&clks IMX6SX_CLK_SSI1>;
 306                                         clock-names = "ipg", "baud";
 307                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 308                                         dma-names = "rx", "tx";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 ssi2: ssi@0202c000 {
 313                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 314                                         reg = <0x0202c000 0x4000>;
 315                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 316                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 317                                                  <&clks IMX6SX_CLK_SSI2>;
 318                                         clock-names = "ipg", "baud";
 319                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 320                                         dma-names = "rx", "tx";
 321                                         status = "disabled";
 322                                 };
 323
 324                                 ssi3: ssi@02030000 {
 325                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 326                                         reg = <0x02030000 0x4000>;
 327                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 328                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 329                                                  <&clks IMX6SX_CLK_SSI3>;
 330                                         clock-names = "ipg", "baud";
 331                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 332                                         dma-names = "rx", "tx";
 333                                         status = "disabled";
 334                                 };
 335
 336                                 asrc: asrc@02034000 {
 337                                         compatible = "fsl,imx53-asrc";
 338                                         reg = <0x02034000 0x4000>;
 339                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 340                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 341                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 342                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 343                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 344                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 345                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 346                                                 <&clks IMX6SX_CLK_SPBA>;
 347                                         clock-names = "mem", "ipg", "asrck_0",
 348                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 349                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 350                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 351                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 352                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 353                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 354                                         dma-names = "rxa", "rxb", "rxc",
 355                                                     "txa", "txb", "txc";
 356                                         fsl,asrc-rate  = <48000>;
 357                                         fsl,asrc-width = <16>;
 358                                         status = "okay";
 359                                 };
 360                         };
 361
 362                         pwm1: pwm@02080000 {
 363                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 364                                 reg = <0x02080000 0x4000>;
 365                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 367                                          <&clks IMX6SX_CLK_PWM1>;
 368                                 clock-names = "ipg", "per";
 369                                 #pwm-cells = <2>;
 370                         };
 371
 372                         pwm2: pwm@02084000 {
 373                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 374                                 reg = <0x02084000 0x4000>;
 375                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 377                                          <&clks IMX6SX_CLK_PWM2>;
 378                                 clock-names = "ipg", "per";
 379                                 #pwm-cells = <2>;
 380                         };
 381
 382                         pwm3: pwm@02088000 {
 383                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 384                                 reg = <0x02088000 0x4000>;
 385                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 387                                          <&clks IMX6SX_CLK_PWM3>;
 388                                 clock-names = "ipg", "per";
 389                                 #pwm-cells = <2>;
 390                         };
 391
 392                         pwm4: pwm@0208c000 {
 393                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 394                                 reg = <0x0208c000 0x4000>;
 395                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 396                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 397                                          <&clks IMX6SX_CLK_PWM4>;
 398                                 clock-names = "ipg", "per";
 399                                 #pwm-cells = <2>;
 400                         };
 401
 402                         flexcan1: can@02090000 {
 403                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 404                                 reg = <0x02090000 0x4000>;
 405                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 407                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 408                                 clock-names = "ipg", "per";
 409                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 410                                 status = "disabled";
 411                         };
 412
 413                         flexcan2: can@02094000 {
 414                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 415                                 reg = <0x02094000 0x4000>;
 416                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 418                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 419                                 clock-names = "ipg", "per";
 420                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 421                                 status = "disabled";
 422                         };
 423
 424                         gpt: gpt@02098000 {
 425                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 426                                 reg = <0x02098000 0x4000>;
 427                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 429                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 430                                 clock-names = "ipg", "per";
 431                         };
 432
 433                         gpio1: gpio@0209c000 {
 434                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 435                                 reg = <0x0209c000 0x4000>;
 436                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 437                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 438                                 gpio-controller;
 439                                 #gpio-cells = <2>;
 440                                 interrupt-controller;
 441                                 #interrupt-cells = <2>;
 442                         };
 443
 444                         gpio2: gpio@020a0000 {
 445                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 446                                 reg = <0x020a0000 0x4000>;
 447                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 448                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 449                                 gpio-controller;
 450                                 #gpio-cells = <2>;
 451                                 interrupt-controller;
 452                                 #interrupt-cells = <2>;
 453                         };
 454
 455                         gpio3: gpio@020a4000 {
 456                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 457                                 reg = <0x020a4000 0x4000>;
 458                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 460                                 gpio-controller;
 461                                 #gpio-cells = <2>;
 462                                 interrupt-controller;
 463                                 #interrupt-cells = <2>;
 464                         };
 465
 466                         gpio4: gpio@020a8000 {
 467                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 468                                 reg = <0x020a8000 0x4000>;
 469                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 471                                 gpio-controller;
 472                                 #gpio-cells = <2>;
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <2>;
 475                         };
 476
 477                         gpio5: gpio@020ac000 {
 478                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 479                                 reg = <0x020ac000 0x4000>;
 480                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 481                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 482                                 gpio-controller;
 483                                 #gpio-cells = <2>;
 484                                 interrupt-controller;
 485                                 #interrupt-cells = <2>;
 486                         };
 487
 488                         gpio6: gpio@020b0000 {
 489                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 490                                 reg = <0x020b0000 0x4000>;
 491                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 492                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 493                                 gpio-controller;
 494                                 #gpio-cells = <2>;
 495                                 interrupt-controller;
 496                                 #interrupt-cells = <2>;
 497                         };
 498
 499                         gpio7: gpio@020b4000 {
 500                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 501                                 reg = <0x020b4000 0x4000>;
 502                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 503                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 interrupt-controller;
 507                                 #interrupt-cells = <2>;
 508                         };
 509
 510                         kpp: kpp@020b8000 {
 511                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 512                                 reg = <0x020b8000 0x4000>;
 513                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 515                                 status = "disabled";
 516                         };
 517
 518                         wdog1: wdog@020bc000 {
 519                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 520                                 reg = <0x020bc000 0x4000>;
 521                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 522                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 523                         };
 524
 525                         wdog2: wdog@020c0000 {
 526                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 527                                 reg = <0x020c0000 0x4000>;
 528                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 529                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 530                                 status = "disabled";
 531                         };
 532
 533                         clks: ccm@020c4000 {
 534                                 compatible = "fsl,imx6sx-ccm";
 535                                 reg = <0x020c4000 0x4000>;
 536                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 538                                 #clock-cells = <1>;
 539                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 540                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 541                         };
 542
 543                         anatop: anatop@020c8000 {
 544                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 545                                              "syscon", "simple-bus";
 546                                 reg = <0x020c8000 0x1000>;
 547                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 548                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 549                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 550
 551                                 regulator-1p1@110 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd1p1";
 554                                         regulator-min-microvolt = <800000>;
 555                                         regulator-max-microvolt = <1375000>;
 556                                         regulator-always-on;
 557                                         anatop-reg-offset = <0x110>;
 558                                         anatop-vol-bit-shift = <8>;
 559                                         anatop-vol-bit-width = <5>;
 560                                         anatop-min-bit-val = <4>;
 561                                         anatop-min-voltage = <800000>;
 562                                         anatop-max-voltage = <1375000>;
 563                                 };
 564
 565                                 regulator-3p0@120 {
 566                                         compatible = "fsl,anatop-regulator";
 567                                         regulator-name = "vdd3p0";
 568                                         regulator-min-microvolt = <2800000>;
 569                                         regulator-max-microvolt = <3150000>;
 570                                         regulator-always-on;
 571                                         anatop-reg-offset = <0x120>;
 572                                         anatop-vol-bit-shift = <8>;
 573                                         anatop-vol-bit-width = <5>;
 574                                         anatop-min-bit-val = <0>;
 575                                         anatop-min-voltage = <2625000>;
 576                                         anatop-max-voltage = <3400000>;
 577                                 };
 578
 579                                 regulator-2p5@130 {
 580                                         compatible = "fsl,anatop-regulator";
 581                                         regulator-name = "vdd2p5";
 582                                         regulator-min-microvolt = <2100000>;
 583                                         regulator-max-microvolt = <2875000>;
 584                                         regulator-always-on;
 585                                         anatop-reg-offset = <0x130>;
 586                                         anatop-vol-bit-shift = <8>;
 587                                         anatop-vol-bit-width = <5>;
 588                                         anatop-min-bit-val = <0>;
 589                                         anatop-min-voltage = <2100000>;
 590                                         anatop-max-voltage = <2875000>;
 591                                 };
 592
 593                                 reg_arm: regulator-vddcore@140 {
 594                                         compatible = "fsl,anatop-regulator";
 595                                         regulator-name = "cpu";
 596                                         regulator-min-microvolt = <725000>;
 597                                         regulator-max-microvolt = <1450000>;
 598                                         regulator-always-on;
 599                                         anatop-reg-offset = <0x140>;
 600                                         anatop-vol-bit-shift = <0>;
 601                                         anatop-vol-bit-width = <5>;
 602                                         anatop-delay-reg-offset = <0x170>;
 603                                         anatop-delay-bit-shift = <24>;
 604                                         anatop-delay-bit-width = <2>;
 605                                         anatop-min-bit-val = <1>;
 606                                         anatop-min-voltage = <725000>;
 607                                         anatop-max-voltage = <1450000>;
 608                                 };
 609
 610                                 reg_pcie: regulator-vddpcie@140 {
 611                                         compatible = "fsl,anatop-regulator";
 612                                         regulator-name = "vddpcie";
 613                                         regulator-min-microvolt = <725000>;
 614                                         regulator-max-microvolt = <1450000>;
 615                                         anatop-reg-offset = <0x140>;
 616                                         anatop-vol-bit-shift = <9>;
 617                                         anatop-vol-bit-width = <5>;
 618                                         anatop-delay-reg-offset = <0x170>;
 619                                         anatop-delay-bit-shift = <26>;
 620                                         anatop-delay-bit-width = <2>;
 621                                         anatop-min-bit-val = <1>;
 622                                         anatop-min-voltage = <725000>;
 623                                         anatop-max-voltage = <1450000>;
 624                                 };
 625
 626                                 reg_soc: regulator-vddsoc@140 {
 627                                         compatible = "fsl,anatop-regulator";
 628                                         regulator-name = "vddsoc";
 629                                         regulator-min-microvolt = <725000>;
 630                                         regulator-max-microvolt = <1450000>;
 631                                         regulator-always-on;
 632                                         anatop-reg-offset = <0x140>;
 633                                         anatop-vol-bit-shift = <18>;
 634                                         anatop-vol-bit-width = <5>;
 635                                         anatop-delay-reg-offset = <0x170>;
 636                                         anatop-delay-bit-shift = <28>;
 637                                         anatop-delay-bit-width = <2>;
 638                                         anatop-min-bit-val = <1>;
 639                                         anatop-min-voltage = <725000>;
 640                                         anatop-max-voltage = <1450000>;
 641                                 };
 642                         };
 643
 644                         tempmon: tempmon {
 645                                 compatible = "fsl,imx6sx-tempmon";
 646                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 647                                 fsl,tempmon = <&anatop>;
 648                                 fsl,tempmon-data = <&ocotp>;
 649                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 650                         };
 651
 652                         usbphy1: usbphy@020c9000 {
 653                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 654                                 reg = <0x020c9000 0x1000>;
 655                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 656                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 657                                 fsl,anatop = <&anatop>;
 658                         };
 659
 660                         usbphy2: usbphy@020ca000 {
 661                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 662                                 reg = <0x020ca000 0x1000>;
 663                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 664                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 665                                 fsl,anatop = <&anatop>;
 666                         };
 667
 668                         snvs: snvs@020cc000 {
 669                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 670                                 #address-cells = <1>;
 671                                 #size-cells = <1>;
 672                                 ranges = <0 0x020cc000 0x4000>;
 673
 674                                 snvs-rtc-lp@34 {
 675                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 676                                         reg = <0x34 0x58>;
 677                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 678                                 };
 679                         };
 680
 681                         epit1: epit@020d0000 {
 682                                 reg = <0x020d0000 0x4000>;
 683                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 684                         };
 685
 686                         epit2: epit@020d4000 {
 687                                 reg = <0x020d4000 0x4000>;
 688                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 689                         };
 690
 691                         src: src@020d8000 {
 692                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 693                                 reg = <0x020d8000 0x4000>;
 694                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 695                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 696                                 #reset-cells = <1>;
 697                         };
 698
 699                         gpc: gpc@020dc000 {
 700                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 701                                 reg = <0x020dc000 0x4000>;
 702                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 703                         };
 704
 705                         iomuxc: iomuxc@020e0000 {
 706                                 compatible = "fsl,imx6sx-iomuxc";
 707                                 reg = <0x020e0000 0x4000>;
 708                         };
 709
 710                         gpr: iomuxc-gpr@020e4000 {
 711                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 712                                 reg = <0x020e4000 0x4000>;
 713                         };
 714
 715                         canfd1: canfd@020e8000 {
 716                                 compatible = "bosch,m_can";
 717                                 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
 718                                 reg-names = "canfd", "message_ram";
 719                                 interrupts = <0 114 0x04>;
 720                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 721                                 mram-cfg = <0x0 0 0 32 0 0 0 1>;
 722                                 status = "disabled";
 723                         };
 724
 725                         canfd2: canfd@020f0000 {
 726                                 compatible = "bosch,m_can";
 727                                 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
 728                                 reg-names = "canfd", "message_ram";
 729                                 interrupts = <0 115 0x04>;
 730                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 731                                 mram-cfg = <0x400 0 0 32 0 0 0 1>;
 732                                 status = "disabled";
 733                         };
 734
 735                         ldb: ldb@020e0014 {
 736                                 #address-cells = <1>;
 737                                 #size-cells = <0>;
 738                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 739                                 gpr = <&gpr>;
 740                                 status = "disabled";
 741
 742                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 743                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 744                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 745                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 746                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 747                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 748                                 clock-names = "ldb_di0",
 749                                               "di0_sel",
 750                                               "di1_sel",
 751                                               "ldb_di0_div_3_5",
 752                                               "ldb_di0_div_7",
 753                                               "ldb_di0_div_sel";
 754
 755                                 lvds-channel@0 {
 756                                         reg = <0>;
 757                                         status = "disabled";
 758                                 };
 759                         };
 760
 761                         sdma: sdma@020ec000 {
 762                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 763                                 reg = <0x020ec000 0x4000>;
 764                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 766                                          <&clks IMX6SX_CLK_SDMA>;
 767                                 clock-names = "ipg", "ahb";
 768                                 #dma-cells = <3>;
 769                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 770                         };
 771                 };
 772
 773                 aips2: aips-bus@02100000 {
 774                         compatible = "fsl,aips-bus", "simple-bus";
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777                         reg = <0x02100000 0x100000>;
 778                         ranges;
 779
 780                         usbotg1: usb@02184000 {
 781                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 782                                 reg = <0x02184000 0x200>;
 783                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 784                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 785                                 fsl,usbphy = <&usbphy1>;
 786                                 fsl,usbmisc = <&usbmisc 0>;
 787                                 fsl,anatop = <&anatop>;
 788                                 status = "disabled";
 789                         };
 790
 791                         usbotg2: usb@02184200 {
 792                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 793                                 reg = <0x02184200 0x200>;
 794                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 796                                 fsl,usbphy = <&usbphy2>;
 797                                 fsl,usbmisc = <&usbmisc 1>;
 798                                 status = "disabled";
 799                         };
 800
 801                         usbh: usb@02184400 {
 802                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 803                                 reg = <0x02184400 0x200>;
 804                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 805                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 806                                 fsl,usbmisc = <&usbmisc 2>;
 807                                 phy_type = "hsic";
 808                                 fsl,anatop = <&anatop>;
 809                                 status = "disabled";
 810                         };
 811
 812                         usbmisc: usbmisc@02184800 {
 813                                 #index-cells = <1>;
 814                                 compatible = "fsl,imx6sx-usbmisc";
 815                                 reg = <0x02184800 0x200>;
 816                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 817                         };
 818
 819                         fec1: ethernet@02188000 {
 820                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 821                                 reg = <0x02188000 0x4000>;
 822                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 823                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 824                                 clocks = <&clks IMX6SX_CLK_ENET>,
 825                                          <&clks IMX6SX_CLK_ENET_AHB>,
 826                                          <&clks IMX6SX_CLK_ENET_PTP>,
 827                                          <&clks IMX6SX_CLK_ENET_REF>,
 828                                          <&clks IMX6SX_CLK_ENET_PTP>;
 829                                 clock-names = "ipg", "ahb", "ptp",
 830                                               "enet_clk_ref", "enet_out";
 831                                 fsl,num-tx-queues=<3>;
 832                                 fsl,num-rx-queues=<3>;
 833                                 status = "disabled";
 834                         };
 835
 836                         mlb: mlb@0218c000 {
 837                                 reg = <0x0218c000 0x4000>;
 838                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 839                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 840                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&clks IMX6SX_CLK_MLB>;
 842                                 status = "disabled";
 843                         };
 844
 845                         usdhc1: usdhc@02190000 {
 846                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 847                                 reg = <0x02190000 0x4000>;
 848                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 849                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 850                                          <&clks IMX6SX_CLK_USDHC1>,
 851                                          <&clks IMX6SX_CLK_USDHC1>;
 852                                 clock-names = "ipg", "ahb", "per";
 853                                 bus-width = <4>;
 854                                 status = "disabled";
 855                         };
 856
 857                         usdhc2: usdhc@02194000 {
 858                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 859                                 reg = <0x02194000 0x4000>;
 860                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 861                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 862                                          <&clks IMX6SX_CLK_USDHC2>,
 863                                          <&clks IMX6SX_CLK_USDHC2>;
 864                                 clock-names = "ipg", "ahb", "per";
 865                                 bus-width = <4>;
 866                                 status = "disabled";
 867                         };
 868
 869                         usdhc3: usdhc@02198000 {
 870                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 871                                 reg = <0x02198000 0x4000>;
 872                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 874                                          <&clks IMX6SX_CLK_USDHC3>,
 875                                          <&clks IMX6SX_CLK_USDHC3>;
 876                                 clock-names = "ipg", "ahb", "per";
 877                                 bus-width = <4>;
 878                                 status = "disabled";
 879                         };
 880
 881                         usdhc4: usdhc@0219c000 {
 882                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 883                                 reg = <0x0219c000 0x4000>;
 884                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 886                                          <&clks IMX6SX_CLK_USDHC4>,
 887                                          <&clks IMX6SX_CLK_USDHC4>;
 888                                 clock-names = "ipg", "ahb", "per";
 889                                 bus-width = <4>;
 890                                 status = "disabled";
 891                         };
 892
 893                         i2c1: i2c@021a0000 {
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 897                                 reg = <0x021a0000 0x4000>;
 898                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 899                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 900                                 status = "disabled";
 901                         };
 902
 903                         i2c2: i2c@021a4000 {
 904                                 #address-cells = <1>;
 905                                 #size-cells = <0>;
 906                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 907                                 reg = <0x021a4000 0x4000>;
 908                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 909                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 910                                 status = "disabled";
 911                         };
 912
 913                         i2c3: i2c@021a8000 {
 914                                 #address-cells = <1>;
 915                                 #size-cells = <0>;
 916                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 917                                 reg = <0x021a8000 0x4000>;
 918                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 919                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 920                                 status = "disabled";
 921                         };
 922
 923                         mmdc: mmdc@021b0000 {
 924                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 925                                 reg = <0x021b0000 0x4000>;
 926                         };
 927
 928                         fec2: ethernet@021b4000 {
 929                                 compatible = "fsl,imx6sx-fec";
 930                                 reg = <0x021b4000 0x4000>;
 931                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 932                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 933                                 clocks = <&clks IMX6SX_CLK_ENET>,
 934                                          <&clks IMX6SX_CLK_ENET_AHB>,
 935                                          <&clks IMX6SX_CLK_ENET_PTP>,
 936                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
 937                                          <&clks IMX6SX_CLK_ENET_PTP>;
 938                                 clock-names = "ipg", "ahb", "ptp",
 939                                               "enet_clk_ref", "enet_out";
 940                                 status = "disabled";
 941                         };
 942
 943                         weim: weim@021b8000 {
 944                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
 945                                 reg = <0x021b8000 0x4000>;
 946                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 947                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
 948                         };
 949
 950                         ocotp: ocotp-ctrl@021bc000 {
 951                                 compatible = "syscon";
 952                                 reg = <0x021bc000 0x4000>;
 953                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 954                         };
 955
 956                         ocotp-fuse@021bc000 {
 957                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
 958                                 reg = <0x021bc000 0x4000>;
 959                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 960                         };
 961
 962                         sai1: sai@021d4000 {
 963                                 compatible = "fsl,imx6sx-sai";
 964                                 reg = <0x021d4000 0x4000>;
 965                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 966                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
 967                                          <&clks IMX6SX_CLK_SAI1>,
 968                                          <&clks 0>, <&clks 0>;
 969                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 970                                 dma-names = "rx", "tx";
 971                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
 972                                 dma-source = <&gpr 0 15 0 16>;
 973                                 status = "disabled";
 974                         };
 975
 976                         audmux: audmux@021d8000 {
 977                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
 978                                 reg = <0x021d8000 0x4000>;
 979                                 status = "disabled";
 980                         };
 981
 982                         sai2: sai@021dc000 {
 983                                 compatible = "fsl,imx6sx-sai";
 984                                 reg = <0x021dc000 0x4000>;
 985                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
 987                                          <&clks IMX6SX_CLK_SAI2>,
 988                                          <&clks 0>, <&clks 0>;
 989                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 990                                 dma-names = "rx", "tx";
 991                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
 992                                 dma-source = <&gpr 0 17 0 18>;
 993                                 status = "disabled";
 994                         };
 995
 996                         qspi1: qspi@021e0000 {
 997                                 #address-cells = <1>;
 998                                 #size-cells = <0>;
 999                                 compatible = "fsl,imx6sx-qspi";
1000                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1001                                 reg-names = "QuadSPI", "QuadSPI-memory";
1002                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1003                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1004                                          <&clks IMX6SX_CLK_QSPI1>;
1005                                 clock-names = "qspi_en", "qspi";
1006                                 status = "disabled";
1007                         };
1008
1009                         qspi2: qspi@021e4000 {
1010                                 #address-cells = <1>;
1011                                 #size-cells = <0>;
1012                                 compatible = "fsl,imx6sx-qspi";
1013                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1014                                 reg-names = "QuadSPI", "QuadSPI-memory";
1015                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1017                                          <&clks IMX6SX_CLK_QSPI2>;
1018                                 clock-names = "qspi_en", "qspi";
1019                                 status = "disabled";
1020                         };
1021
1022                         uart2: serial@021e8000 {
1023                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1024                                 reg = <0x021e8000 0x4000>;
1025                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1026                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1027                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1028                                 clock-names = "ipg", "per";
1029                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1030                                 dma-names = "rx", "tx";
1031                                 status = "disabled";
1032                         };
1033
1034                         uart3: serial@021ec000 {
1035                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1036                                 reg = <0x021ec000 0x4000>;
1037                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1038                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1039                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1040                                 clock-names = "ipg", "per";
1041                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1042                                 dma-names = "rx", "tx";
1043                                 status = "disabled";
1044                         };
1045
1046                         uart4: serial@021f0000 {
1047                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1048                                 reg = <0x021f0000 0x4000>;
1049                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1050                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1051                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1052                                 clock-names = "ipg", "per";
1053                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1054                                 dma-names = "rx", "tx";
1055                                 status = "disabled";
1056                         };
1057
1058                         uart5: serial@021f4000 {
1059                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1060                                 reg = <0x021f4000 0x4000>;
1061                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1062                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1063                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1064                                 clock-names = "ipg", "per";
1065                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1066                                 dma-names = "rx", "tx";
1067                                 status = "disabled";
1068                         };
1069
1070                         i2c4: i2c@021f8000 {
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1074                                 reg = <0x021f8000 0x4000>;
1075                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1076                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1077                                 status = "disabled";
1078                         };
1079                 };
1080
1081                 aips3: aips-bus@02200000 {
1082                         compatible = "fsl,aips-bus", "simple-bus";
1083                         #address-cells = <1>;
1084                         #size-cells = <1>;
1085                         reg = <0x02200000 0x100000>;
1086                         ranges;
1087
1088                         spba-bus@02200000 {
1089                                 compatible = "fsl,spba-bus", "simple-bus";
1090                                 #address-cells = <1>;
1091                                 #size-cells = <1>;
1092                                 reg = <0x02240000 0x40000>;
1093                                 ranges;
1094
1095                                 dcic1: dcic@0220c000 {
1096                                         compatible = "fsl,imx6sx-dcic";
1097                                         reg = <0x0220c000 0x4000>;
1098                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1099                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1100                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1101                                         clock-names = "dcic", "disp-axi";
1102                                         gpr = <&gpr>;
1103                                         status = "disabled";
1104                                 };
1105
1106                                 dcic2: dcic@02210000 {
1107                                         compatible = "fsl,imx6sx-dcic";
1108                                         reg = <0x02210000 0x4000>;
1109                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1110                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1111                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1112                                         clock-names = "dcic", "disp-axi";
1113                                         gpr = <&gpr>;
1114                                         status = "disabled";
1115                                 };
1116
1117                                 csi1: csi@02214000 {
1118                                         reg = <0x02214000 0x4000>;
1119                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1120                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1121                                                  <&clks IMX6SX_CLK_CSI>,
1122                                                  <&clks IMX6SX_CLK_DCIC1>;
1123                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1124                                         status = "disabled";
1125                                 };
1126
1127                                 pxp: pxp@02218000 {
1128                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1129                                         reg = <0x02218000 0x4000>;
1130                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1131                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1132                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1133                                         clock-names = "pxp-axi", "disp-axi";
1134                                         status = "disabled";
1135                                 };
1136
1137                                 csi2: csi@0221c000 {
1138                                         reg = <0x0221c000 0x4000>;
1139                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1140                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1141                                                  <&clks IMX6SX_CLK_CSI>,
1142                                                  <&clks IMX6SX_CLK_DCIC2>;
1143                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1144                                         status = "disabled";
1145                                 };
1146
1147                                 lcdif1: lcdif@02220000 {
1148                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1149                                         reg = <0x02220000 0x4000>;
1150                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1151                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1152                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1153                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1154                                         clock-names = "pix", "axi", "disp_axi";
1155                                         status = "disabled";
1156                                 };
1157
1158                                 lcdif2: lcdif@02224000 {
1159                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1160                                         reg = <0x02224000 0x4000>;
1161                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1162                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1163                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1164                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1165                                         clock-names = "pix", "axi", "disp_axi";
1166                                         status = "disabled";
1167                                 };
1168
1169                                 vadc: vadc@02228000 {
1170                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1171                                         reg-names = "vadc-vafe", "vadc-vdec";
1172                                         clocks = <&clks IMX6SX_CLK_VADC>,
1173                                                  <&clks IMX6SX_CLK_CSI>;
1174                                         clock-names = "vadc", "csi";
1175                                         status = "disabled";
1176                                 };
1177                         };
1178
1179                         adc1: adc@02280000 {
1180                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1181                                 reg = <0x02280000 0x4000>;
1182                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1183                                 clocks = <&clks IMX6SX_CLK_IPG>;
1184                                 num-channels = <4>;
1185                                 clock-names = "adc";
1186                                 status = "disabled";
1187                         };
1188
1189                         adc2: adc@02284000 {
1190                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1191                                 reg = <0x02284000 0x4000>;
1192                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1193                                 clocks = <&clks IMX6SX_CLK_IPG>;
1194                                 num-channels = <4>;
1195                                 clock-names = "adc";
1196                                 status = "disabled";
1197                         };
1198
1199                         wdog3: wdog@02288000 {
1200                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1201                                 reg = <0x02288000 0x4000>;
1202                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1203                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1204                                 status = "disabled";
1205                         };
1206
1207                         ecspi5: ecspi@0228c000 {
1208                                 #address-cells = <1>;
1209                                 #size-cells = <0>;
1210                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1211                                 reg = <0x0228c000 0x4000>;
1212                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1213                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1214                                          <&clks IMX6SX_CLK_ECSPI5>;
1215                                 clock-names = "ipg", "per";
1216                                 status = "disabled";
1217                         };
1218
1219                         uart6: serial@022a0000 {
1220                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1221                                 reg = <0x022a0000 0x4000>;
1222                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1223                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1224                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1225                                 clock-names = "ipg", "per";
1226                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1227                                 dma-names = "rx", "tx";
1228                                 status = "disabled";
1229                         };
1230
1231                         pwm5: pwm@022a4000 {
1232                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1233                                 reg = <0x022a4000 0x4000>;
1234                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1235                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1236                                          <&clks IMX6SX_CLK_PWM5>;
1237                                 clock-names = "ipg", "per";
1238                                 #pwm-cells = <2>;
1239                         };
1240
1241                         pwm6: pwm@022a8000 {
1242                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1243                                 reg = <0x022a8000 0x4000>;
1244                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1245                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1246                                          <&clks IMX6SX_CLK_PWM6>;
1247                                 clock-names = "ipg", "per";
1248                                 #pwm-cells = <2>;
1249                         };
1250
1251                         pwm7: pwm@022ac000 {
1252                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1253                                 reg = <0x022ac000 0x4000>;
1254                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1255                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1256                                          <&clks IMX6SX_CLK_PWM7>;
1257                                 clock-names = "ipg", "per";
1258                                 #pwm-cells = <2>;
1259                         };
1260
1261                         pwm8: pwm@0022b0000 {
1262                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1263                                 reg = <0x0022b0000 0x4000>;
1264                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1265                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1266                                          <&clks IMX6SX_CLK_PWM8>;
1267                                 clock-names = "ipg", "per";
1268                                 #pwm-cells = <2>;
1269                         };
1270                 };
1271
1272                 pcie: pcie@0x08000000 {
1273                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1274                         reg = <0x08ffc000 0x4000>; /* DBI */
1275                         #address-cells = <3>;
1276                         #size-cells = <2>;
1277                         device_type = "pci";
1278                                   /* configuration space */
1279                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1280                                   /* downstream I/O */
1281                                   0x81000000 0 0          0x08f80000 0 0x00010000
1282                                   /* non-prefetchable memory */
1283                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1284                         num-lanes = <1>;
1285                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1286                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1287                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1288                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1289                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1290                         clock-names = "pcie_ref_125m", "pcie_axi",
1291                                       "lvds_gate", "display_axi";
1292                         status = "disabled";
1293                 };
1294         };
1295 };