arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                                 198000  975000
  66                         >;
  67                         fsl,soc-operating-points = <
  68                                 /* ARM kHz  SOC uV */
  69                                 996000      1175000
  70                                 792000      1175000
  71                                 396000      1175000
  72                                 198000      1175000
  73                         >;
  74                         clock-latency = <61036>; /* two CLK32 periods */
  75                         clocks = <&clks IMX6SX_CLK_ARM>,
  76                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  77                                  <&clks IMX6SX_CLK_STEP>,
  78                                  <&clks IMX6SX_CLK_PLL1_SW>,
  79                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  80                         clock-names = "arm", "pll2_pfd2_396m", "step",
  81                                       "pll1_sw", "pll1_sys";
  82                         arm-supply = <&reg_arm>;
  83                         soc-supply = <&reg_soc>;
  84                 };
  85         };
  86
  87         intc: interrupt-controller@00a01000 {
  88                 compatible = "arm,cortex-a9-gic";
  89                 #interrupt-cells = <3>;
  90                 interrupt-controller;
  91                 reg = <0x00a01000 0x1000>,
  92                       <0x00a00100 0x100>;
  93         };
  94
  95         clocks {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 ckil: clock@0 {
 100                         compatible = "fixed-clock";
 101                         reg = <0>;
 102                         #clock-cells = <0>;
 103                         clock-frequency = <32768>;
 104                         clock-output-names = "ckil";
 105                 };
 106
 107                 osc: clock@1 {
 108                         compatible = "fixed-clock";
 109                         reg = <1>;
 110                         #clock-cells = <0>;
 111                         clock-frequency = <24000000>;
 112                         clock-output-names = "osc";
 113                 };
 114
 115                 ipp_di0: clock@2 {
 116                         compatible = "fixed-clock";
 117                         reg = <2>;
 118                         #clock-cells = <0>;
 119                         clock-frequency = <0>;
 120                         clock-output-names = "ipp_di0";
 121                 };
 122
 123                 ipp_di1: clock@3 {
 124                         compatible = "fixed-clock";
 125                         reg = <3>;
 126                         #clock-cells = <0>;
 127                         clock-frequency = <0>;
 128                         clock-output-names = "ipp_di1";
 129                 };
 130         };
 131
 132         soc {
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 compatible = "simple-bus";
 136                 interrupt-parent = <&intc>;
 137                 ranges;
 138
 139                 busfreq {
 140                         compatible = "fsl,imx6_busfreq";
 141                         clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
 142                                 <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
 143                                 <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
 144                                 <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
 145                                 <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
 146                                 <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
 147                                 <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
 148                                 <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
 149                                 <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
 150                                 <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>,
 151                                 <&clks IMX6SX_CLK_M4>;
 152                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
 153                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
 154                                 "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", "m4";
 155                         fsl,max_ddr_freq = <400000000>;
 156                 };
 157
 158                 pmu {
 159                         compatible = "arm,cortex-a9-pmu";
 160                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 161                 };
 162
 163                 ocrams: sram@008f8000 {
 164                         compatible = "fsl,lpm-sram";
 165                         reg = <0x008f8000 0x4000>;
 166                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 167                 };
 168
 169                 ocrams_ddr: sram@00900000 {
 170                         compatible = "fsl,ddr-lpm-sram";
 171                         reg = <0x00900000 0x1000>;
 172                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 173                 };
 174
 175                 ocram: sram@00901000 {
 176                         compatible = "mmio-sram";
 177                         reg = <0x00901000 0x1F000>;
 178                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 179                 };
 180
 181                 ocram_mf: sram-mf@00900000 {
 182                         compatible = "fsl,mega-fast-sram";
 183                         reg = <0x00900000 0x20000>;
 184                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 185                 };
 186
 187                 L2: l2-cache@00a02000 {
 188                         compatible = "arm,pl310-cache";
 189                         reg = <0x00a02000 0x1000>;
 190                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 191                         cache-unified;
 192                         cache-level = <2>;
 193                         arm,tag-latency = <4 2 3>;
 194                         arm,data-latency = <4 2 3>;
 195                 };
 196
 197                 gpu: gpu@01800000 {
 198                         compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
 199                         reg = <0x01800000 0x4000>, <0x80000000 0x0>;
 200                         reg-names = "iobase_3d", "phys_baseaddr";
 201                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 202                         interrupt-names = "irq_3d";
 203                         clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
 204                                 <&clks 0>;
 205                         clock-names = "gpu3d_axi_clk", "gpu3d_clk",
 206                                 "gpu3d_shader_clk";
 207                         resets = <&src 0>;
 208                         reset-names = "gpu3d";
 209                         power-domains = <&gpc 1>;
 210                 };
 211
 212                 caam_sm: caam-sm@00100000 {
 213                         compatible = "fsl,imx6q-caam-sm";
 214                         reg = <0x00100000 0x3fff>;
 215                 };
 216
 217                 dma_apbh: dma-apbh@01804000 {
 218                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 219                         reg = <0x01804000 0x2000>;
 220                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 224                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 225                         #dma-cells = <1>;
 226                         dma-channels = <4>;
 227                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 228                 };
 229
 230                 irq_sec_vio: caam_secvio {
 231                         compatible = "fsl,imx6q-caam-secvio";
 232                         interrupts = <0 20 0x04>;
 233                         secvio_src = <0x8000001d>;
 234                 };
 235
 236                 gpmi: gpmi-nand@01806000{
 237                         compatible = "fsl,imx6sx-gpmi-nand";
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 241                         reg-names = "gpmi-nand", "bch";
 242                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 243                         interrupt-names = "bch";
 244                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 245                                  <&clks IMX6SX_CLK_GPMI_APB>,
 246                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 247                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 248                                  <&clks IMX6SX_CLK_PER1_BCH>;
 249                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 250                                       "gpmi_bch_apb", "per1_bch";
 251                         dmas = <&dma_apbh 0>;
 252                         dma-names = "rx-tx";
 253                         status = "disabled";
 254                 };
 255
 256                 aips1: aips-bus@02000000 {
 257                         compatible = "fsl,aips-bus", "simple-bus";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260                         reg = <0x02000000 0x100000>;
 261                         ranges;
 262
 263                         spba-bus@02000000 {
 264                                 compatible = "fsl,spba-bus", "simple-bus";
 265                                 #address-cells = <1>;
 266                                 #size-cells = <1>;
 267                                 reg = <0x02000000 0x40000>;
 268                                 ranges;
 269
 270                                 spdif: spdif@02004000 {
 271                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 272                                         reg = <0x02004000 0x4000>;
 273                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 274                                         dmas = <&sdma 14 18 0>,
 275                                                <&sdma 15 18 0>;
 276                                         dma-names = "rx", "tx";
 277                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 278                                                  <&clks IMX6SX_CLK_OSC>,
 279                                                  <&clks IMX6SX_CLK_SPDIF>,
 280                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 281                                                  <&clks IMX6SX_CLK_IPG>,
 282                                                  <&clks 0>, <&clks 0>,
 283                                                  <&clks IMX6SX_CLK_SPBA>;
 284                                         clock-names = "core", "rxtx0",
 285                                                       "rxtx1", "rxtx2",
 286                                                       "rxtx3", "rxtx4",
 287                                                       "rxtx5", "rxtx6",
 288                                                       "rxtx7", "dma";
 289                                         status = "disabled";
 290                                 };
 291
 292                                 ecspi1: ecspi@02008000 {
 293                                         #address-cells = <1>;
 294                                         #size-cells = <0>;
 295                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 296                                         reg = <0x02008000 0x4000>;
 297                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 298                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 299                                                  <&clks IMX6SX_CLK_ECSPI1>;
 300                                         clock-names = "ipg", "per";
 301                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 302                                         dma-names = "rx", "tx";
 303                                         status = "disabled";
 304                                 };
 305
 306                                 ecspi2: ecspi@0200c000 {
 307                                         #address-cells = <1>;
 308                                         #size-cells = <0>;
 309                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 310                                         reg = <0x0200c000 0x4000>;
 311                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 312                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 313                                                  <&clks IMX6SX_CLK_ECSPI2>;
 314                                         clock-names = "ipg", "per";
 315                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 316                                         dma-names = "rx", "tx";
 317                                         status = "disabled";
 318                                 };
 319
 320                                 ecspi3: ecspi@02010000 {
 321                                         #address-cells = <1>;
 322                                         #size-cells = <0>;
 323                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 324                                         reg = <0x02010000 0x4000>;
 325                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 326                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 327                                                  <&clks IMX6SX_CLK_ECSPI3>;
 328                                         clock-names = "ipg", "per";
 329                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 330                                         dma-names = "rx", "tx";
 331                                         status = "disabled";
 332                                 };
 333
 334                                 ecspi4: ecspi@02014000 {
 335                                         #address-cells = <1>;
 336                                         #size-cells = <0>;
 337                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 338                                         reg = <0x02014000 0x4000>;
 339                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 340                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 341                                                  <&clks IMX6SX_CLK_ECSPI4>;
 342                                         clock-names = "ipg", "per";
 343                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 344                                         dma-names = "rx", "tx";
 345                                         status = "disabled";
 346                                 };
 347
 348                                 uart1: serial@02020000 {
 349                                         compatible = "fsl,imx6sx-uart",
 350                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 351                                         reg = <0x02020000 0x4000>;
 352                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 353                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 354                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 355                                         clock-names = "ipg", "per";
 356                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 357                                         dma-names = "rx", "tx";
 358                                         status = "disabled";
 359                                 };
 360
 361                                 esai: esai@02024000 {
 362                                         compatible = "fsl,imx35-esai";
 363                                         reg = <0x02024000 0x4000>;
 364                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 365                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 366                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 367                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 368                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 369                                                  <&clks IMX6SX_CLK_SPBA>;
 370                                         clock-names = "core", "mem", "extal",
 371                                                       "fsys", "dma";
 372                                         dmas = <&sdma 23 21 0>,
 373                                                <&sdma 24 21 0>;
 374                                         dma-names = "rx", "tx";
 375                                         status = "disabled";
 376                                 };
 377
 378                                 ssi1: ssi@02028000 {
 379                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 380                                         reg = <0x02028000 0x4000>;
 381                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 382                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 383                                                  <&clks IMX6SX_CLK_SSI1>;
 384                                         clock-names = "ipg", "baud";
 385                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 386                                         dma-names = "rx", "tx";
 387                                         status = "disabled";
 388                                 };
 389
 390                                 ssi2: ssi@0202c000 {
 391                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 392                                         reg = <0x0202c000 0x4000>;
 393                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 394                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 395                                                  <&clks IMX6SX_CLK_SSI2>;
 396                                         clock-names = "ipg", "baud";
 397                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 398                                         dma-names = "rx", "tx";
 399                                         status = "disabled";
 400                                 };
 401
 402                                 ssi3: ssi@02030000 {
 403                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 404                                         reg = <0x02030000 0x4000>;
 405                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 406                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 407                                                  <&clks IMX6SX_CLK_SSI3>;
 408                                         clock-names = "ipg", "baud";
 409                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 410                                         dma-names = "rx", "tx";
 411                                         status = "disabled";
 412                                 };
 413
 414                                 asrc: asrc@02034000 {
 415                                         compatible = "fsl,imx53-asrc";
 416                                         reg = <0x02034000 0x4000>;
 417                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 418                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 419                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 420                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 421                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 422                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 423                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 424                                                 <&clks IMX6SX_CLK_SPBA>;
 425                                         clock-names = "mem", "ipg", "asrck_0",
 426                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 427                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 428                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 429                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 430                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 431                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 432                                         dma-names = "rxa", "rxb", "rxc",
 433                                                     "txa", "txb", "txc";
 434                                         fsl,asrc-rate  = <48000>;
 435                                         fsl,asrc-width = <16>;
 436                                         status = "okay";
 437                                 };
 438
 439                                 asrc_p2p: asrc_p2p {
 440                                         compatible = "fsl,imx6q-asrc-p2p";
 441                                         fsl,p2p-rate  = <48000>;
 442                                         fsl,p2p-width = <16>;
 443                                         fsl,asrc-dma-rx-events = <17 18 19>;
 444                                         fsl,asrc-dma-tx-events = <20 21 22>;
 445                                         status = "okay";
 446                                 };
 447                         };
 448
 449                         pwm1: pwm@02080000 {
 450                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 451                                 reg = <0x02080000 0x4000>;
 452                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 454                                          <&clks IMX6SX_CLK_PWM1>;
 455                                 clock-names = "ipg", "per";
 456                                 #pwm-cells = <2>;
 457                         };
 458
 459                         pwm2: pwm@02084000 {
 460                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 461                                 reg = <0x02084000 0x4000>;
 462                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 464                                          <&clks IMX6SX_CLK_PWM2>;
 465                                 clock-names = "ipg", "per";
 466                                 #pwm-cells = <2>;
 467                         };
 468
 469                         pwm3: pwm@02088000 {
 470                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 471                                 reg = <0x02088000 0x4000>;
 472                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 473                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 474                                          <&clks IMX6SX_CLK_PWM3>;
 475                                 clock-names = "ipg", "per";
 476                                 #pwm-cells = <2>;
 477                         };
 478
 479                         pwm4: pwm@0208c000 {
 480                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 481                                 reg = <0x0208c000 0x4000>;
 482                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 484                                          <&clks IMX6SX_CLK_PWM4>;
 485                                 clock-names = "ipg", "per";
 486                                 #pwm-cells = <2>;
 487                         };
 488
 489                         flexcan1: can@02090000 {
 490                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 491                                 reg = <0x02090000 0x4000>;
 492                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 494                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 495                                 clock-names = "ipg", "per";
 496                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 497                                 status = "disabled";
 498                         };
 499
 500                         flexcan2: can@02094000 {
 501                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 502                                 reg = <0x02094000 0x4000>;
 503                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 505                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 506                                 clock-names = "ipg", "per";
 507                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 508                                 status = "disabled";
 509                         };
 510
 511                         gpt: gpt@02098000 {
 512                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 513                                 reg = <0x02098000 0x4000>;
 514                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 515                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 516                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 517                                 clock-names = "ipg", "per";
 518                         };
 519
 520                         gpio1: gpio@0209c000 {
 521                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 522                                 reg = <0x0209c000 0x4000>;
 523                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 524                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 525                                 gpio-controller;
 526                                 #gpio-cells = <2>;
 527                                 interrupt-controller;
 528                                 #interrupt-cells = <2>;
 529                         };
 530
 531                         gpio2: gpio@020a0000 {
 532                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 533                                 reg = <0x020a0000 0x4000>;
 534                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                         };
 541
 542                         gpio3: gpio@020a4000 {
 543                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 544                                 reg = <0x020a4000 0x4000>;
 545                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 547                                 gpio-controller;
 548                                 #gpio-cells = <2>;
 549                                 interrupt-controller;
 550                                 #interrupt-cells = <2>;
 551                         };
 552
 553                         gpio4: gpio@020a8000 {
 554                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 555                                 reg = <0x020a8000 0x4000>;
 556                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 557                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 558                                 gpio-controller;
 559                                 #gpio-cells = <2>;
 560                                 interrupt-controller;
 561                                 #interrupt-cells = <2>;
 562                         };
 563
 564                         gpio5: gpio@020ac000 {
 565                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 566                                 reg = <0x020ac000 0x4000>;
 567                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 568                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 569                                 gpio-controller;
 570                                 #gpio-cells = <2>;
 571                                 interrupt-controller;
 572                                 #interrupt-cells = <2>;
 573                         };
 574
 575                         gpio6: gpio@020b0000 {
 576                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 577                                 reg = <0x020b0000 0x4000>;
 578                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 579                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 580                                 gpio-controller;
 581                                 #gpio-cells = <2>;
 582                                 interrupt-controller;
 583                                 #interrupt-cells = <2>;
 584                         };
 585
 586                         gpio7: gpio@020b4000 {
 587                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 588                                 reg = <0x020b4000 0x4000>;
 589                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 591                                 gpio-controller;
 592                                 #gpio-cells = <2>;
 593                                 interrupt-controller;
 594                                 #interrupt-cells = <2>;
 595                         };
 596
 597                         kpp: kpp@020b8000 {
 598                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 599                                 reg = <0x020b8000 0x4000>;
 600                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 601                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 602                                 status = "disabled";
 603                         };
 604
 605                         wdog1: wdog@020bc000 {
 606                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 607                                 reg = <0x020bc000 0x4000>;
 608                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 609                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 610                         };
 611
 612                         wdog2: wdog@020c0000 {
 613                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 614                                 reg = <0x020c0000 0x4000>;
 615                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 617                                 status = "disabled";
 618                         };
 619
 620                         clks: ccm@020c4000 {
 621                                 compatible = "fsl,imx6sx-ccm";
 622                                 reg = <0x020c4000 0x4000>;
 623                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 624                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 625                                 #clock-cells = <1>;
 626                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 627                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 628                         };
 629
 630                         anatop: anatop@020c8000 {
 631                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 632                                              "syscon", "simple-bus";
 633                                 reg = <0x020c8000 0x1000>;
 634                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 635                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 636                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 637
 638                                 regulator-1p1@110 {
 639                                         compatible = "fsl,anatop-regulator";
 640                                         regulator-name = "vdd1p1";
 641                                         regulator-min-microvolt = <800000>;
 642                                         regulator-max-microvolt = <1375000>;
 643                                         regulator-always-on;
 644                                         anatop-reg-offset = <0x110>;
 645                                         anatop-vol-bit-shift = <8>;
 646                                         anatop-vol-bit-width = <5>;
 647                                         anatop-min-bit-val = <4>;
 648                                         anatop-min-voltage = <800000>;
 649                                         anatop-max-voltage = <1375000>;
 650                                 };
 651
 652                                 regulator-3p0@120 {
 653                                         compatible = "fsl,anatop-regulator";
 654                                         regulator-name = "vdd3p0";
 655                                         regulator-min-microvolt = <2800000>;
 656                                         regulator-max-microvolt = <3150000>;
 657                                         regulator-always-on;
 658                                         anatop-reg-offset = <0x120>;
 659                                         anatop-vol-bit-shift = <8>;
 660                                         anatop-vol-bit-width = <5>;
 661                                         anatop-min-bit-val = <0>;
 662                                         anatop-min-voltage = <2625000>;
 663                                         anatop-max-voltage = <3400000>;
 664                                 };
 665
 666                                 regulator-2p5@130 {
 667                                         compatible = "fsl,anatop-regulator";
 668                                         regulator-name = "vdd2p5";
 669                                         regulator-min-microvolt = <2100000>;
 670                                         regulator-max-microvolt = <2875000>;
 671                                         regulator-always-on;
 672                                         anatop-reg-offset = <0x130>;
 673                                         anatop-vol-bit-shift = <8>;
 674                                         anatop-vol-bit-width = <5>;
 675                                         anatop-min-bit-val = <0>;
 676                                         anatop-min-voltage = <2100000>;
 677                                         anatop-max-voltage = <2875000>;
 678                                 };
 679
 680                                 reg_arm: regulator-vddcore@140 {
 681                                         compatible = "fsl,anatop-regulator";
 682                                         regulator-name = "cpu";
 683                                         regulator-min-microvolt = <725000>;
 684                                         regulator-max-microvolt = <1450000>;
 685                                         regulator-always-on;
 686                                         anatop-reg-offset = <0x140>;
 687                                         anatop-vol-bit-shift = <0>;
 688                                         anatop-vol-bit-width = <5>;
 689                                         anatop-delay-reg-offset = <0x170>;
 690                                         anatop-delay-bit-shift = <24>;
 691                                         anatop-delay-bit-width = <2>;
 692                                         anatop-min-bit-val = <1>;
 693                                         anatop-min-voltage = <725000>;
 694                                         anatop-max-voltage = <1450000>;
 695                                 };
 696
 697                                 reg_pcie_phy: regulator-vddpcie-phy@140 {
 698                                         compatible = "fsl,anatop-regulator";
 699                                         regulator-name = "vddpcie-phy";
 700                                         regulator-min-microvolt = <725000>;
 701                                         regulator-max-microvolt = <1450000>;
 702                                         anatop-reg-offset = <0x140>;
 703                                         anatop-vol-bit-shift = <9>;
 704                                         anatop-vol-bit-width = <5>;
 705                                         anatop-delay-reg-offset = <0x170>;
 706                                         anatop-delay-bit-shift = <26>;
 707                                         anatop-delay-bit-width = <2>;
 708                                         anatop-min-bit-val = <1>;
 709                                         anatop-min-voltage = <725000>;
 710                                         anatop-max-voltage = <1450000>;
 711                                 };
 712
 713                                 reg_soc: regulator-vddsoc@140 {
 714                                         compatible = "fsl,anatop-regulator";
 715                                         regulator-name = "vddsoc";
 716                                         regulator-min-microvolt = <725000>;
 717                                         regulator-max-microvolt = <1450000>;
 718                                         regulator-always-on;
 719                                         anatop-reg-offset = <0x140>;
 720                                         anatop-vol-bit-shift = <18>;
 721                                         anatop-vol-bit-width = <5>;
 722                                         anatop-delay-reg-offset = <0x170>;
 723                                         anatop-delay-bit-shift = <28>;
 724                                         anatop-delay-bit-width = <2>;
 725                                         anatop-min-bit-val = <1>;
 726                                         anatop-min-voltage = <725000>;
 727                                         anatop-max-voltage = <1450000>;
 728                                 };
 729                         };
 730
 731                         tempmon: tempmon {
 732                                 compatible = "fsl,imx6sx-tempmon";
 733                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 734                                 fsl,tempmon = <&anatop>;
 735                                 fsl,tempmon-data = <&ocotp>;
 736                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 737                         };
 738
 739                         usbphy1: usbphy@020c9000 {
 740                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 741                                 reg = <0x020c9000 0x1000>;
 742                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 744                                 fsl,anatop = <&anatop>;
 745                         };
 746
 747                         usbphy2: usbphy@020ca000 {
 748                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 749                                 reg = <0x020ca000 0x1000>;
 750                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 751                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 752                                 fsl,anatop = <&anatop>;
 753                         };
 754
 755                         mqs: mqs {
 756                                 compatible = "fsl,imx6sx-mqs";
 757                                 gpr = <&gpr>;
 758                                 status = "disabled";
 759                         };
 760
 761                         caam_snvs: caam-snvs@020cc000 {
 762                                 compatible = "fsl,imx6q-caam-snvs";
 763                                 reg = <0x020cc000 0x4000>;
 764                         };
 765
 766                         snvs: snvs@020cc000 {
 767                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 768                                 #address-cells = <1>;
 769                                 #size-cells = <1>;
 770                                 ranges = <0 0x020cc000 0x4000>;
 771
 772                                 snvs-rtc-lp@34 {
 773                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 774                                         reg = <0x34 0x58>;
 775                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 776                                 };
 777                         };
 778
 779                         snvs-pwrkey@0x020cc000 {
 780                                 compatible = "fsl,imx6sx-snvs-pwrkey";
 781                                 reg = <0x020cc000 0x4000>;
 782                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 783                                 fsl,keycode = <116>; /* KEY_POWER */
 784                                 fsl,wakeup;
 785                         };
 786
 787                         epit1: epit@020d0000 {
 788                                 reg = <0x020d0000 0x4000>;
 789                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 790                         };
 791
 792                         epit2: epit@020d4000 {
 793                                 reg = <0x020d4000 0x4000>;
 794                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 795                         };
 796
 797                         src: src@020d8000 {
 798                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 799                                 reg = <0x020d8000 0x4000>;
 800                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 801                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 802                                 #reset-cells = <1>;
 803                         };
 804
 805                         gpc: gpc@020dc000 {
 806                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 807                                 reg = <0x020dc000 0x4000>;
 808                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 809                                 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
 810                                 clocks = <&clks IMX6SX_CLK_GPU>;
 811                                 pcie-phy-supply = <&reg_pcie_phy>;
 812                                 #power-domain-cells = <1>;
 813                         };
 814
 815                         iomuxc: iomuxc@020e0000 {
 816                                 compatible = "fsl,imx6sx-iomuxc";
 817                                 reg = <0x020e0000 0x4000>;
 818                         };
 819
 820                         gpr: iomuxc-gpr@020e4000 {
 821                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 822                                 reg = <0x020e4000 0x4000>;
 823                         };
 824
 825                         ldb: ldb@020e0014 {
 826                                 #address-cells = <1>;
 827                                 #size-cells = <0>;
 828                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 829                                 gpr = <&gpr>;
 830                                 status = "disabled";
 831
 832                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 833                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 834                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 835                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 836                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 837                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 838                                 clock-names = "ldb_di0",
 839                                               "di0_sel",
 840                                               "di1_sel",
 841                                               "ldb_di0_div_3_5",
 842                                               "ldb_di0_div_7",
 843                                               "ldb_di0_div_sel";
 844
 845                                 lvds-channel@0 {
 846                                         reg = <0>;
 847                                         status = "disabled";
 848                                 };
 849                         };
 850
 851                         sdma: sdma@020ec000 {
 852                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 853                                 reg = <0x020ec000 0x4000>;
 854                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 856                                          <&clks IMX6SX_CLK_SDMA>;
 857                                 clock-names = "ipg", "ahb";
 858                                 #dma-cells = <3>;
 859                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 860                         };
 861                 };
 862
 863                 aips2: aips-bus@02100000 {
 864                         compatible = "fsl,aips-bus", "simple-bus";
 865                         #address-cells = <1>;
 866                         #size-cells = <1>;
 867                         reg = <0x02100000 0x100000>;
 868                         ranges;
 869
 870                         crypto: caam@2100000 {
 871                                 compatible = "fsl,sec-v4.0";
 872                                 #address-cells = <1>;
 873                                 #size-cells = <1>;
 874                                 reg = <0x2100000 0x40000>;
 875                                 ranges = <0 0x2100000 0x40000>;
 876                                 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
 877                                 clocks = <&clks 134>, <&clks 135>, <&clks 136> ,<&clks 213>;
 878                                 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
 879
 880                                 sec_jr0: jr0@1000 {
 881                                         compatible = "fsl,sec-v4.0-job-ring";
 882                                         reg = <0x1000 0x1000>;
 883                                         interrupt-parent = <&intc>;
 884                                         interrupts = <0 105 0x4>;
 885                                 };
 886
 887                                 sec_jr1: jr1@2000 {
 888                                         compatible = "fsl,sec-v4.0-job-ring";
 889                                         reg = <0x2000 0x1000>;
 890                                         interrupt-parent = <&intc>;
 891                                         interrupts = <0 106 0x4>;
 892                                 };
 893                         };
 894
 895                         usbotg1: usb@02184000 {
 896                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 897                                 reg = <0x02184000 0x200>;
 898                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 899                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 900                                 fsl,usbphy = <&usbphy1>;
 901                                 fsl,usbmisc = <&usbmisc 0>;
 902                                 fsl,anatop = <&anatop>;
 903                                 status = "disabled";
 904                         };
 905
 906                         usbotg2: usb@02184200 {
 907                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 908                                 reg = <0x02184200 0x200>;
 909                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 910                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 911                                 fsl,usbphy = <&usbphy2>;
 912                                 fsl,usbmisc = <&usbmisc 1>;
 913                                 status = "disabled";
 914                         };
 915
 916                         usbh: usb@02184400 {
 917                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 918                                 reg = <0x02184400 0x200>;
 919                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 921                                 fsl,usbmisc = <&usbmisc 2>;
 922                                 phy_type = "hsic";
 923                                 fsl,anatop = <&anatop>;
 924                                 status = "disabled";
 925                         };
 926
 927                         usbmisc: usbmisc@02184800 {
 928                                 #index-cells = <1>;
 929                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 930                                 reg = <0x02184800 0x200>;
 931                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 932                         };
 933
 934                         fec1: ethernet@02188000 {
 935                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 936                                 reg = <0x02188000 0x4000>;
 937                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 938                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&clks IMX6SX_CLK_ENET>,
 940                                          <&clks IMX6SX_CLK_ENET_AHB>,
 941                                          <&clks IMX6SX_CLK_ENET_PTP>,
 942                                          <&clks IMX6SX_CLK_ENET_REF>,
 943                                          <&clks IMX6SX_CLK_ENET_PTP>;
 944                                 clock-names = "ipg", "ahb", "ptp",
 945                                               "enet_clk_ref", "enet_out";
 946                                 fsl,num-tx-queues=<3>;
 947                                 fsl,num-rx-queues=<3>;
 948                                 status = "disabled";
 949                         };
 950
 951                         mlb: mlb@0218c000 {
 952                                 compatible = "fsl,imx6sx-mlb50";
 953                                 reg = <0x0218c000 0x4000>;
 954                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 955                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 956                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 957                                 clocks = <&clks IMX6SX_CLK_MLB>;
 958                                 clock-names = "mlb";
 959                                 iram = <&ocram>;
 960                                 status = "disabled";
 961                         };
 962
 963                         usdhc1: usdhc@02190000 {
 964                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 965                                 reg = <0x02190000 0x4000>;
 966                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 968                                          <&clks IMX6SX_CLK_USDHC1>,
 969                                          <&clks IMX6SX_CLK_USDHC1>;
 970                                 clock-names = "ipg", "ahb", "per";
 971                                 bus-width = <4>;
 972                                 status = "disabled";
 973                         };
 974
 975                         usdhc2: usdhc@02194000 {
 976                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 977                                 reg = <0x02194000 0x4000>;
 978                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 979                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 980                                          <&clks IMX6SX_CLK_USDHC2>,
 981                                          <&clks IMX6SX_CLK_USDHC2>;
 982                                 clock-names = "ipg", "ahb", "per";
 983                                 bus-width = <4>;
 984                                 status = "disabled";
 985                         };
 986
 987                         usdhc3: usdhc@02198000 {
 988                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 989                                 reg = <0x02198000 0x4000>;
 990                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 991                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 992                                          <&clks IMX6SX_CLK_USDHC3>,
 993                                          <&clks IMX6SX_CLK_USDHC3>;
 994                                 clock-names = "ipg", "ahb", "per";
 995                                 bus-width = <4>;
 996                                 status = "disabled";
 997                         };
 998
 999                         usdhc4: usdhc@0219c000 {
1000                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1001                                 reg = <0x0219c000 0x4000>;
1002                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1003                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
1004                                          <&clks IMX6SX_CLK_USDHC4>,
1005                                          <&clks IMX6SX_CLK_USDHC4>;
1006                                 clock-names = "ipg", "ahb", "per";
1007                                 bus-width = <4>;
1008                                 status = "disabled";
1009                         };
1010
1011                         i2c1: i2c@021a0000 {
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1015                                 reg = <0x021a0000 0x4000>;
1016                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clks IMX6SX_CLK_I2C1>;
1018                                 status = "disabled";
1019                         };
1020
1021                         i2c2: i2c@021a4000 {
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1025                                 reg = <0x021a4000 0x4000>;
1026                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks IMX6SX_CLK_I2C2>;
1028                                 status = "disabled";
1029                         };
1030
1031                         i2c3: i2c@021a8000 {
1032                                 #address-cells = <1>;
1033                                 #size-cells = <0>;
1034                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1035                                 reg = <0x021a8000 0x4000>;
1036                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1037                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1038                                 status = "disabled";
1039                         };
1040
1041                         mmdc: mmdc@021b0000 {
1042                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1043                                 reg = <0x021b0000 0x4000>;
1044                         };
1045
1046                         fec2: ethernet@021b4000 {
1047                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1048                                 reg = <0x021b4000 0x4000>;
1049                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1050                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1051                                 clocks = <&clks IMX6SX_CLK_ENET>,
1052                                          <&clks IMX6SX_CLK_ENET_AHB>,
1053                                          <&clks IMX6SX_CLK_ENET_PTP>,
1054                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1055                                          <&clks IMX6SX_CLK_ENET_PTP>;
1056                                 clock-names = "ipg", "ahb", "ptp",
1057                                               "enet_clk_ref", "enet_out";
1058                                 status = "disabled";
1059                         };
1060
1061                         weim: weim@021b8000 {
1062                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1063                                 reg = <0x021b8000 0x4000>;
1064                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1066                         };
1067
1068                         ocotp: ocotp-ctrl@021bc000 {
1069                                 compatible = "syscon";
1070                                 reg = <0x021bc000 0x4000>;
1071                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1072                         };
1073
1074                         ocotp-fuse@021bc000 {
1075                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
1076                                 reg = <0x021bc000 0x4000>;
1077                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1078                         };
1079
1080                         romcp@021ac000 {
1081                                 compatible = "fsl,imx6sx-romcp", "syscon";
1082                                 reg = <0x021ac000 0x4000>;
1083                         };
1084
1085                         sai1: sai@021d4000 {
1086                                 compatible = "fsl,imx6sx-sai";
1087                                 reg = <0x021d4000 0x4000>;
1088                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1089                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1090                                          <&clks IMX6SX_CLK_SAI1>,
1091                                          <&clks 0>, <&clks 0>;
1092                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1093                                 dma-names = "rx", "tx";
1094                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
1095                                 dma-source = <&gpr 0 15 0 16>;
1096                                 status = "disabled";
1097                         };
1098
1099                         audmux: audmux@021d8000 {
1100                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1101                                 reg = <0x021d8000 0x4000>;
1102                                 status = "disabled";
1103                         };
1104
1105                         sai2: sai@021dc000 {
1106                                 compatible = "fsl,imx6sx-sai";
1107                                 reg = <0x021dc000 0x4000>;
1108                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1109                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1110                                          <&clks IMX6SX_CLK_SAI2>,
1111                                          <&clks 0>, <&clks 0>;
1112                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1113                                 dma-names = "rx", "tx";
1114                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1115                                 dma-source = <&gpr 0 17 0 18>;
1116                                 status = "disabled";
1117                         };
1118
1119                         qspi1: qspi@021e0000 {
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 compatible = "fsl,imx6sx-qspi";
1123                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1124                                 reg-names = "QuadSPI", "QuadSPI-memory";
1125                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1126                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1127                                          <&clks IMX6SX_CLK_QSPI1>;
1128                                 clock-names = "qspi_en", "qspi";
1129                                 status = "disabled";
1130                         };
1131
1132                         qspi2: qspi@021e4000 {
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135                                 compatible = "fsl,imx6sx-qspi";
1136                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1137                                 reg-names = "QuadSPI", "QuadSPI-memory";
1138                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1139                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1140                                          <&clks IMX6SX_CLK_QSPI2>;
1141                                 clock-names = "qspi_en", "qspi";
1142                                 status = "disabled";
1143                         };
1144
1145                         qspi_m4: qspi-m4 {
1146                                 compatible = "fsl,imx6sx-qspi-m4-restore";
1147                                 reg = <0x021e4000 0x4000>;
1148                                 status = "disabled";
1149                         };
1150
1151                         uart2: serial@021e8000 {
1152                                 compatible = "fsl,imx6sx-uart",
1153                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1154                                 reg = <0x021e8000 0x4000>;
1155                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1156                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1157                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1158                                 clock-names = "ipg", "per";
1159                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1160                                 dma-names = "rx", "tx";
1161                                 status = "disabled";
1162                         };
1163
1164                         uart3: serial@021ec000 {
1165                                 compatible = "fsl,imx6sx-uart",
1166                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1167                                 reg = <0x021ec000 0x4000>;
1168                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1169                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1170                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1171                                 clock-names = "ipg", "per";
1172                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1173                                 dma-names = "rx", "tx";
1174                                 status = "disabled";
1175                         };
1176
1177                         uart4: serial@021f0000 {
1178                                 compatible = "fsl,imx6sx-uart",
1179                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1180                                 reg = <0x021f0000 0x4000>;
1181                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1182                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1183                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1184                                 clock-names = "ipg", "per";
1185                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1186                                 dma-names = "rx", "tx";
1187                                 status = "disabled";
1188                         };
1189
1190                         uart5: serial@021f4000 {
1191                                 compatible = "fsl,imx6sx-uart",
1192                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1193                                 reg = <0x021f4000 0x4000>;
1194                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1195                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1196                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1197                                 clock-names = "ipg", "per";
1198                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1199                                 dma-names = "rx", "tx";
1200                                 status = "disabled";
1201                         };
1202
1203                         i2c4: i2c@021f8000 {
1204                                 #address-cells = <1>;
1205                                 #size-cells = <0>;
1206                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1207                                 reg = <0x021f8000 0x4000>;
1208                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1209                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1210                                 status = "disabled";
1211                         };
1212                 };
1213
1214                 aips3: aips-bus@02200000 {
1215                         compatible = "fsl,aips-bus", "simple-bus";
1216                         #address-cells = <1>;
1217                         #size-cells = <1>;
1218                         reg = <0x02200000 0x100000>;
1219                         ranges;
1220
1221                         spba-bus@02200000 {
1222                                 compatible = "fsl,spba-bus", "simple-bus";
1223                                 #address-cells = <1>;
1224                                 #size-cells = <1>;
1225                                 reg = <0x02240000 0x40000>;
1226                                 ranges;
1227
1228                                 dcic1: dcic@0220c000 {
1229                                         compatible = "fsl,imx6sx-dcic";
1230                                         reg = <0x0220c000 0x4000>;
1231                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1232                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1233                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1234                                         clock-names = "dcic", "disp-axi";
1235                                         gpr = <&gpr>;
1236                                         status = "disabled";
1237                                 };
1238
1239                                 dcic2: dcic@02210000 {
1240                                         compatible = "fsl,imx6sx-dcic";
1241                                         reg = <0x02210000 0x4000>;
1242                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1243                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1244                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1245                                         clock-names = "dcic", "disp-axi";
1246                                         gpr = <&gpr>;
1247                                         status = "disabled";
1248                                 };
1249
1250                                 csi1: csi@02214000 {
1251                                         compatible = "fsl,imx6s-csi";
1252                                         reg = <0x02214000 0x4000>;
1253                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1254                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1255                                                  <&clks IMX6SX_CLK_CSI>,
1256                                                  <&clks IMX6SX_CLK_DCIC1>;
1257                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1258                                         status = "disabled";
1259                                 };
1260
1261                                 pxp: pxp@02218000 {
1262                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1263                                         reg = <0x02218000 0x4000>;
1264                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1265                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1266                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1267                                         clock-names = "pxp-axi", "disp-axi";
1268                                         status = "disabled";
1269                                 };
1270
1271                                 csi2: csi@0221c000 {
1272                                         compatible = "fsl,imx6s-csi";
1273                                         reg = <0x0221c000 0x4000>;
1274                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1275                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1276                                                  <&clks IMX6SX_CLK_CSI>,
1277                                                  <&clks IMX6SX_CLK_DCIC2>;
1278                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1279                                         status = "disabled";
1280                                 };
1281
1282                                 lcdif1: lcdif@02220000 {
1283                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1284                                         reg = <0x02220000 0x4000>;
1285                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1286                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1287                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1288                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1289                                         clock-names = "pix", "axi", "disp_axi";
1290                                         status = "disabled";
1291                                 };
1292
1293                                 lcdif2: lcdif@02224000 {
1294                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1295                                         reg = <0x02224000 0x4000>;
1296                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1297                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1298                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1299                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1300                                         clock-names = "pix", "axi", "disp_axi";
1301                                         status = "disabled";
1302                                 };
1303
1304                                 vadc: vadc@02228000 {
1305                                         compatible = "fsl,imx6sx-vadc";
1306                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1307                                         reg-names = "vadc-vafe", "vadc-vdec";
1308                                         clocks = <&clks IMX6SX_CLK_VADC>,
1309                                                  <&clks IMX6SX_CLK_CSI>;
1310                                         clock-names = "vadc", "csi";
1311                                         gpr = <&gpr>;
1312                                         status = "disabled";
1313                                 };
1314                         };
1315
1316                         adc1: adc@02280000 {
1317                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1318                                 reg = <0x02280000 0x4000>;
1319                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1320                                 clocks = <&clks IMX6SX_CLK_IPG>;
1321                                 num-channels = <4>;
1322                                 clock-names = "adc";
1323                                 status = "disabled";
1324                         };
1325
1326                         adc2: adc@02284000 {
1327                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1328                                 reg = <0x02284000 0x4000>;
1329                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1330                                 clocks = <&clks IMX6SX_CLK_IPG>;
1331                                 num-channels = <4>;
1332                                 clock-names = "adc";
1333                                 status = "disabled";
1334                         };
1335
1336                         wdog3: wdog@02288000 {
1337                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1338                                 reg = <0x02288000 0x4000>;
1339                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1340                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1341                                 status = "disabled";
1342                         };
1343
1344                         ecspi5: ecspi@0228c000 {
1345                                 #address-cells = <1>;
1346                                 #size-cells = <0>;
1347                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1348                                 reg = <0x0228c000 0x4000>;
1349                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1350                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1351                                          <&clks IMX6SX_CLK_ECSPI5>;
1352                                 clock-names = "ipg", "per";
1353                                 status = "disabled";
1354                         };
1355
1356                         sema4: sema4@02290000 { /* sema4 */
1357                                 compatible = "fsl,imx6sx-sema4";
1358                                 reg = <0x02290000 0x4000>;
1359                                 interrupts = <0 116 0x04>;
1360                                 status = "okay";
1361                         };
1362
1363                         mu: mu@02294000 { /* mu */
1364                                 compatible = "fsl,imx6sx-mu";
1365                                 reg = <0x02294000 0x4000>;
1366                                 interrupts = <0 90 0x04>;
1367                                 status = "okay";
1368                         };
1369
1370                         mcctest: mcctest{
1371                                 compatible = "fsl,imx6sx-mcc-test";
1372                                 status = "disabled";
1373                         };
1374
1375                         mcctty: mcctty{
1376                                 compatible = "fsl,imx6sx-mcc-tty";
1377                                 status = "disabled";
1378                         };
1379
1380                         uart6: serial@022a0000 {
1381                                 compatible = "fsl,imx6sx-uart",
1382                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1383                                 reg = <0x022a0000 0x4000>;
1384                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1385                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1386                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1387                                 clock-names = "ipg", "per";
1388                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1389                                 dma-names = "rx", "tx";
1390                                 status = "disabled";
1391                         };
1392
1393                         pwm5: pwm@022a4000 {
1394                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1395                                 reg = <0x022a4000 0x4000>;
1396                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1397                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1398                                          <&clks IMX6SX_CLK_PWM5>;
1399                                 clock-names = "ipg", "per";
1400                                 #pwm-cells = <2>;
1401                         };
1402
1403                         pwm6: pwm@022a8000 {
1404                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1405                                 reg = <0x022a8000 0x4000>;
1406                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1407                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1408                                          <&clks IMX6SX_CLK_PWM6>;
1409                                 clock-names = "ipg", "per";
1410                                 #pwm-cells = <2>;
1411                         };
1412
1413                         pwm7: pwm@022ac000 {
1414                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1415                                 reg = <0x022ac000 0x4000>;
1416                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1417                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1418                                          <&clks IMX6SX_CLK_PWM7>;
1419                                 clock-names = "ipg", "per";
1420                                 #pwm-cells = <2>;
1421                         };
1422
1423                         pwm8: pwm@0022b0000 {
1424                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1425                                 reg = <0x0022b0000 0x4000>;
1426                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1427                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1428                                          <&clks IMX6SX_CLK_PWM8>;
1429                                 clock-names = "ipg", "per";
1430                                 #pwm-cells = <2>;
1431                         };
1432                 };
1433
1434                 pcie: pcie@0x08000000 {
1435                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1436                         reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
1437                         reg-names = "dbi", "config";
1438                         #address-cells = <3>;
1439                         #size-cells = <2>;
1440                         device_type = "pci";
1441                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1442                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1443                         num-lanes = <1>;
1444                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1445                         interrupt-names = "msi";
1446                         #interrupt-cells = <1>;
1447                         interrupt-map-mask = <0 0 0 0x7>;
1448                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1449                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1450                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1451                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1452                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1453                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1454                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1455                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1456                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1457                         pcie-phy-supply = <&reg_pcie_phy>;
1458                         status = "disabled";
1459                 };
1460         };
1461 };