arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                         >;
  66                         fsl,soc-operating-points = <
  67                                 /* ARM kHz  SOC uV */
  68                                 996000      1175000
  69                                 792000      1175000
  70                                 396000      1175000
  71                         >;
  72                         clock-latency = <61036>; /* two CLK32 periods */
  73                         clocks = <&clks IMX6SX_CLK_ARM>,
  74                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6SX_CLK_STEP>,
  76                                  <&clks IMX6SX_CLK_PLL1_SW>,
  77                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  78                         clock-names = "arm", "pll2_pfd2_396m", "step",
  79                                       "pll1_sw", "pll1_sys";
  80                         arm-supply = <&reg_arm>;
  81                         soc-supply = <&reg_soc>;
  82                 };
  83         };
  84
  85         intc: interrupt-controller@00a01000 {
  86                 compatible = "arm,cortex-a9-gic";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x00a01000 0x1000>,
  90                       <0x00a00100 0x100>;
  91         };
  92
  93         clocks {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ckil: clock@0 {
  98                         compatible = "fixed-clock";
  99                         reg = <0>;
 100                         #clock-cells = <0>;
 101                         clock-frequency = <32768>;
 102                         clock-output-names = "ckil";
 103                 };
 104
 105                 osc: clock@1 {
 106                         compatible = "fixed-clock";
 107                         reg = <1>;
 108                         #clock-cells = <0>;
 109                         clock-frequency = <24000000>;
 110                         clock-output-names = "osc";
 111                 };
 112
 113                 ipp_di0: clock@2 {
 114                         compatible = "fixed-clock";
 115                         reg = <2>;
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                         clock-output-names = "ipp_di0";
 119                 };
 120
 121                 ipp_di1: clock@3 {
 122                         compatible = "fixed-clock";
 123                         reg = <3>;
 124                         #clock-cells = <0>;
 125                         clock-frequency = <0>;
 126                         clock-output-names = "ipp_di1";
 127                 };
 128         };
 129
 130         soc {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "simple-bus";
 134                 interrupt-parent = <&intc>;
 135                 ranges;
 136
 137                 busfreq {
 138                         compatible = "fsl,imx6_busfreq";
 139                         clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
 140                                 <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
 141                                 <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
 142                                 <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
 143                                 <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
 144                                 <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
 145                                 <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
 146                                 <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
 147                                 <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
 148                                 <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>,
 149                                 <&clks IMX6SX_CLK_M4>;
 150                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
 151                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
 152                                 "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", "m4";
 153                         fsl,max_ddr_freq = <400000000>;
 154                 };
 155
 156                 pmu {
 157                         compatible = "arm,cortex-a9-pmu";
 158                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 ocrams: sram@008f8000 {
 162                         compatible = "fsl,lpm-sram";
 163                         reg = <0x008f8000 0x4000>;
 164                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 165                 };
 166
 167                 ocrams_ddr: sram@00900000 {
 168                         compatible = "fsl,ddr-lpm-sram";
 169                         reg = <0x00900000 0x1000>;
 170                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 171                 };
 172
 173                 ocram: sram@00901000 {
 174                         compatible = "mmio-sram";
 175                         reg = <0x00901000 0x1F000>;
 176                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 177                 };
 178
 179                 ocram_mf: sram-mf@00900000 {
 180                         compatible = "fsl,mega-fast-sram";
 181                         reg = <0x00900000 0x20000>;
 182                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 183                 };
 184
 185                 L2: l2-cache@00a02000 {
 186                         compatible = "arm,pl310-cache";
 187                         reg = <0x00a02000 0x1000>;
 188                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 189                         cache-unified;
 190                         cache-level = <2>;
 191                         arm,tag-latency = <4 2 3>;
 192                         arm,data-latency = <4 2 3>;
 193                 };
 194
 195                 gpu: gpu@01800000 {
 196                         compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
 197                         reg = <0x01800000 0x4000>, <0x80000000 0x0>;
 198                         reg-names = "iobase_3d", "phys_baseaddr";
 199                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 200                         interrupt-names = "irq_3d";
 201                         clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
 202                                 <&clks 0>;
 203                         clock-names = "gpu3d_axi_clk", "gpu3d_clk",
 204                                 "gpu3d_shader_clk";
 205                         resets = <&src 0>;
 206                         reset-names = "gpu3d";
 207                         power-domains = <&gpc 1>;
 208                 };
 209
 210                 dma_apbh: dma-apbh@01804000 {
 211                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 212                         reg = <0x01804000 0x2000>;
 213                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 217                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 218                         #dma-cells = <1>;
 219                         dma-channels = <4>;
 220                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 221                 };
 222
 223                 gpmi: gpmi-nand@01806000{
 224                         compatible = "fsl,imx6sx-gpmi-nand";
 225                         #address-cells = <1>;
 226                         #size-cells = <1>;
 227                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 228                         reg-names = "gpmi-nand", "bch";
 229                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 230                         interrupt-names = "bch";
 231                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 232                                  <&clks IMX6SX_CLK_GPMI_APB>,
 233                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 234                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 235                                  <&clks IMX6SX_CLK_PER1_BCH>;
 236                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 237                                       "gpmi_bch_apb", "per1_bch";
 238                         dmas = <&dma_apbh 0>;
 239                         dma-names = "rx-tx";
 240                         status = "disabled";
 241                 };
 242
 243                 aips1: aips-bus@02000000 {
 244                         compatible = "fsl,aips-bus", "simple-bus";
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         reg = <0x02000000 0x100000>;
 248                         ranges;
 249
 250                         spba-bus@02000000 {
 251                                 compatible = "fsl,spba-bus", "simple-bus";
 252                                 #address-cells = <1>;
 253                                 #size-cells = <1>;
 254                                 reg = <0x02000000 0x40000>;
 255                                 ranges;
 256
 257                                 spdif: spdif@02004000 {
 258                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 259                                         reg = <0x02004000 0x4000>;
 260                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 261                                         dmas = <&sdma 14 18 0>,
 262                                                <&sdma 15 18 0>;
 263                                         dma-names = "rx", "tx";
 264                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 265                                                  <&clks IMX6SX_CLK_OSC>,
 266                                                  <&clks IMX6SX_CLK_SPDIF>,
 267                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 268                                                  <&clks IMX6SX_CLK_IPG>,
 269                                                  <&clks 0>, <&clks 0>,
 270                                                  <&clks IMX6SX_CLK_SPBA>;
 271                                         clock-names = "core", "rxtx0",
 272                                                       "rxtx1", "rxtx2",
 273                                                       "rxtx3", "rxtx4",
 274                                                       "rxtx5", "rxtx6",
 275                                                       "rxtx7", "dma";
 276                                         status = "disabled";
 277                                 };
 278
 279                                 ecspi1: ecspi@02008000 {
 280                                         #address-cells = <1>;
 281                                         #size-cells = <0>;
 282                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 283                                         reg = <0x02008000 0x4000>;
 284                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 286                                                  <&clks IMX6SX_CLK_ECSPI1>;
 287                                         clock-names = "ipg", "per";
 288                                         status = "disabled";
 289                                 };
 290
 291                                 ecspi2: ecspi@0200c000 {
 292                                         #address-cells = <1>;
 293                                         #size-cells = <0>;
 294                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 295                                         reg = <0x0200c000 0x4000>;
 296                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 297                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 298                                                  <&clks IMX6SX_CLK_ECSPI2>;
 299                                         clock-names = "ipg", "per";
 300                                         status = "disabled";
 301                                 };
 302
 303                                 ecspi3: ecspi@02010000 {
 304                                         #address-cells = <1>;
 305                                         #size-cells = <0>;
 306                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 307                                         reg = <0x02010000 0x4000>;
 308                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 309                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 310                                                  <&clks IMX6SX_CLK_ECSPI3>;
 311                                         clock-names = "ipg", "per";
 312                                         status = "disabled";
 313                                 };
 314
 315                                 ecspi4: ecspi@02014000 {
 316                                         #address-cells = <1>;
 317                                         #size-cells = <0>;
 318                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 319                                         reg = <0x02014000 0x4000>;
 320                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 322                                                  <&clks IMX6SX_CLK_ECSPI4>;
 323                                         clock-names = "ipg", "per";
 324                                         status = "disabled";
 325                                 };
 326
 327                                 uart1: serial@02020000 {
 328                                         compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
 329                                         reg = <0x02020000 0x4000>;
 330                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 331                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 332                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 333                                         clock-names = "ipg", "per";
 334                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 335                                         dma-names = "rx", "tx";
 336                                         status = "disabled";
 337                                 };
 338
 339                                 esai: esai@02024000 {
 340                                         compatible = "fsl,imx35-esai";
 341                                         reg = <0x02024000 0x4000>;
 342                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 343                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 344                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 345                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 346                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 347                                                  <&clks IMX6SX_CLK_SPBA>;
 348                                         clock-names = "core", "mem", "extal",
 349                                                       "fsys", "dma";
 350                                         dmas = <&sdma 23 21 0>,
 351                                                <&sdma 24 21 0>;
 352                                         dma-names = "rx", "tx";
 353                                         status = "disabled";
 354                                 };
 355
 356                                 ssi1: ssi@02028000 {
 357                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 358                                         reg = <0x02028000 0x4000>;
 359                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 360                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 361                                                  <&clks IMX6SX_CLK_SSI1>;
 362                                         clock-names = "ipg", "baud";
 363                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 364                                         dma-names = "rx", "tx";
 365                                         status = "disabled";
 366                                 };
 367
 368                                 ssi2: ssi@0202c000 {
 369                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 370                                         reg = <0x0202c000 0x4000>;
 371                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 372                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 373                                                  <&clks IMX6SX_CLK_SSI2>;
 374                                         clock-names = "ipg", "baud";
 375                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 376                                         dma-names = "rx", "tx";
 377                                         status = "disabled";
 378                                 };
 379
 380                                 ssi3: ssi@02030000 {
 381                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 382                                         reg = <0x02030000 0x4000>;
 383                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 384                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 385                                                  <&clks IMX6SX_CLK_SSI3>;
 386                                         clock-names = "ipg", "baud";
 387                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 388                                         dma-names = "rx", "tx";
 389                                         status = "disabled";
 390                                 };
 391
 392                                 asrc: asrc@02034000 {
 393                                         compatible = "fsl,imx53-asrc";
 394                                         reg = <0x02034000 0x4000>;
 395                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 396                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 397                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 398                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 399                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 400                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 401                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 402                                                 <&clks IMX6SX_CLK_SPBA>;
 403                                         clock-names = "mem", "ipg", "asrck_0",
 404                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 405                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 406                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 407                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 408                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 409                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 410                                         dma-names = "rxa", "rxb", "rxc",
 411                                                     "txa", "txb", "txc";
 412                                         fsl,asrc-rate  = <48000>;
 413                                         fsl,asrc-width = <16>;
 414                                         status = "okay";
 415                                 };
 416
 417                                 asrc_p2p: asrc_p2p {
 418                                         compatible = "fsl,imx6q-asrc-p2p";
 419                                         fsl,p2p-rate  = <48000>;
 420                                         fsl,p2p-width = <16>;
 421                                         fsl,asrc-dma-rx-events = <17 18 19>;
 422                                         fsl,asrc-dma-tx-events = <20 21 22>;
 423                                         status = "okay";
 424                                 };
 425                         };
 426
 427                         pwm1: pwm@02080000 {
 428                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 429                                 reg = <0x02080000 0x4000>;
 430                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 432                                          <&clks IMX6SX_CLK_PWM1>;
 433                                 clock-names = "ipg", "per";
 434                                 #pwm-cells = <2>;
 435                         };
 436
 437                         pwm2: pwm@02084000 {
 438                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 439                                 reg = <0x02084000 0x4000>;
 440                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 442                                          <&clks IMX6SX_CLK_PWM2>;
 443                                 clock-names = "ipg", "per";
 444                                 #pwm-cells = <2>;
 445                         };
 446
 447                         pwm3: pwm@02088000 {
 448                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 449                                 reg = <0x02088000 0x4000>;
 450                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 452                                          <&clks IMX6SX_CLK_PWM3>;
 453                                 clock-names = "ipg", "per";
 454                                 #pwm-cells = <2>;
 455                         };
 456
 457                         pwm4: pwm@0208c000 {
 458                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 459                                 reg = <0x0208c000 0x4000>;
 460                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 462                                          <&clks IMX6SX_CLK_PWM4>;
 463                                 clock-names = "ipg", "per";
 464                                 #pwm-cells = <2>;
 465                         };
 466
 467                         flexcan1: can@02090000 {
 468                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 469                                 reg = <0x02090000 0x4000>;
 470                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 471                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 472                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 473                                 clock-names = "ipg", "per";
 474                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 475                                 status = "disabled";
 476                         };
 477
 478                         flexcan2: can@02094000 {
 479                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 480                                 reg = <0x02094000 0x4000>;
 481                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 483                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 484                                 clock-names = "ipg", "per";
 485                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 486                                 status = "disabled";
 487                         };
 488
 489                         gpt: gpt@02098000 {
 490                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 491                                 reg = <0x02098000 0x4000>;
 492                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 494                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 495                                 clock-names = "ipg", "per";
 496                         };
 497
 498                         gpio1: gpio@0209c000 {
 499                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 500                                 reg = <0x0209c000 0x4000>;
 501                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 502                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 503                                 gpio-controller;
 504                                 #gpio-cells = <2>;
 505                                 interrupt-controller;
 506                                 #interrupt-cells = <2>;
 507                         };
 508
 509                         gpio2: gpio@020a0000 {
 510                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 511                                 reg = <0x020a0000 0x4000>;
 512                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 513                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 514                                 gpio-controller;
 515                                 #gpio-cells = <2>;
 516                                 interrupt-controller;
 517                                 #interrupt-cells = <2>;
 518                         };
 519
 520                         gpio3: gpio@020a4000 {
 521                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 522                                 reg = <0x020a4000 0x4000>;
 523                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 524                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 525                                 gpio-controller;
 526                                 #gpio-cells = <2>;
 527                                 interrupt-controller;
 528                                 #interrupt-cells = <2>;
 529                         };
 530
 531                         gpio4: gpio@020a8000 {
 532                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 533                                 reg = <0x020a8000 0x4000>;
 534                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                         };
 541
 542                         gpio5: gpio@020ac000 {
 543                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 544                                 reg = <0x020ac000 0x4000>;
 545                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 547                                 gpio-controller;
 548                                 #gpio-cells = <2>;
 549                                 interrupt-controller;
 550                                 #interrupt-cells = <2>;
 551                         };
 552
 553                         gpio6: gpio@020b0000 {
 554                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 555                                 reg = <0x020b0000 0x4000>;
 556                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 557                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 558                                 gpio-controller;
 559                                 #gpio-cells = <2>;
 560                                 interrupt-controller;
 561                                 #interrupt-cells = <2>;
 562                         };
 563
 564                         gpio7: gpio@020b4000 {
 565                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 566                                 reg = <0x020b4000 0x4000>;
 567                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 568                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 569                                 gpio-controller;
 570                                 #gpio-cells = <2>;
 571                                 interrupt-controller;
 572                                 #interrupt-cells = <2>;
 573                         };
 574
 575                         kpp: kpp@020b8000 {
 576                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 577                                 reg = <0x020b8000 0x4000>;
 578                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 579                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 580                                 status = "disabled";
 581                         };
 582
 583                         wdog1: wdog@020bc000 {
 584                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 585                                 reg = <0x020bc000 0x4000>;
 586                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 587                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 588                         };
 589
 590                         wdog2: wdog@020c0000 {
 591                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 592                                 reg = <0x020c0000 0x4000>;
 593                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 594                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 595                                 status = "disabled";
 596                         };
 597
 598                         clks: ccm@020c4000 {
 599                                 compatible = "fsl,imx6sx-ccm";
 600                                 reg = <0x020c4000 0x4000>;
 601                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 602                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 603                                 #clock-cells = <1>;
 604                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 605                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 606                         };
 607
 608                         anatop: anatop@020c8000 {
 609                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 610                                              "syscon", "simple-bus";
 611                                 reg = <0x020c8000 0x1000>;
 612                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 613                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 614                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 615
 616                                 regulator-1p1@110 {
 617                                         compatible = "fsl,anatop-regulator";
 618                                         regulator-name = "vdd1p1";
 619                                         regulator-min-microvolt = <800000>;
 620                                         regulator-max-microvolt = <1375000>;
 621                                         regulator-always-on;
 622                                         anatop-reg-offset = <0x110>;
 623                                         anatop-vol-bit-shift = <8>;
 624                                         anatop-vol-bit-width = <5>;
 625                                         anatop-min-bit-val = <4>;
 626                                         anatop-min-voltage = <800000>;
 627                                         anatop-max-voltage = <1375000>;
 628                                 };
 629
 630                                 regulator-3p0@120 {
 631                                         compatible = "fsl,anatop-regulator";
 632                                         regulator-name = "vdd3p0";
 633                                         regulator-min-microvolt = <2800000>;
 634                                         regulator-max-microvolt = <3150000>;
 635                                         regulator-always-on;
 636                                         anatop-reg-offset = <0x120>;
 637                                         anatop-vol-bit-shift = <8>;
 638                                         anatop-vol-bit-width = <5>;
 639                                         anatop-min-bit-val = <0>;
 640                                         anatop-min-voltage = <2625000>;
 641                                         anatop-max-voltage = <3400000>;
 642                                 };
 643
 644                                 regulator-2p5@130 {
 645                                         compatible = "fsl,anatop-regulator";
 646                                         regulator-name = "vdd2p5";
 647                                         regulator-min-microvolt = <2100000>;
 648                                         regulator-max-microvolt = <2875000>;
 649                                         regulator-always-on;
 650                                         anatop-reg-offset = <0x130>;
 651                                         anatop-vol-bit-shift = <8>;
 652                                         anatop-vol-bit-width = <5>;
 653                                         anatop-min-bit-val = <0>;
 654                                         anatop-min-voltage = <2100000>;
 655                                         anatop-max-voltage = <2875000>;
 656                                 };
 657
 658                                 reg_arm: regulator-vddcore@140 {
 659                                         compatible = "fsl,anatop-regulator";
 660                                         regulator-name = "cpu";
 661                                         regulator-min-microvolt = <725000>;
 662                                         regulator-max-microvolt = <1450000>;
 663                                         regulator-always-on;
 664                                         anatop-reg-offset = <0x140>;
 665                                         anatop-vol-bit-shift = <0>;
 666                                         anatop-vol-bit-width = <5>;
 667                                         anatop-delay-reg-offset = <0x170>;
 668                                         anatop-delay-bit-shift = <24>;
 669                                         anatop-delay-bit-width = <2>;
 670                                         anatop-min-bit-val = <1>;
 671                                         anatop-min-voltage = <725000>;
 672                                         anatop-max-voltage = <1450000>;
 673                                 };
 674
 675                                 reg_pcie: regulator-vddpcie@140 {
 676                                         compatible = "fsl,anatop-regulator";
 677                                         regulator-name = "vddpcie";
 678                                         regulator-min-microvolt = <725000>;
 679                                         regulator-max-microvolt = <1450000>;
 680                                         anatop-reg-offset = <0x140>;
 681                                         anatop-vol-bit-shift = <9>;
 682                                         anatop-vol-bit-width = <5>;
 683                                         anatop-delay-reg-offset = <0x170>;
 684                                         anatop-delay-bit-shift = <26>;
 685                                         anatop-delay-bit-width = <2>;
 686                                         anatop-min-bit-val = <1>;
 687                                         anatop-min-voltage = <725000>;
 688                                         anatop-max-voltage = <1450000>;
 689                                 };
 690
 691                                 reg_soc: regulator-vddsoc@140 {
 692                                         compatible = "fsl,anatop-regulator";
 693                                         regulator-name = "vddsoc";
 694                                         regulator-min-microvolt = <725000>;
 695                                         regulator-max-microvolt = <1450000>;
 696                                         regulator-always-on;
 697                                         anatop-reg-offset = <0x140>;
 698                                         anatop-vol-bit-shift = <18>;
 699                                         anatop-vol-bit-width = <5>;
 700                                         anatop-delay-reg-offset = <0x170>;
 701                                         anatop-delay-bit-shift = <28>;
 702                                         anatop-delay-bit-width = <2>;
 703                                         anatop-min-bit-val = <1>;
 704                                         anatop-min-voltage = <725000>;
 705                                         anatop-max-voltage = <1450000>;
 706                                 };
 707                         };
 708
 709                         tempmon: tempmon {
 710                                 compatible = "fsl,imx6sx-tempmon";
 711                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 712                                 fsl,tempmon = <&anatop>;
 713                                 fsl,tempmon-data = <&ocotp>;
 714                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 715                         };
 716
 717                         usbphy1: usbphy@020c9000 {
 718                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 719                                 reg = <0x020c9000 0x1000>;
 720                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 721                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 722                                 fsl,anatop = <&anatop>;
 723                         };
 724
 725                         usbphy2: usbphy@020ca000 {
 726                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 727                                 reg = <0x020ca000 0x1000>;
 728                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 729                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 730                                 fsl,anatop = <&anatop>;
 731                         };
 732
 733                         mqs: mqs {
 734                                 compatible = "fsl,imx6sx-mqs";
 735                                 gpr = <&gpr>;
 736                                 status = "disabled";
 737                         };
 738
 739                         snvs: snvs@020cc000 {
 740                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 741                                 #address-cells = <1>;
 742                                 #size-cells = <1>;
 743                                 ranges = <0 0x020cc000 0x4000>;
 744
 745                                 snvs-rtc-lp@34 {
 746                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 747                                         reg = <0x34 0x58>;
 748                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 749                                 };
 750                         };
 751
 752                         snvs-pwrkey@0x020cc000 {
 753                                 compatible = "fsl,imx6sx-snvs-pwrkey";
 754                                 reg = <0x020cc000 0x4000>;
 755                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 756                                 fsl,keycode = <116>; /* KEY_POWER */
 757                                 fsl,wakeup;
 758                         };
 759
 760                         epit1: epit@020d0000 {
 761                                 reg = <0x020d0000 0x4000>;
 762                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 763                         };
 764
 765                         epit2: epit@020d4000 {
 766                                 reg = <0x020d4000 0x4000>;
 767                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 768                         };
 769
 770                         src: src@020d8000 {
 771                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 772                                 reg = <0x020d8000 0x4000>;
 773                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 774                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 775                                 #reset-cells = <1>;
 776                         };
 777
 778                         gpc: gpc@020dc000 {
 779                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 780                                 reg = <0x020dc000 0x4000>;
 781                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 782                                 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400200>;
 783                                 clocks = <&clks IMX6SX_CLK_GPU>;
 784                                 #power-domain-cells = <1>;
 785                         };
 786
 787                         iomuxc: iomuxc@020e0000 {
 788                                 compatible = "fsl,imx6sx-iomuxc";
 789                                 reg = <0x020e0000 0x4000>;
 790                         };
 791
 792                         gpr: iomuxc-gpr@020e4000 {
 793                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 794                                 reg = <0x020e4000 0x4000>;
 795                         };
 796
 797                         canfd1: canfd@020e8000 {
 798                                 compatible = "bosch,m_can";
 799                                 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
 800                                 reg-names = "canfd", "message_ram";
 801                                 interrupts = <0 114 0x04>;
 802                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 803                                 mram-cfg = <0x0 0 0 32 0 0 0 1>;
 804                                 status = "disabled";
 805                         };
 806
 807                         canfd2: canfd@020f0000 {
 808                                 compatible = "bosch,m_can";
 809                                 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
 810                                 reg-names = "canfd", "message_ram";
 811                                 interrupts = <0 115 0x04>;
 812                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 813                                 mram-cfg = <0x400 0 0 32 0 0 0 1>;
 814                                 status = "disabled";
 815                         };
 816
 817                         ldb: ldb@020e0014 {
 818                                 #address-cells = <1>;
 819                                 #size-cells = <0>;
 820                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 821                                 gpr = <&gpr>;
 822                                 status = "disabled";
 823
 824                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 825                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 826                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 827                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 828                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 829                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 830                                 clock-names = "ldb_di0",
 831                                               "di0_sel",
 832                                               "di1_sel",
 833                                               "ldb_di0_div_3_5",
 834                                               "ldb_di0_div_7",
 835                                               "ldb_di0_div_sel";
 836
 837                                 lvds-channel@0 {
 838                                         reg = <0>;
 839                                         status = "disabled";
 840                                 };
 841                         };
 842
 843                         sdma: sdma@020ec000 {
 844                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 845                                 reg = <0x020ec000 0x4000>;
 846                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 847                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 848                                          <&clks IMX6SX_CLK_SDMA>;
 849                                 clock-names = "ipg", "ahb";
 850                                 #dma-cells = <3>;
 851                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 852                         };
 853                 };
 854
 855                 aips2: aips-bus@02100000 {
 856                         compatible = "fsl,aips-bus", "simple-bus";
 857                         #address-cells = <1>;
 858                         #size-cells = <1>;
 859                         reg = <0x02100000 0x100000>;
 860                         ranges;
 861
 862                         usbotg1: usb@02184000 {
 863                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 864                                 reg = <0x02184000 0x200>;
 865                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 866                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 867                                 fsl,usbphy = <&usbphy1>;
 868                                 fsl,usbmisc = <&usbmisc 0>;
 869                                 fsl,anatop = <&anatop>;
 870                                 status = "disabled";
 871                         };
 872
 873                         usbotg2: usb@02184200 {
 874                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 875                                 reg = <0x02184200 0x200>;
 876                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 878                                 fsl,usbphy = <&usbphy2>;
 879                                 fsl,usbmisc = <&usbmisc 1>;
 880                                 status = "disabled";
 881                         };
 882
 883                         usbh: usb@02184400 {
 884                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 885                                 reg = <0x02184400 0x200>;
 886                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 887                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 888                                 fsl,usbmisc = <&usbmisc 2>;
 889                                 phy_type = "hsic";
 890                                 fsl,anatop = <&anatop>;
 891                                 status = "disabled";
 892                         };
 893
 894                         usbmisc: usbmisc@02184800 {
 895                                 #index-cells = <1>;
 896                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 897                                 reg = <0x02184800 0x200>;
 898                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 899                         };
 900
 901                         fec1: ethernet@02188000 {
 902                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 903                                 reg = <0x02188000 0x4000>;
 904                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 905                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clks IMX6SX_CLK_ENET>,
 907                                          <&clks IMX6SX_CLK_ENET_AHB>,
 908                                          <&clks IMX6SX_CLK_ENET_PTP>,
 909                                          <&clks IMX6SX_CLK_ENET_REF>,
 910                                          <&clks IMX6SX_CLK_ENET_PTP>;
 911                                 clock-names = "ipg", "ahb", "ptp",
 912                                               "enet_clk_ref", "enet_out";
 913                                 fsl,num-tx-queues=<3>;
 914                                 fsl,num-rx-queues=<3>;
 915                                 status = "disabled";
 916                         };
 917
 918                         mlb: mlb@0218c000 {
 919                                 reg = <0x0218c000 0x4000>;
 920                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 921                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 922                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 923                                 clocks = <&clks IMX6SX_CLK_MLB>;
 924                                 status = "disabled";
 925                         };
 926
 927                         usdhc1: usdhc@02190000 {
 928                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 929                                 reg = <0x02190000 0x4000>;
 930                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 931                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 932                                          <&clks IMX6SX_CLK_USDHC1>,
 933                                          <&clks IMX6SX_CLK_USDHC1>;
 934                                 clock-names = "ipg", "ahb", "per";
 935                                 bus-width = <4>;
 936                                 status = "disabled";
 937                         };
 938
 939                         usdhc2: usdhc@02194000 {
 940                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 941                                 reg = <0x02194000 0x4000>;
 942                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 943                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 944                                          <&clks IMX6SX_CLK_USDHC2>,
 945                                          <&clks IMX6SX_CLK_USDHC2>;
 946                                 clock-names = "ipg", "ahb", "per";
 947                                 bus-width = <4>;
 948                                 status = "disabled";
 949                         };
 950
 951                         usdhc3: usdhc@02198000 {
 952                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 953                                 reg = <0x02198000 0x4000>;
 954                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 956                                          <&clks IMX6SX_CLK_USDHC3>,
 957                                          <&clks IMX6SX_CLK_USDHC3>;
 958                                 clock-names = "ipg", "ahb", "per";
 959                                 bus-width = <4>;
 960                                 status = "disabled";
 961                         };
 962
 963                         usdhc4: usdhc@0219c000 {
 964                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 965                                 reg = <0x0219c000 0x4000>;
 966                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 968                                          <&clks IMX6SX_CLK_USDHC4>,
 969                                          <&clks IMX6SX_CLK_USDHC4>;
 970                                 clock-names = "ipg", "ahb", "per";
 971                                 bus-width = <4>;
 972                                 status = "disabled";
 973                         };
 974
 975                         i2c1: i2c@021a0000 {
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 979                                 reg = <0x021a0000 0x4000>;
 980                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 981                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 982                                 status = "disabled";
 983                         };
 984
 985                         i2c2: i2c@021a4000 {
 986                                 #address-cells = <1>;
 987                                 #size-cells = <0>;
 988                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 989                                 reg = <0x021a4000 0x4000>;
 990                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 991                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 992                                 status = "disabled";
 993                         };
 994
 995                         i2c3: i2c@021a8000 {
 996                                 #address-cells = <1>;
 997                                 #size-cells = <0>;
 998                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 999                                 reg = <0x021a8000 0x4000>;
1000                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1001                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1002                                 status = "disabled";
1003                         };
1004
1005                         mmdc: mmdc@021b0000 {
1006                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1007                                 reg = <0x021b0000 0x4000>;
1008                         };
1009
1010                         fec2: ethernet@021b4000 {
1011                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1012                                 reg = <0x021b4000 0x4000>;
1013                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1014                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1015                                 clocks = <&clks IMX6SX_CLK_ENET>,
1016                                          <&clks IMX6SX_CLK_ENET_AHB>,
1017                                          <&clks IMX6SX_CLK_ENET_PTP>,
1018                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1019                                          <&clks IMX6SX_CLK_ENET_PTP>;
1020                                 clock-names = "ipg", "ahb", "ptp",
1021                                               "enet_clk_ref", "enet_out";
1022                                 status = "disabled";
1023                         };
1024
1025                         weim: weim@021b8000 {
1026                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1027                                 reg = <0x021b8000 0x4000>;
1028                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1029                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1030                         };
1031
1032                         ocotp: ocotp-ctrl@021bc000 {
1033                                 compatible = "syscon";
1034                                 reg = <0x021bc000 0x4000>;
1035                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1036                         };
1037
1038                         ocotp-fuse@021bc000 {
1039                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
1040                                 reg = <0x021bc000 0x4000>;
1041                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1042                         };
1043
1044                         romcp@021ac000 {
1045                                 compatible = "fsl,imx6sx-romcp", "syscon";
1046                                 reg = <0x021ac000 0x4000>;
1047                         };
1048
1049                         sai1: sai@021d4000 {
1050                                 compatible = "fsl,imx6sx-sai";
1051                                 reg = <0x021d4000 0x4000>;
1052                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1053                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1054                                          <&clks IMX6SX_CLK_SAI1>,
1055                                          <&clks 0>, <&clks 0>;
1056                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1057                                 dma-names = "rx", "tx";
1058                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
1059                                 dma-source = <&gpr 0 15 0 16>;
1060                                 status = "disabled";
1061                         };
1062
1063                         audmux: audmux@021d8000 {
1064                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1065                                 reg = <0x021d8000 0x4000>;
1066                                 status = "disabled";
1067                         };
1068
1069                         sai2: sai@021dc000 {
1070                                 compatible = "fsl,imx6sx-sai";
1071                                 reg = <0x021dc000 0x4000>;
1072                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1073                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1074                                          <&clks IMX6SX_CLK_SAI2>,
1075                                          <&clks 0>, <&clks 0>;
1076                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1077                                 dma-names = "rx", "tx";
1078                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1079                                 dma-source = <&gpr 0 17 0 18>;
1080                                 status = "disabled";
1081                         };
1082
1083                         qspi1: qspi@021e0000 {
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086                                 compatible = "fsl,imx6sx-qspi";
1087                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1088                                 reg-names = "QuadSPI", "QuadSPI-memory";
1089                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1090                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1091                                          <&clks IMX6SX_CLK_QSPI1>;
1092                                 clock-names = "qspi_en", "qspi";
1093                                 status = "disabled";
1094                         };
1095
1096                         qspi2: qspi@021e4000 {
1097                                 #address-cells = <1>;
1098                                 #size-cells = <0>;
1099                                 compatible = "fsl,imx6sx-qspi";
1100                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1101                                 reg-names = "QuadSPI", "QuadSPI-memory";
1102                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1103                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1104                                          <&clks IMX6SX_CLK_QSPI2>;
1105                                 clock-names = "qspi_en", "qspi";
1106                                 status = "disabled";
1107                         };
1108
1109                         qspi_m4: qspi-m4 {
1110                                 compatible = "fsl,imx6sx-qspi-m4-restore";
1111                                 reg = <0x021e4000 0x4000>;
1112                                 status = "disabled";
1113                         };
1114
1115                         uart2: serial@021e8000 {
1116                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1117                                 reg = <0x021e8000 0x4000>;
1118                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1119                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1120                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1121                                 clock-names = "ipg", "per";
1122                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1123                                 dma-names = "rx", "tx";
1124                                 status = "disabled";
1125                         };
1126
1127                         uart3: serial@021ec000 {
1128                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1129                                 reg = <0x021ec000 0x4000>;
1130                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1131                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1132                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1133                                 clock-names = "ipg", "per";
1134                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1135                                 dma-names = "rx", "tx";
1136                                 status = "disabled";
1137                         };
1138
1139                         uart4: serial@021f0000 {
1140                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1141                                 reg = <0x021f0000 0x4000>;
1142                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1143                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1144                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1145                                 clock-names = "ipg", "per";
1146                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1147                                 dma-names = "rx", "tx";
1148                                 status = "disabled";
1149                         };
1150
1151                         uart5: serial@021f4000 {
1152                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1153                                 reg = <0x021f4000 0x4000>;
1154                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1155                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1156                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1157                                 clock-names = "ipg", "per";
1158                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1159                                 dma-names = "rx", "tx";
1160                                 status = "disabled";
1161                         };
1162
1163                         i2c4: i2c@021f8000 {
1164                                 #address-cells = <1>;
1165                                 #size-cells = <0>;
1166                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1167                                 reg = <0x021f8000 0x4000>;
1168                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1169                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1170                                 status = "disabled";
1171                         };
1172                 };
1173
1174                 aips3: aips-bus@02200000 {
1175                         compatible = "fsl,aips-bus", "simple-bus";
1176                         #address-cells = <1>;
1177                         #size-cells = <1>;
1178                         reg = <0x02200000 0x100000>;
1179                         ranges;
1180
1181                         spba-bus@02200000 {
1182                                 compatible = "fsl,spba-bus", "simple-bus";
1183                                 #address-cells = <1>;
1184                                 #size-cells = <1>;
1185                                 reg = <0x02240000 0x40000>;
1186                                 ranges;
1187
1188                                 dcic1: dcic@0220c000 {
1189                                         compatible = "fsl,imx6sx-dcic";
1190                                         reg = <0x0220c000 0x4000>;
1191                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1192                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1193                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1194                                         clock-names = "dcic", "disp-axi";
1195                                         gpr = <&gpr>;
1196                                         status = "disabled";
1197                                 };
1198
1199                                 dcic2: dcic@02210000 {
1200                                         compatible = "fsl,imx6sx-dcic";
1201                                         reg = <0x02210000 0x4000>;
1202                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1203                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1204                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1205                                         clock-names = "dcic", "disp-axi";
1206                                         gpr = <&gpr>;
1207                                         status = "disabled";
1208                                 };
1209
1210                                 csi1: csi@02214000 {
1211                                         compatible = "fsl,imx6s-csi";
1212                                         reg = <0x02214000 0x4000>;
1213                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1214                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1215                                                  <&clks IMX6SX_CLK_CSI>,
1216                                                  <&clks IMX6SX_CLK_DCIC1>;
1217                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1218                                         status = "disabled";
1219                                 };
1220
1221                                 pxp: pxp@02218000 {
1222                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1223                                         reg = <0x02218000 0x4000>;
1224                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1225                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1226                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1227                                         clock-names = "pxp-axi", "disp-axi";
1228                                         status = "disabled";
1229                                 };
1230
1231                                 csi2: csi@0221c000 {
1232                                         compatible = "fsl,imx6s-csi";
1233                                         reg = <0x0221c000 0x4000>;
1234                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1235                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1236                                                  <&clks IMX6SX_CLK_CSI>,
1237                                                  <&clks IMX6SX_CLK_DCIC2>;
1238                                         clock-names = "disp-axi", "csi_mclk", "disp_dcic";
1239                                         status = "disabled";
1240                                 };
1241
1242                                 lcdif1: lcdif@02220000 {
1243                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1244                                         reg = <0x02220000 0x4000>;
1245                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1246                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1247                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1248                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1249                                         clock-names = "pix", "axi", "disp_axi";
1250                                         status = "disabled";
1251                                 };
1252
1253                                 lcdif2: lcdif@02224000 {
1254                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1255                                         reg = <0x02224000 0x4000>;
1256                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1257                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1258                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1259                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1260                                         clock-names = "pix", "axi", "disp_axi";
1261                                         status = "disabled";
1262                                 };
1263
1264                                 vadc: vadc@02228000 {
1265                                         compatible = "fsl,imx6sx-vadc";
1266                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1267                                         reg-names = "vadc-vafe", "vadc-vdec";
1268                                         clocks = <&clks IMX6SX_CLK_VADC>,
1269                                                  <&clks IMX6SX_CLK_CSI>;
1270                                         clock-names = "vadc", "csi";
1271                                         gpr = <&gpr>;
1272                                         status = "disabled";
1273                                 };
1274                         };
1275
1276                         adc1: adc@02280000 {
1277                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1278                                 reg = <0x02280000 0x4000>;
1279                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1280                                 clocks = <&clks IMX6SX_CLK_IPG>;
1281                                 num-channels = <4>;
1282                                 clock-names = "adc";
1283                                 status = "disabled";
1284                         };
1285
1286                         adc2: adc@02284000 {
1287                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1288                                 reg = <0x02284000 0x4000>;
1289                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1290                                 clocks = <&clks IMX6SX_CLK_IPG>;
1291                                 num-channels = <4>;
1292                                 clock-names = "adc";
1293                                 status = "disabled";
1294                         };
1295
1296                         wdog3: wdog@02288000 {
1297                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1298                                 reg = <0x02288000 0x4000>;
1299                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1300                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1301                                 status = "disabled";
1302                         };
1303
1304                         ecspi5: ecspi@0228c000 {
1305                                 #address-cells = <1>;
1306                                 #size-cells = <0>;
1307                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1308                                 reg = <0x0228c000 0x4000>;
1309                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1310                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1311                                          <&clks IMX6SX_CLK_ECSPI5>;
1312                                 clock-names = "ipg", "per";
1313                                 status = "disabled";
1314                         };
1315
1316                         sema4: sema4@02290000 { /* sema4 */
1317                                 compatible = "fsl,imx6sx-sema4";
1318                                 reg = <0x02290000 0x4000>;
1319                                 interrupts = <0 116 0x04>;
1320                                 status = "okay";
1321                         };
1322
1323                         mu: mu@02294000 { /* mu */
1324                                 compatible = "fsl,imx6sx-mu";
1325                                 reg = <0x02294000 0x4000>;
1326                                 interrupts = <0 90 0x04>;
1327                                 status = "okay";
1328                         };
1329
1330                         uart6: serial@022a0000 {
1331                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1332                                 reg = <0x022a0000 0x4000>;
1333                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1334                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1335                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1336                                 clock-names = "ipg", "per";
1337                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1338                                 dma-names = "rx", "tx";
1339                                 status = "disabled";
1340                         };
1341
1342                         pwm5: pwm@022a4000 {
1343                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1344                                 reg = <0x022a4000 0x4000>;
1345                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1346                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1347                                          <&clks IMX6SX_CLK_PWM5>;
1348                                 clock-names = "ipg", "per";
1349                                 #pwm-cells = <2>;
1350                         };
1351
1352                         pwm6: pwm@022a8000 {
1353                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1354                                 reg = <0x022a8000 0x4000>;
1355                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1356                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1357                                          <&clks IMX6SX_CLK_PWM6>;
1358                                 clock-names = "ipg", "per";
1359                                 #pwm-cells = <2>;
1360                         };
1361
1362                         pwm7: pwm@022ac000 {
1363                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1364                                 reg = <0x022ac000 0x4000>;
1365                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1366                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1367                                          <&clks IMX6SX_CLK_PWM7>;
1368                                 clock-names = "ipg", "per";
1369                                 #pwm-cells = <2>;
1370                         };
1371
1372                         pwm8: pwm@0022b0000 {
1373                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1374                                 reg = <0x0022b0000 0x4000>;
1375                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1376                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1377                                          <&clks IMX6SX_CLK_PWM8>;
1378                                 clock-names = "ipg", "per";
1379                                 #pwm-cells = <2>;
1380                         };
1381                 };
1382
1383                 pcie: pcie@0x08000000 {
1384                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1385                         reg = <0x08ffc000 0x4000>; /* DBI */
1386                         #address-cells = <3>;
1387                         #size-cells = <2>;
1388                         device_type = "pci";
1389                                   /* configuration space */
1390                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1391                                   /* downstream I/O */
1392                                   0x81000000 0 0          0x08f80000 0 0x00010000
1393                                   /* non-prefetchable memory */
1394                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1395                         num-lanes = <1>;
1396                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1397                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1398                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1399                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1400                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1401                         clock-names = "pcie_ref_125m", "pcie_axi",
1402                                       "lvds_gate", "display_axi";
1403                         status = "disabled";
1404                 };
1405         };
1406 };