2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sx-pinfunc.h"
13 #include "skeleton.dtsi"
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
66 fsl,soc-operating-points = <
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <®_arm>;
81 soc-supply = <®_soc>;
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
89 reg = <0x00a01000 0x1000>,
98 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
114 compatible = "fixed-clock";
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
122 compatible = "fixed-clock";
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
195 reg = <0x02000000 0x100000>;
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
202 reg = <0x02000000 0x40000>;
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
301 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
313 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
314 reg = <0x0202c000 0x4000>;
315 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
317 <&clks IMX6SX_CLK_SSI2>;
318 clock-names = "ipg", "baud";
319 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
320 dma-names = "rx", "tx";
325 compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
326 reg = <0x02030000 0x4000>;
327 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
329 <&clks IMX6SX_CLK_SSI3>;
330 clock-names = "ipg", "baud";
331 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
332 dma-names = "rx", "tx";
336 asrc: asrc@02034000 {
337 compatible = "fsl,imx53-asrc";
338 reg = <0x02034000 0x4000>;
339 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
341 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
342 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
343 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
344 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
345 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
346 <&clks IMX6SX_CLK_SPBA>;
347 clock-names = "mem", "ipg", "asrck_0",
348 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
349 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
350 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
351 "asrck_d", "asrck_e", "asrck_f", "dma";
352 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
353 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
354 dma-names = "rxa", "rxb", "rxc",
356 fsl,asrc-rate = <48000>;
357 fsl,asrc-width = <16>;
362 compatible = "fsl,imx6q-asrc-p2p";
363 fsl,p2p-rate = <48000>;
364 fsl,p2p-width = <16>;
365 fsl,asrc-dma-rx-events = <17 18 19>;
366 fsl,asrc-dma-tx-events = <20 21 22>;
372 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
373 reg = <0x02080000 0x4000>;
374 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6SX_CLK_PWM1>,
376 <&clks IMX6SX_CLK_PWM1>;
377 clock-names = "ipg", "per";
382 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
383 reg = <0x02084000 0x4000>;
384 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks IMX6SX_CLK_PWM2>,
386 <&clks IMX6SX_CLK_PWM2>;
387 clock-names = "ipg", "per";
392 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
393 reg = <0x02088000 0x4000>;
394 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks IMX6SX_CLK_PWM3>,
396 <&clks IMX6SX_CLK_PWM3>;
397 clock-names = "ipg", "per";
402 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
403 reg = <0x0208c000 0x4000>;
404 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6SX_CLK_PWM4>,
406 <&clks IMX6SX_CLK_PWM4>;
407 clock-names = "ipg", "per";
411 flexcan1: can@02090000 {
412 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
413 reg = <0x02090000 0x4000>;
414 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
416 <&clks IMX6SX_CLK_CAN1_SERIAL>;
417 clock-names = "ipg", "per";
418 stop-mode = <&gpr 0x10 1 0x10 17>;
422 flexcan2: can@02094000 {
423 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
424 reg = <0x02094000 0x4000>;
425 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
427 <&clks IMX6SX_CLK_CAN2_SERIAL>;
428 clock-names = "ipg", "per";
429 stop-mode = <&gpr 0x10 2 0x10 18>;
434 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
435 reg = <0x02098000 0x4000>;
436 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
438 <&clks IMX6SX_CLK_GPT_SERIAL>;
439 clock-names = "ipg", "per";
442 gpio1: gpio@0209c000 {
443 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
444 reg = <0x0209c000 0x4000>;
445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
453 gpio2: gpio@020a0000 {
454 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
455 reg = <0x020a0000 0x4000>;
456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
464 gpio3: gpio@020a4000 {
465 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
466 reg = <0x020a4000 0x4000>;
467 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
475 gpio4: gpio@020a8000 {
476 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
477 reg = <0x020a8000 0x4000>;
478 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
486 gpio5: gpio@020ac000 {
487 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
488 reg = <0x020ac000 0x4000>;
489 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
497 gpio6: gpio@020b0000 {
498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
499 reg = <0x020b0000 0x4000>;
500 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
508 gpio7: gpio@020b4000 {
509 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
510 reg = <0x020b4000 0x4000>;
511 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
520 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
521 reg = <0x020b8000 0x4000>;
522 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clks IMX6SX_CLK_DUMMY>;
527 wdog1: wdog@020bc000 {
528 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
529 reg = <0x020bc000 0x4000>;
530 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clks IMX6SX_CLK_DUMMY>;
534 wdog2: wdog@020c0000 {
535 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
536 reg = <0x020c0000 0x4000>;
537 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clks IMX6SX_CLK_DUMMY>;
543 compatible = "fsl,imx6sx-ccm";
544 reg = <0x020c4000 0x4000>;
545 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
549 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
552 anatop: anatop@020c8000 {
553 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
554 "syscon", "simple-bus";
555 reg = <0x020c8000 0x1000>;
556 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
561 compatible = "fsl,anatop-regulator";
562 regulator-name = "vdd1p1";
563 regulator-min-microvolt = <800000>;
564 regulator-max-microvolt = <1375000>;
566 anatop-reg-offset = <0x110>;
567 anatop-vol-bit-shift = <8>;
568 anatop-vol-bit-width = <5>;
569 anatop-min-bit-val = <4>;
570 anatop-min-voltage = <800000>;
571 anatop-max-voltage = <1375000>;
575 compatible = "fsl,anatop-regulator";
576 regulator-name = "vdd3p0";
577 regulator-min-microvolt = <2800000>;
578 regulator-max-microvolt = <3150000>;
580 anatop-reg-offset = <0x120>;
581 anatop-vol-bit-shift = <8>;
582 anatop-vol-bit-width = <5>;
583 anatop-min-bit-val = <0>;
584 anatop-min-voltage = <2625000>;
585 anatop-max-voltage = <3400000>;
589 compatible = "fsl,anatop-regulator";
590 regulator-name = "vdd2p5";
591 regulator-min-microvolt = <2100000>;
592 regulator-max-microvolt = <2875000>;
594 anatop-reg-offset = <0x130>;
595 anatop-vol-bit-shift = <8>;
596 anatop-vol-bit-width = <5>;
597 anatop-min-bit-val = <0>;
598 anatop-min-voltage = <2100000>;
599 anatop-max-voltage = <2875000>;
602 reg_arm: regulator-vddcore@140 {
603 compatible = "fsl,anatop-regulator";
604 regulator-name = "cpu";
605 regulator-min-microvolt = <725000>;
606 regulator-max-microvolt = <1450000>;
608 anatop-reg-offset = <0x140>;
609 anatop-vol-bit-shift = <0>;
610 anatop-vol-bit-width = <5>;
611 anatop-delay-reg-offset = <0x170>;
612 anatop-delay-bit-shift = <24>;
613 anatop-delay-bit-width = <2>;
614 anatop-min-bit-val = <1>;
615 anatop-min-voltage = <725000>;
616 anatop-max-voltage = <1450000>;
619 reg_pcie: regulator-vddpcie@140 {
620 compatible = "fsl,anatop-regulator";
621 regulator-name = "vddpcie";
622 regulator-min-microvolt = <725000>;
623 regulator-max-microvolt = <1450000>;
624 anatop-reg-offset = <0x140>;
625 anatop-vol-bit-shift = <9>;
626 anatop-vol-bit-width = <5>;
627 anatop-delay-reg-offset = <0x170>;
628 anatop-delay-bit-shift = <26>;
629 anatop-delay-bit-width = <2>;
630 anatop-min-bit-val = <1>;
631 anatop-min-voltage = <725000>;
632 anatop-max-voltage = <1450000>;
635 reg_soc: regulator-vddsoc@140 {
636 compatible = "fsl,anatop-regulator";
637 regulator-name = "vddsoc";
638 regulator-min-microvolt = <725000>;
639 regulator-max-microvolt = <1450000>;
641 anatop-reg-offset = <0x140>;
642 anatop-vol-bit-shift = <18>;
643 anatop-vol-bit-width = <5>;
644 anatop-delay-reg-offset = <0x170>;
645 anatop-delay-bit-shift = <28>;
646 anatop-delay-bit-width = <2>;
647 anatop-min-bit-val = <1>;
648 anatop-min-voltage = <725000>;
649 anatop-max-voltage = <1450000>;
654 compatible = "fsl,imx6sx-tempmon";
655 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
656 fsl,tempmon = <&anatop>;
657 fsl,tempmon-data = <&ocotp>;
658 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
661 usbphy1: usbphy@020c9000 {
662 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
663 reg = <0x020c9000 0x1000>;
664 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clks IMX6SX_CLK_USBPHY1>;
666 fsl,anatop = <&anatop>;
669 usbphy2: usbphy@020ca000 {
670 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
671 reg = <0x020ca000 0x1000>;
672 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6SX_CLK_USBPHY2>;
674 fsl,anatop = <&anatop>;
677 snvs: snvs@020cc000 {
678 compatible = "fsl,sec-v4.0-mon", "simple-bus";
679 #address-cells = <1>;
681 ranges = <0 0x020cc000 0x4000>;
684 compatible = "fsl,sec-v4.0-mon-rtc-lp";
686 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
690 epit1: epit@020d0000 {
691 reg = <0x020d0000 0x4000>;
692 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
695 epit2: epit@020d4000 {
696 reg = <0x020d4000 0x4000>;
697 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
701 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
702 reg = <0x020d8000 0x4000>;
703 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
709 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
710 reg = <0x020dc000 0x4000>;
711 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
712 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400200>;
715 iomuxc: iomuxc@020e0000 {
716 compatible = "fsl,imx6sx-iomuxc";
717 reg = <0x020e0000 0x4000>;
720 gpr: iomuxc-gpr@020e4000 {
721 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
722 reg = <0x020e4000 0x4000>;
725 canfd1: canfd@020e8000 {
726 compatible = "bosch,m_can";
727 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
728 reg-names = "canfd", "message_ram";
729 interrupts = <0 114 0x04>;
730 clocks = <&clks IMX6SX_CLK_CANFD>;
731 mram-cfg = <0x0 0 0 32 0 0 0 1>;
735 canfd2: canfd@020f0000 {
736 compatible = "bosch,m_can";
737 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
738 reg-names = "canfd", "message_ram";
739 interrupts = <0 115 0x04>;
740 clocks = <&clks IMX6SX_CLK_CANFD>;
741 mram-cfg = <0x400 0 0 32 0 0 0 1>;
746 #address-cells = <1>;
748 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
752 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
753 <&clks IMX6SX_CLK_LCDIF1_SEL>,
754 <&clks IMX6SX_CLK_LCDIF2_SEL>,
755 <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
756 <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
757 <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
758 clock-names = "ldb_di0",
771 sdma: sdma@020ec000 {
772 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
773 reg = <0x020ec000 0x4000>;
774 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6SX_CLK_SDMA>,
776 <&clks IMX6SX_CLK_SDMA>;
777 clock-names = "ipg", "ahb";
779 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
783 aips2: aips-bus@02100000 {
784 compatible = "fsl,aips-bus", "simple-bus";
785 #address-cells = <1>;
787 reg = <0x02100000 0x100000>;
790 usbotg1: usb@02184000 {
791 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
792 reg = <0x02184000 0x200>;
793 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clks IMX6SX_CLK_USBOH3>;
795 fsl,usbphy = <&usbphy1>;
796 fsl,usbmisc = <&usbmisc 0>;
797 fsl,anatop = <&anatop>;
801 usbotg2: usb@02184200 {
802 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
803 reg = <0x02184200 0x200>;
804 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6SX_CLK_USBOH3>;
806 fsl,usbphy = <&usbphy2>;
807 fsl,usbmisc = <&usbmisc 1>;
812 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
813 reg = <0x02184400 0x200>;
814 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SX_CLK_USBOH3>;
816 fsl,usbmisc = <&usbmisc 2>;
818 fsl,anatop = <&anatop>;
822 usbmisc: usbmisc@02184800 {
824 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
825 reg = <0x02184800 0x200>;
826 clocks = <&clks IMX6SX_CLK_USBOH3>;
829 fec1: ethernet@02188000 {
830 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
831 reg = <0x02188000 0x4000>;
832 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&clks IMX6SX_CLK_ENET>,
835 <&clks IMX6SX_CLK_ENET_AHB>,
836 <&clks IMX6SX_CLK_ENET_PTP>,
837 <&clks IMX6SX_CLK_ENET_REF>,
838 <&clks IMX6SX_CLK_ENET_PTP>;
839 clock-names = "ipg", "ahb", "ptp",
840 "enet_clk_ref", "enet_out";
841 fsl,num-tx-queues=<3>;
842 fsl,num-rx-queues=<3>;
847 reg = <0x0218c000 0x4000>;
848 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6SX_CLK_MLB>;
855 usdhc1: usdhc@02190000 {
856 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
857 reg = <0x02190000 0x4000>;
858 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clks IMX6SX_CLK_USDHC1>,
860 <&clks IMX6SX_CLK_USDHC1>,
861 <&clks IMX6SX_CLK_USDHC1>;
862 clock-names = "ipg", "ahb", "per";
867 usdhc2: usdhc@02194000 {
868 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
869 reg = <0x02194000 0x4000>;
870 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6SX_CLK_USDHC2>,
872 <&clks IMX6SX_CLK_USDHC2>,
873 <&clks IMX6SX_CLK_USDHC2>;
874 clock-names = "ipg", "ahb", "per";
879 usdhc3: usdhc@02198000 {
880 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
881 reg = <0x02198000 0x4000>;
882 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6SX_CLK_USDHC3>,
884 <&clks IMX6SX_CLK_USDHC3>,
885 <&clks IMX6SX_CLK_USDHC3>;
886 clock-names = "ipg", "ahb", "per";
891 usdhc4: usdhc@0219c000 {
892 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
893 reg = <0x0219c000 0x4000>;
894 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&clks IMX6SX_CLK_USDHC4>,
896 <&clks IMX6SX_CLK_USDHC4>,
897 <&clks IMX6SX_CLK_USDHC4>;
898 clock-names = "ipg", "ahb", "per";
904 #address-cells = <1>;
906 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
907 reg = <0x021a0000 0x4000>;
908 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX6SX_CLK_I2C1>;
914 #address-cells = <1>;
916 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
917 reg = <0x021a4000 0x4000>;
918 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clks IMX6SX_CLK_I2C2>;
924 #address-cells = <1>;
926 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
927 reg = <0x021a8000 0x4000>;
928 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6SX_CLK_I2C3>;
933 mmdc: mmdc@021b0000 {
934 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
935 reg = <0x021b0000 0x4000>;
938 fec2: ethernet@021b4000 {
939 compatible = "fsl,imx6sx-fec";
940 reg = <0x021b4000 0x4000>;
941 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6SX_CLK_ENET>,
944 <&clks IMX6SX_CLK_ENET_AHB>,
945 <&clks IMX6SX_CLK_ENET_PTP>,
946 <&clks IMX6SX_CLK_ENET2_REF_125M>,
947 <&clks IMX6SX_CLK_ENET_PTP>;
948 clock-names = "ipg", "ahb", "ptp",
949 "enet_clk_ref", "enet_out";
953 weim: weim@021b8000 {
954 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
955 reg = <0x021b8000 0x4000>;
956 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
960 ocotp: ocotp-ctrl@021bc000 {
961 compatible = "syscon";
962 reg = <0x021bc000 0x4000>;
963 clocks = <&clks IMX6SX_CLK_OCOTP>;
966 ocotp-fuse@021bc000 {
967 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
968 reg = <0x021bc000 0x4000>;
969 clocks = <&clks IMX6SX_CLK_OCOTP>;
973 compatible = "fsl,imx6sx-sai";
974 reg = <0x021d4000 0x4000>;
975 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
977 <&clks IMX6SX_CLK_SAI1>,
978 <&clks 0>, <&clks 0>;
979 clock-names = "bus", "mclk1", "mclk2", "mclk3";
980 dma-names = "rx", "tx";
981 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
982 dma-source = <&gpr 0 15 0 16>;
986 audmux: audmux@021d8000 {
987 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
988 reg = <0x021d8000 0x4000>;
993 compatible = "fsl,imx6sx-sai";
994 reg = <0x021dc000 0x4000>;
995 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
997 <&clks IMX6SX_CLK_SAI2>,
998 <&clks 0>, <&clks 0>;
999 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1000 dma-names = "rx", "tx";
1001 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1002 dma-source = <&gpr 0 17 0 18>;
1003 status = "disabled";
1006 qspi1: qspi@021e0000 {
1007 #address-cells = <1>;
1009 compatible = "fsl,imx6sx-qspi";
1010 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1011 reg-names = "QuadSPI", "QuadSPI-memory";
1012 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clks IMX6SX_CLK_QSPI1>,
1014 <&clks IMX6SX_CLK_QSPI1>;
1015 clock-names = "qspi_en", "qspi";
1016 status = "disabled";
1019 qspi2: qspi@021e4000 {
1020 #address-cells = <1>;
1022 compatible = "fsl,imx6sx-qspi";
1023 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1024 reg-names = "QuadSPI", "QuadSPI-memory";
1025 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&clks IMX6SX_CLK_QSPI2>,
1027 <&clks IMX6SX_CLK_QSPI2>;
1028 clock-names = "qspi_en", "qspi";
1029 status = "disabled";
1032 uart2: serial@021e8000 {
1033 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1034 reg = <0x021e8000 0x4000>;
1035 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1037 <&clks IMX6SX_CLK_UART_SERIAL>;
1038 clock-names = "ipg", "per";
1039 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1040 dma-names = "rx", "tx";
1041 status = "disabled";
1044 uart3: serial@021ec000 {
1045 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1046 reg = <0x021ec000 0x4000>;
1047 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1049 <&clks IMX6SX_CLK_UART_SERIAL>;
1050 clock-names = "ipg", "per";
1051 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1052 dma-names = "rx", "tx";
1053 status = "disabled";
1056 uart4: serial@021f0000 {
1057 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1058 reg = <0x021f0000 0x4000>;
1059 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1061 <&clks IMX6SX_CLK_UART_SERIAL>;
1062 clock-names = "ipg", "per";
1063 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1064 dma-names = "rx", "tx";
1065 status = "disabled";
1068 uart5: serial@021f4000 {
1069 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1070 reg = <0x021f4000 0x4000>;
1071 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1073 <&clks IMX6SX_CLK_UART_SERIAL>;
1074 clock-names = "ipg", "per";
1075 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1076 dma-names = "rx", "tx";
1077 status = "disabled";
1080 i2c4: i2c@021f8000 {
1081 #address-cells = <1>;
1083 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1084 reg = <0x021f8000 0x4000>;
1085 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&clks IMX6SX_CLK_I2C4>;
1087 status = "disabled";
1091 aips3: aips-bus@02200000 {
1092 compatible = "fsl,aips-bus", "simple-bus";
1093 #address-cells = <1>;
1095 reg = <0x02200000 0x100000>;
1099 compatible = "fsl,spba-bus", "simple-bus";
1100 #address-cells = <1>;
1102 reg = <0x02240000 0x40000>;
1105 dcic1: dcic@0220c000 {
1106 compatible = "fsl,imx6sx-dcic";
1107 reg = <0x0220c000 0x4000>;
1108 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clks IMX6SX_CLK_DCIC1>,
1110 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1111 clock-names = "dcic", "disp-axi";
1113 status = "disabled";
1116 dcic2: dcic@02210000 {
1117 compatible = "fsl,imx6sx-dcic";
1118 reg = <0x02210000 0x4000>;
1119 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6SX_CLK_DCIC2>,
1121 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1122 clock-names = "dcic", "disp-axi";
1124 status = "disabled";
1127 csi1: csi@02214000 {
1128 reg = <0x02214000 0x4000>;
1129 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1131 <&clks IMX6SX_CLK_CSI>,
1132 <&clks IMX6SX_CLK_DCIC1>;
1133 clock-names = "disp-axi", "csi_mclk", "dcic";
1134 status = "disabled";
1138 compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1139 reg = <0x02218000 0x4000>;
1140 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1142 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1143 clock-names = "pxp-axi", "disp-axi";
1144 status = "disabled";
1147 csi2: csi@0221c000 {
1148 reg = <0x0221c000 0x4000>;
1149 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1151 <&clks IMX6SX_CLK_CSI>,
1152 <&clks IMX6SX_CLK_DCIC2>;
1153 clock-names = "disp-axi", "csi_mclk", "dcic";
1154 status = "disabled";
1157 lcdif1: lcdif@02220000 {
1158 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1159 reg = <0x02220000 0x4000>;
1160 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1162 <&clks IMX6SX_CLK_LCDIF_APB>,
1163 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1164 clock-names = "pix", "axi", "disp_axi";
1165 status = "disabled";
1168 lcdif2: lcdif@02224000 {
1169 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1170 reg = <0x02224000 0x4000>;
1171 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1173 <&clks IMX6SX_CLK_LCDIF_APB>,
1174 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1175 clock-names = "pix", "axi", "disp_axi";
1176 status = "disabled";
1179 vadc: vadc@02228000 {
1180 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1181 reg-names = "vadc-vafe", "vadc-vdec";
1182 clocks = <&clks IMX6SX_CLK_VADC>,
1183 <&clks IMX6SX_CLK_CSI>;
1184 clock-names = "vadc", "csi";
1185 status = "disabled";
1189 adc1: adc@02280000 {
1190 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1191 reg = <0x02280000 0x4000>;
1192 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&clks IMX6SX_CLK_IPG>;
1195 clock-names = "adc";
1196 status = "disabled";
1199 adc2: adc@02284000 {
1200 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1201 reg = <0x02284000 0x4000>;
1202 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6SX_CLK_IPG>;
1205 clock-names = "adc";
1206 status = "disabled";
1209 wdog3: wdog@02288000 {
1210 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1211 reg = <0x02288000 0x4000>;
1212 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX6SX_CLK_DUMMY>;
1214 status = "disabled";
1217 ecspi5: ecspi@0228c000 {
1218 #address-cells = <1>;
1220 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1221 reg = <0x0228c000 0x4000>;
1222 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1224 <&clks IMX6SX_CLK_ECSPI5>;
1225 clock-names = "ipg", "per";
1226 status = "disabled";
1229 uart6: serial@022a0000 {
1230 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1231 reg = <0x022a0000 0x4000>;
1232 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1234 <&clks IMX6SX_CLK_UART_SERIAL>;
1235 clock-names = "ipg", "per";
1236 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1237 dma-names = "rx", "tx";
1238 status = "disabled";
1241 pwm5: pwm@022a4000 {
1242 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1243 reg = <0x022a4000 0x4000>;
1244 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&clks IMX6SX_CLK_PWM5>,
1246 <&clks IMX6SX_CLK_PWM5>;
1247 clock-names = "ipg", "per";
1251 pwm6: pwm@022a8000 {
1252 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1253 reg = <0x022a8000 0x4000>;
1254 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&clks IMX6SX_CLK_PWM6>,
1256 <&clks IMX6SX_CLK_PWM6>;
1257 clock-names = "ipg", "per";
1261 pwm7: pwm@022ac000 {
1262 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1263 reg = <0x022ac000 0x4000>;
1264 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&clks IMX6SX_CLK_PWM7>,
1266 <&clks IMX6SX_CLK_PWM7>;
1267 clock-names = "ipg", "per";
1271 pwm8: pwm@0022b0000 {
1272 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1273 reg = <0x0022b0000 0x4000>;
1274 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&clks IMX6SX_CLK_PWM8>,
1276 <&clks IMX6SX_CLK_PWM8>;
1277 clock-names = "ipg", "per";
1282 pcie: pcie@0x08000000 {
1283 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1284 reg = <0x08ffc000 0x4000>; /* DBI */
1285 #address-cells = <3>;
1287 device_type = "pci";
1288 /* configuration space */
1289 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1290 /* downstream I/O */
1291 0x81000000 0 0 0x08f80000 0 0x00010000
1292 /* non-prefetchable memory */
1293 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1295 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1297 <&clks IMX6SX_CLK_PCIE_AXI>,
1298 <&clks IMX6SX_CLK_LVDS1_OUT>,
1299 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1300 clock-names = "pcie_ref_125m", "pcie_axi",
1301 "lvds_gate", "display_axi";
1302 status = "disabled";