arch/arm/boot/dts/imx6sx.dtsi

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6sx-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "imx6sx-pinfunc.h"
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 can0 = &flexcan1;
  18                 can1 = &flexcan2;
  19                 ethernet0 = &fec1;
  20                 ethernet1 = &fec2;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 serial5 = &uart6;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 spi4 = &ecspi5;
  47                 usbphy0 = &usbphy1;
  48                 usbphy1 = &usbphy2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu0: cpu@0 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <0>;
  59                         next-level-cache = <&L2>;
  60                         operating-points = <
  61                                 /* kHz    uV */
  62                                 996000  1250000
  63                                 792000  1175000
  64                                 396000  1075000
  65                         >;
  66                         fsl,soc-operating-points = <
  67                                 /* ARM kHz  SOC uV */
  68                                 996000      1175000
  69                                 792000      1175000
  70                                 396000      1175000
  71                         >;
  72                         clock-latency = <61036>; /* two CLK32 periods */
  73                         clocks = <&clks IMX6SX_CLK_ARM>,
  74                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  75                                  <&clks IMX6SX_CLK_STEP>,
  76                                  <&clks IMX6SX_CLK_PLL1_SW>,
  77                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  78                         clock-names = "arm", "pll2_pfd2_396m", "step",
  79                                       "pll1_sw", "pll1_sys";
  80                         arm-supply = <&reg_arm>;
  81                         soc-supply = <&reg_soc>;
  82                 };
  83         };
  84
  85         intc: interrupt-controller@00a01000 {
  86                 compatible = "arm,cortex-a9-gic";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x00a01000 0x1000>,
  90                       <0x00a00100 0x100>;
  91         };
  92
  93         clocks {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ckil: clock@0 {
  98                         compatible = "fixed-clock";
  99                         reg = <0>;
 100                         #clock-cells = <0>;
 101                         clock-frequency = <32768>;
 102                         clock-output-names = "ckil";
 103                 };
 104
 105                 osc: clock@1 {
 106                         compatible = "fixed-clock";
 107                         reg = <1>;
 108                         #clock-cells = <0>;
 109                         clock-frequency = <24000000>;
 110                         clock-output-names = "osc";
 111                 };
 112
 113                 ipp_di0: clock@2 {
 114                         compatible = "fixed-clock";
 115                         reg = <2>;
 116                         #clock-cells = <0>;
 117                         clock-frequency = <0>;
 118                         clock-output-names = "ipp_di0";
 119                 };
 120
 121                 ipp_di1: clock@3 {
 122                         compatible = "fixed-clock";
 123                         reg = <3>;
 124                         #clock-cells = <0>;
 125                         clock-frequency = <0>;
 126                         clock-output-names = "ipp_di1";
 127                 };
 128         };
 129
 130         soc {
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 compatible = "simple-bus";
 134                 interrupt-parent = <&intc>;
 135                 ranges;
 136
 137                 pmu {
 138                         compatible = "arm,cortex-a9-pmu";
 139                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 140                 };
 141
 142                 ocrams: sram@008f8000 {
 143                         compatible = "fsl,lpm-sram";
 144                         reg = <0x008f8000 0x4000>;
 145                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 146                 };
 147
 148                 ocram: sram@00900000 {
 149                         compatible = "mmio-sram";
 150                         reg = <0x00900000 0x20000>;
 151                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 152                 };
 153
 154                 L2: l2-cache@00a02000 {
 155                         compatible = "arm,pl310-cache";
 156                         reg = <0x00a02000 0x1000>;
 157                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 158                         cache-unified;
 159                         cache-level = <2>;
 160                         arm,tag-latency = <4 2 3>;
 161                         arm,data-latency = <4 2 3>;
 162                 };
 163
 164                 dma_apbh: dma-apbh@01804000 {
 165                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 166                         reg = <0x01804000 0x2000>;
 167                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 171                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 172                         #dma-cells = <1>;
 173                         dma-channels = <4>;
 174                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 175                 };
 176
 177                 gpmi: gpmi-nand@01806000{
 178                         compatible = "fsl,imx6sx-gpmi-nand";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 182                         reg-names = "gpmi-nand", "bch";
 183                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 184                         interrupt-names = "bch";
 185                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 186                                  <&clks IMX6SX_CLK_GPMI_APB>,
 187                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 188                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 189                                  <&clks IMX6SX_CLK_PER1_BCH>;
 190                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 191                                       "gpmi_bch_apb", "per1_bch";
 192                         dmas = <&dma_apbh 0>;
 193                         dma-names = "rx-tx";
 194                         status = "disabled";
 195                 };
 196
 197                 aips1: aips-bus@02000000 {
 198                         compatible = "fsl,aips-bus", "simple-bus";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         reg = <0x02000000 0x100000>;
 202                         ranges;
 203
 204                         spba-bus@02000000 {
 205                                 compatible = "fsl,spba-bus", "simple-bus";
 206                                 #address-cells = <1>;
 207                                 #size-cells = <1>;
 208                                 reg = <0x02000000 0x40000>;
 209                                 ranges;
 210
 211                                 spdif: spdif@02004000 {
 212                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 213                                         reg = <0x02004000 0x4000>;
 214                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 215                                         dmas = <&sdma 14 18 0>,
 216                                                <&sdma 15 18 0>;
 217                                         dma-names = "rx", "tx";
 218                                         clocks = <&clks IMX6SX_CLK_SPDIF>,
 219                                                  <&clks IMX6SX_CLK_OSC>,
 220                                                  <&clks IMX6SX_CLK_SPDIF>,
 221                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 222                                                  <&clks IMX6SX_CLK_IPG>,
 223                                                  <&clks 0>, <&clks 0>,
 224                                                  <&clks IMX6SX_CLK_SPBA>;
 225                                         clock-names = "core", "rxtx0",
 226                                                       "rxtx1", "rxtx2",
 227                                                       "rxtx3", "rxtx4",
 228                                                       "rxtx5", "rxtx6",
 229                                                       "rxtx7", "dma";
 230                                         status = "disabled";
 231                                 };
 232
 233                                 ecspi1: ecspi@02008000 {
 234                                         #address-cells = <1>;
 235                                         #size-cells = <0>;
 236                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 237                                         reg = <0x02008000 0x4000>;
 238                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 239                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 240                                                  <&clks IMX6SX_CLK_ECSPI1>;
 241                                         clock-names = "ipg", "per";
 242                                         status = "disabled";
 243                                 };
 244
 245                                 ecspi2: ecspi@0200c000 {
 246                                         #address-cells = <1>;
 247                                         #size-cells = <0>;
 248                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 249                                         reg = <0x0200c000 0x4000>;
 250                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 251                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 252                                                  <&clks IMX6SX_CLK_ECSPI2>;
 253                                         clock-names = "ipg", "per";
 254                                         status = "disabled";
 255                                 };
 256
 257                                 ecspi3: ecspi@02010000 {
 258                                         #address-cells = <1>;
 259                                         #size-cells = <0>;
 260                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 261                                         reg = <0x02010000 0x4000>;
 262                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 263                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 264                                                  <&clks IMX6SX_CLK_ECSPI3>;
 265                                         clock-names = "ipg", "per";
 266                                         status = "disabled";
 267                                 };
 268
 269                                 ecspi4: ecspi@02014000 {
 270                                         #address-cells = <1>;
 271                                         #size-cells = <0>;
 272                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 273                                         reg = <0x02014000 0x4000>;
 274                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 275                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 276                                                  <&clks IMX6SX_CLK_ECSPI4>;
 277                                         clock-names = "ipg", "per";
 278                                         status = "disabled";
 279                                 };
 280
 281                                 uart1: serial@02020000 {
 282                                         compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
 283                                         reg = <0x02020000 0x4000>;
 284                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 286                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 287                                         clock-names = "ipg", "per";
 288                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 289                                         dma-names = "rx", "tx";
 290                                         status = "disabled";
 291                                 };
 292
 293                                 esai: esai@02024000 {
 294                                         reg = <0x02024000 0x4000>;
 295                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 296                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 297                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 298                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 299                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 300                                                  <&clks IMX6SX_CLK_SPBA>;
 301                                         clock-names = "core", "mem", "extal",
 302                                                       "fsys", "dma";
 303                                         status = "disabled";
 304                                 };
 305
 306                                 ssi1: ssi@02028000 {
 307                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 308                                         reg = <0x02028000 0x4000>;
 309                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 310                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 311                                                  <&clks IMX6SX_CLK_SSI1>;
 312                                         clock-names = "ipg", "baud";
 313                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 314                                         dma-names = "rx", "tx";
 315                                         status = "disabled";
 316                                 };
 317
 318                                 ssi2: ssi@0202c000 {
 319                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 320                                         reg = <0x0202c000 0x4000>;
 321                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 322                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 323                                                  <&clks IMX6SX_CLK_SSI2>;
 324                                         clock-names = "ipg", "baud";
 325                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 326                                         dma-names = "rx", "tx";
 327                                         status = "disabled";
 328                                 };
 329
 330                                 ssi3: ssi@02030000 {
 331                                         compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
 332                                         reg = <0x02030000 0x4000>;
 333                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 334                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 335                                                  <&clks IMX6SX_CLK_SSI3>;
 336                                         clock-names = "ipg", "baud";
 337                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 338                                         dma-names = "rx", "tx";
 339                                         status = "disabled";
 340                                 };
 341
 342                                 asrc: asrc@02034000 {
 343                                         compatible = "fsl,imx53-asrc";
 344                                         reg = <0x02034000 0x4000>;
 345                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 346                                         clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
 347                                                 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
 348                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 349                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 350                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 351                                                 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
 352                                                 <&clks IMX6SX_CLK_SPBA>;
 353                                         clock-names = "mem", "ipg", "asrck_0",
 354                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 355                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 356                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 357                                                 "asrck_d", "asrck_e", "asrck_f", "dma";
 358                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 359                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 360                                         dma-names = "rxa", "rxb", "rxc",
 361                                                     "txa", "txb", "txc";
 362                                         fsl,asrc-rate  = <48000>;
 363                                         fsl,asrc-width = <16>;
 364                                         status = "okay";
 365                                 };
 366
 367                                 asrc_p2p: asrc_p2p {
 368                                         compatible = "fsl,imx6q-asrc-p2p";
 369                                         fsl,p2p-rate  = <48000>;
 370                                         fsl,p2p-width = <16>;
 371                                         fsl,asrc-dma-rx-events = <17 18 19>;
 372                                         fsl,asrc-dma-tx-events = <20 21 22>;
 373                                         status = "okay";
 374                                 };
 375                         };
 376
 377                         pwm1: pwm@02080000 {
 378                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 379                                 reg = <0x02080000 0x4000>;
 380                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 382                                          <&clks IMX6SX_CLK_PWM1>;
 383                                 clock-names = "ipg", "per";
 384                                 #pwm-cells = <2>;
 385                         };
 386
 387                         pwm2: pwm@02084000 {
 388                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 389                                 reg = <0x02084000 0x4000>;
 390                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 392                                          <&clks IMX6SX_CLK_PWM2>;
 393                                 clock-names = "ipg", "per";
 394                                 #pwm-cells = <2>;
 395                         };
 396
 397                         pwm3: pwm@02088000 {
 398                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 399                                 reg = <0x02088000 0x4000>;
 400                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 402                                          <&clks IMX6SX_CLK_PWM3>;
 403                                 clock-names = "ipg", "per";
 404                                 #pwm-cells = <2>;
 405                         };
 406
 407                         pwm4: pwm@0208c000 {
 408                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 409                                 reg = <0x0208c000 0x4000>;
 410                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 412                                          <&clks IMX6SX_CLK_PWM4>;
 413                                 clock-names = "ipg", "per";
 414                                 #pwm-cells = <2>;
 415                         };
 416
 417                         flexcan1: can@02090000 {
 418                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 419                                 reg = <0x02090000 0x4000>;
 420                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 422                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 423                                 clock-names = "ipg", "per";
 424                                 stop-mode = <&gpr 0x10 1 0x10 17>;
 425                                 status = "disabled";
 426                         };
 427
 428                         flexcan2: can@02094000 {
 429                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 430                                 reg = <0x02094000 0x4000>;
 431                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 432                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 433                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 434                                 clock-names = "ipg", "per";
 435                                 stop-mode = <&gpr 0x10 2 0x10 18>;
 436                                 status = "disabled";
 437                         };
 438
 439                         gpt: gpt@02098000 {
 440                                 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
 441                                 reg = <0x02098000 0x4000>;
 442                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 443                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 444                                          <&clks IMX6SX_CLK_GPT_SERIAL>;
 445                                 clock-names = "ipg", "per";
 446                         };
 447
 448                         gpio1: gpio@0209c000 {
 449                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 450                                 reg = <0x0209c000 0x4000>;
 451                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 452                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 453                                 gpio-controller;
 454                                 #gpio-cells = <2>;
 455                                 interrupt-controller;
 456                                 #interrupt-cells = <2>;
 457                         };
 458
 459                         gpio2: gpio@020a0000 {
 460                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 461                                 reg = <0x020a0000 0x4000>;
 462                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 464                                 gpio-controller;
 465                                 #gpio-cells = <2>;
 466                                 interrupt-controller;
 467                                 #interrupt-cells = <2>;
 468                         };
 469
 470                         gpio3: gpio@020a4000 {
 471                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 472                                 reg = <0x020a4000 0x4000>;
 473                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 474                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 475                                 gpio-controller;
 476                                 #gpio-cells = <2>;
 477                                 interrupt-controller;
 478                                 #interrupt-cells = <2>;
 479                         };
 480
 481                         gpio4: gpio@020a8000 {
 482                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 483                                 reg = <0x020a8000 0x4000>;
 484                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 485                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 486                                 gpio-controller;
 487                                 #gpio-cells = <2>;
 488                                 interrupt-controller;
 489                                 #interrupt-cells = <2>;
 490                         };
 491
 492                         gpio5: gpio@020ac000 {
 493                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 494                                 reg = <0x020ac000 0x4000>;
 495                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 496                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 497                                 gpio-controller;
 498                                 #gpio-cells = <2>;
 499                                 interrupt-controller;
 500                                 #interrupt-cells = <2>;
 501                         };
 502
 503                         gpio6: gpio@020b0000 {
 504                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 505                                 reg = <0x020b0000 0x4000>;
 506                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 508                                 gpio-controller;
 509                                 #gpio-cells = <2>;
 510                                 interrupt-controller;
 511                                 #interrupt-cells = <2>;
 512                         };
 513
 514                         gpio7: gpio@020b4000 {
 515                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 516                                 reg = <0x020b4000 0x4000>;
 517                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 519                                 gpio-controller;
 520                                 #gpio-cells = <2>;
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <2>;
 523                         };
 524
 525                         kpp: kpp@020b8000 {
 526                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 527                                 reg = <0x020b8000 0x4000>;
 528                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 529                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 530                                 status = "disabled";
 531                         };
 532
 533                         wdog1: wdog@020bc000 {
 534                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 535                                 reg = <0x020bc000 0x4000>;
 536                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 537                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 538                         };
 539
 540                         wdog2: wdog@020c0000 {
 541                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 542                                 reg = <0x020c0000 0x4000>;
 543                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 544                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
 545                                 status = "disabled";
 546                         };
 547
 548                         clks: ccm@020c4000 {
 549                                 compatible = "fsl,imx6sx-ccm";
 550                                 reg = <0x020c4000 0x4000>;
 551                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 552                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 553                                 #clock-cells = <1>;
 554                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 555                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 556                         };
 557
 558                         anatop: anatop@020c8000 {
 559                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 560                                              "syscon", "simple-bus";
 561                                 reg = <0x020c8000 0x1000>;
 562                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 563                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 564                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 565
 566                                 regulator-1p1@110 {
 567                                         compatible = "fsl,anatop-regulator";
 568                                         regulator-name = "vdd1p1";
 569                                         regulator-min-microvolt = <800000>;
 570                                         regulator-max-microvolt = <1375000>;
 571                                         regulator-always-on;
 572                                         anatop-reg-offset = <0x110>;
 573                                         anatop-vol-bit-shift = <8>;
 574                                         anatop-vol-bit-width = <5>;
 575                                         anatop-min-bit-val = <4>;
 576                                         anatop-min-voltage = <800000>;
 577                                         anatop-max-voltage = <1375000>;
 578                                 };
 579
 580                                 regulator-3p0@120 {
 581                                         compatible = "fsl,anatop-regulator";
 582                                         regulator-name = "vdd3p0";
 583                                         regulator-min-microvolt = <2800000>;
 584                                         regulator-max-microvolt = <3150000>;
 585                                         regulator-always-on;
 586                                         anatop-reg-offset = <0x120>;
 587                                         anatop-vol-bit-shift = <8>;
 588                                         anatop-vol-bit-width = <5>;
 589                                         anatop-min-bit-val = <0>;
 590                                         anatop-min-voltage = <2625000>;
 591                                         anatop-max-voltage = <3400000>;
 592                                 };
 593
 594                                 regulator-2p5@130 {
 595                                         compatible = "fsl,anatop-regulator";
 596                                         regulator-name = "vdd2p5";
 597                                         regulator-min-microvolt = <2100000>;
 598                                         regulator-max-microvolt = <2875000>;
 599                                         regulator-always-on;
 600                                         anatop-reg-offset = <0x130>;
 601                                         anatop-vol-bit-shift = <8>;
 602                                         anatop-vol-bit-width = <5>;
 603                                         anatop-min-bit-val = <0>;
 604                                         anatop-min-voltage = <2100000>;
 605                                         anatop-max-voltage = <2875000>;
 606                                 };
 607
 608                                 reg_arm: regulator-vddcore@140 {
 609                                         compatible = "fsl,anatop-regulator";
 610                                         regulator-name = "cpu";
 611                                         regulator-min-microvolt = <725000>;
 612                                         regulator-max-microvolt = <1450000>;
 613                                         regulator-always-on;
 614                                         anatop-reg-offset = <0x140>;
 615                                         anatop-vol-bit-shift = <0>;
 616                                         anatop-vol-bit-width = <5>;
 617                                         anatop-delay-reg-offset = <0x170>;
 618                                         anatop-delay-bit-shift = <24>;
 619                                         anatop-delay-bit-width = <2>;
 620                                         anatop-min-bit-val = <1>;
 621                                         anatop-min-voltage = <725000>;
 622                                         anatop-max-voltage = <1450000>;
 623                                 };
 624
 625                                 reg_pcie: regulator-vddpcie@140 {
 626                                         compatible = "fsl,anatop-regulator";
 627                                         regulator-name = "vddpcie";
 628                                         regulator-min-microvolt = <725000>;
 629                                         regulator-max-microvolt = <1450000>;
 630                                         anatop-reg-offset = <0x140>;
 631                                         anatop-vol-bit-shift = <9>;
 632                                         anatop-vol-bit-width = <5>;
 633                                         anatop-delay-reg-offset = <0x170>;
 634                                         anatop-delay-bit-shift = <26>;
 635                                         anatop-delay-bit-width = <2>;
 636                                         anatop-min-bit-val = <1>;
 637                                         anatop-min-voltage = <725000>;
 638                                         anatop-max-voltage = <1450000>;
 639                                 };
 640
 641                                 reg_soc: regulator-vddsoc@140 {
 642                                         compatible = "fsl,anatop-regulator";
 643                                         regulator-name = "vddsoc";
 644                                         regulator-min-microvolt = <725000>;
 645                                         regulator-max-microvolt = <1450000>;
 646                                         regulator-always-on;
 647                                         anatop-reg-offset = <0x140>;
 648                                         anatop-vol-bit-shift = <18>;
 649                                         anatop-vol-bit-width = <5>;
 650                                         anatop-delay-reg-offset = <0x170>;
 651                                         anatop-delay-bit-shift = <28>;
 652                                         anatop-delay-bit-width = <2>;
 653                                         anatop-min-bit-val = <1>;
 654                                         anatop-min-voltage = <725000>;
 655                                         anatop-max-voltage = <1450000>;
 656                                 };
 657                         };
 658
 659                         tempmon: tempmon {
 660                                 compatible = "fsl,imx6sx-tempmon";
 661                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 662                                 fsl,tempmon = <&anatop>;
 663                                 fsl,tempmon-data = <&ocotp>;
 664                                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 665                         };
 666
 667                         usbphy1: usbphy@020c9000 {
 668                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 669                                 reg = <0x020c9000 0x1000>;
 670                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 672                                 fsl,anatop = <&anatop>;
 673                         };
 674
 675                         usbphy2: usbphy@020ca000 {
 676                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 677                                 reg = <0x020ca000 0x1000>;
 678                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 679                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 680                                 fsl,anatop = <&anatop>;
 681                         };
 682
 683                         snvs: snvs@020cc000 {
 684                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 685                                 #address-cells = <1>;
 686                                 #size-cells = <1>;
 687                                 ranges = <0 0x020cc000 0x4000>;
 688
 689                                 snvs-rtc-lp@34 {
 690                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 691                                         reg = <0x34 0x58>;
 692                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 693                                 };
 694                         };
 695
 696                         epit1: epit@020d0000 {
 697                                 reg = <0x020d0000 0x4000>;
 698                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 699                         };
 700
 701                         epit2: epit@020d4000 {
 702                                 reg = <0x020d4000 0x4000>;
 703                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 704                         };
 705
 706                         src: src@020d8000 {
 707                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 708                                 reg = <0x020d8000 0x4000>;
 709                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 710                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 711                                 #reset-cells = <1>;
 712                         };
 713
 714                         gpc: gpc@020dc000 {
 715                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 716                                 reg = <0x020dc000 0x4000>;
 717                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 718                                 fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400200>;
 719                         };
 720
 721                         iomuxc: iomuxc@020e0000 {
 722                                 compatible = "fsl,imx6sx-iomuxc";
 723                                 reg = <0x020e0000 0x4000>;
 724                         };
 725
 726                         gpr: iomuxc-gpr@020e4000 {
 727                                 compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
 728                                 reg = <0x020e4000 0x4000>;
 729                         };
 730
 731                         canfd1: canfd@020e8000 {
 732                                 compatible = "bosch,m_can";
 733                                 reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
 734                                 reg-names = "canfd", "message_ram";
 735                                 interrupts = <0 114 0x04>;
 736                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 737                                 mram-cfg = <0x0 0 0 32 0 0 0 1>;
 738                                 status = "disabled";
 739                         };
 740
 741                         canfd2: canfd@020f0000 {
 742                                 compatible = "bosch,m_can";
 743                                 reg = <0x020f0000 0x4000>, <0x02298000 0x4000>;
 744                                 reg-names = "canfd", "message_ram";
 745                                 interrupts = <0 115 0x04>;
 746                                 clocks = <&clks IMX6SX_CLK_CANFD>;
 747                                 mram-cfg = <0x400 0 0 32 0 0 0 1>;
 748                                 status = "disabled";
 749                         };
 750
 751                         ldb: ldb@020e0014 {
 752                                 #address-cells = <1>;
 753                                 #size-cells = <0>;
 754                                 compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
 755                                 gpr = <&gpr>;
 756                                 status = "disabled";
 757
 758                                 clocks = <&clks IMX6SX_CLK_LDB_DI0>,
 759                                          <&clks IMX6SX_CLK_LCDIF1_SEL>,
 760                                          <&clks IMX6SX_CLK_LCDIF2_SEL>,
 761                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
 762                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
 763                                          <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
 764                                 clock-names = "ldb_di0",
 765                                               "di0_sel",
 766                                               "di1_sel",
 767                                               "ldb_di0_div_3_5",
 768                                               "ldb_di0_div_7",
 769                                               "ldb_di0_div_sel";
 770
 771                                 lvds-channel@0 {
 772                                         reg = <0>;
 773                                         status = "disabled";
 774                                 };
 775                         };
 776
 777                         sdma: sdma@020ec000 {
 778                                 compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
 779                                 reg = <0x020ec000 0x4000>;
 780                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 781                                 clocks = <&clks IMX6SX_CLK_SDMA>,
 782                                          <&clks IMX6SX_CLK_SDMA>;
 783                                 clock-names = "ipg", "ahb";
 784                                 #dma-cells = <3>;
 785                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 786                         };
 787                 };
 788
 789                 aips2: aips-bus@02100000 {
 790                         compatible = "fsl,aips-bus", "simple-bus";
 791                         #address-cells = <1>;
 792                         #size-cells = <1>;
 793                         reg = <0x02100000 0x100000>;
 794                         ranges;
 795
 796                         usbotg1: usb@02184000 {
 797                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 798                                 reg = <0x02184000 0x200>;
 799                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 800                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 801                                 fsl,usbphy = <&usbphy1>;
 802                                 fsl,usbmisc = <&usbmisc 0>;
 803                                 fsl,anatop = <&anatop>;
 804                                 status = "disabled";
 805                         };
 806
 807                         usbotg2: usb@02184200 {
 808                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 809                                 reg = <0x02184200 0x200>;
 810                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 811                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 812                                 fsl,usbphy = <&usbphy2>;
 813                                 fsl,usbmisc = <&usbmisc 1>;
 814                                 status = "disabled";
 815                         };
 816
 817                         usbh: usb@02184400 {
 818                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 819                                 reg = <0x02184400 0x200>;
 820                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 822                                 fsl,usbmisc = <&usbmisc 2>;
 823                                 phy_type = "hsic";
 824                                 fsl,anatop = <&anatop>;
 825                                 status = "disabled";
 826                         };
 827
 828                         usbmisc: usbmisc@02184800 {
 829                                 #index-cells = <1>;
 830                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 831                                 reg = <0x02184800 0x200>;
 832                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 833                         };
 834
 835                         fec1: ethernet@02188000 {
 836                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 837                                 reg = <0x02188000 0x4000>;
 838                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 839                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX6SX_CLK_ENET>,
 841                                          <&clks IMX6SX_CLK_ENET_AHB>,
 842                                          <&clks IMX6SX_CLK_ENET_PTP>,
 843                                          <&clks IMX6SX_CLK_ENET_REF>,
 844                                          <&clks IMX6SX_CLK_ENET_PTP>;
 845                                 clock-names = "ipg", "ahb", "ptp",
 846                                               "enet_clk_ref", "enet_out";
 847                                 fsl,num-tx-queues=<3>;
 848                                 fsl,num-rx-queues=<3>;
 849                                 status = "disabled";
 850                         };
 851
 852                         mlb: mlb@0218c000 {
 853                                 reg = <0x0218c000 0x4000>;
 854                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 855                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 856                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 857                                 clocks = <&clks IMX6SX_CLK_MLB>;
 858                                 status = "disabled";
 859                         };
 860
 861                         usdhc1: usdhc@02190000 {
 862                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 863                                 reg = <0x02190000 0x4000>;
 864                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 866                                          <&clks IMX6SX_CLK_USDHC1>,
 867                                          <&clks IMX6SX_CLK_USDHC1>;
 868                                 clock-names = "ipg", "ahb", "per";
 869                                 bus-width = <4>;
 870                                 status = "disabled";
 871                         };
 872
 873                         usdhc2: usdhc@02194000 {
 874                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 875                                 reg = <0x02194000 0x4000>;
 876                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 878                                          <&clks IMX6SX_CLK_USDHC2>,
 879                                          <&clks IMX6SX_CLK_USDHC2>;
 880                                 clock-names = "ipg", "ahb", "per";
 881                                 bus-width = <4>;
 882                                 status = "disabled";
 883                         };
 884
 885                         usdhc3: usdhc@02198000 {
 886                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 887                                 reg = <0x02198000 0x4000>;
 888                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 890                                          <&clks IMX6SX_CLK_USDHC3>,
 891                                          <&clks IMX6SX_CLK_USDHC3>;
 892                                 clock-names = "ipg", "ahb", "per";
 893                                 bus-width = <4>;
 894                                 status = "disabled";
 895                         };
 896
 897                         usdhc4: usdhc@0219c000 {
 898                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 899                                 reg = <0x0219c000 0x4000>;
 900                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 902                                          <&clks IMX6SX_CLK_USDHC4>,
 903                                          <&clks IMX6SX_CLK_USDHC4>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 bus-width = <4>;
 906                                 status = "disabled";
 907                         };
 908
 909                         i2c1: i2c@021a0000 {
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 913                                 reg = <0x021a0000 0x4000>;
 914                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks IMX6SX_CLK_I2C1>;
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c2: i2c@021a4000 {
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 923                                 reg = <0x021a4000 0x4000>;
 924                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 925                                 clocks = <&clks IMX6SX_CLK_I2C2>;
 926                                 status = "disabled";
 927                         };
 928
 929                         i2c3: i2c@021a8000 {
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 933                                 reg = <0x021a8000 0x4000>;
 934                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks IMX6SX_CLK_I2C3>;
 936                                 status = "disabled";
 937                         };
 938
 939                         mmdc: mmdc@021b0000 {
 940                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
 941                                 reg = <0x021b0000 0x4000>;
 942                         };
 943
 944                         fec2: ethernet@021b4000 {
 945                                 compatible = "fsl,imx6sx-fec";
 946                                 reg = <0x021b4000 0x4000>;
 947                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 948                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 949                                 clocks = <&clks IMX6SX_CLK_ENET>,
 950                                          <&clks IMX6SX_CLK_ENET_AHB>,
 951                                          <&clks IMX6SX_CLK_ENET_PTP>,
 952                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
 953                                          <&clks IMX6SX_CLK_ENET_PTP>;
 954                                 clock-names = "ipg", "ahb", "ptp",
 955                                               "enet_clk_ref", "enet_out";
 956                                 status = "disabled";
 957                         };
 958
 959                         weim: weim@021b8000 {
 960                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
 961                                 reg = <0x021b8000 0x4000>;
 962                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 963                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
 964                         };
 965
 966                         ocotp: ocotp-ctrl@021bc000 {
 967                                 compatible = "syscon";
 968                                 reg = <0x021bc000 0x4000>;
 969                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 970                         };
 971
 972                         ocotp-fuse@021bc000 {
 973                                 compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
 974                                 reg = <0x021bc000 0x4000>;
 975                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
 976                         };
 977
 978                         sai1: sai@021d4000 {
 979                                 compatible = "fsl,imx6sx-sai";
 980                                 reg = <0x021d4000 0x4000>;
 981                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 982                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
 983                                          <&clks IMX6SX_CLK_SAI1>,
 984                                          <&clks 0>, <&clks 0>;
 985                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 986                                 dma-names = "rx", "tx";
 987                                 dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
 988                                 dma-source = <&gpr 0 15 0 16>;
 989                                 status = "disabled";
 990                         };
 991
 992                         audmux: audmux@021d8000 {
 993                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
 994                                 reg = <0x021d8000 0x4000>;
 995                                 status = "disabled";
 996                         };
 997
 998                         sai2: sai@021dc000 {
 999                                 compatible = "fsl,imx6sx-sai";
1000                                 reg = <0x021dc000 0x4000>;
1001                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1002                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1003                                          <&clks IMX6SX_CLK_SAI2>,
1004                                          <&clks 0>, <&clks 0>;
1005                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1006                                 dma-names = "rx", "tx";
1007                                 dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
1008                                 dma-source = <&gpr 0 17 0 18>;
1009                                 status = "disabled";
1010                         };
1011
1012                         qspi1: qspi@021e0000 {
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                                 compatible = "fsl,imx6sx-qspi";
1016                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1017                                 reg-names = "QuadSPI", "QuadSPI-memory";
1018                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1019                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1020                                          <&clks IMX6SX_CLK_QSPI1>;
1021                                 clock-names = "qspi_en", "qspi";
1022                                 status = "disabled";
1023                         };
1024
1025                         qspi2: qspi@021e4000 {
1026                                 #address-cells = <1>;
1027                                 #size-cells = <0>;
1028                                 compatible = "fsl,imx6sx-qspi";
1029                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1030                                 reg-names = "QuadSPI", "QuadSPI-memory";
1031                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1032                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1033                                          <&clks IMX6SX_CLK_QSPI2>;
1034                                 clock-names = "qspi_en", "qspi";
1035                                 status = "disabled";
1036                         };
1037
1038                         uart2: serial@021e8000 {
1039                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1040                                 reg = <0x021e8000 0x4000>;
1041                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1042                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1043                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1044                                 clock-names = "ipg", "per";
1045                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1046                                 dma-names = "rx", "tx";
1047                                 status = "disabled";
1048                         };
1049
1050                         uart3: serial@021ec000 {
1051                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1052                                 reg = <0x021ec000 0x4000>;
1053                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1054                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1055                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1056                                 clock-names = "ipg", "per";
1057                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1058                                 dma-names = "rx", "tx";
1059                                 status = "disabled";
1060                         };
1061
1062                         uart4: serial@021f0000 {
1063                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1064                                 reg = <0x021f0000 0x4000>;
1065                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1066                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1067                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1068                                 clock-names = "ipg", "per";
1069                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1070                                 dma-names = "rx", "tx";
1071                                 status = "disabled";
1072                         };
1073
1074                         uart5: serial@021f4000 {
1075                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1076                                 reg = <0x021f4000 0x4000>;
1077                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1078                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1079                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1080                                 clock-names = "ipg", "per";
1081                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1082                                 dma-names = "rx", "tx";
1083                                 status = "disabled";
1084                         };
1085
1086                         i2c4: i2c@021f8000 {
1087                                 #address-cells = <1>;
1088                                 #size-cells = <0>;
1089                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1090                                 reg = <0x021f8000 0x4000>;
1091                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1092                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1093                                 status = "disabled";
1094                         };
1095                 };
1096
1097                 aips3: aips-bus@02200000 {
1098                         compatible = "fsl,aips-bus", "simple-bus";
1099                         #address-cells = <1>;
1100                         #size-cells = <1>;
1101                         reg = <0x02200000 0x100000>;
1102                         ranges;
1103
1104                         spba-bus@02200000 {
1105                                 compatible = "fsl,spba-bus", "simple-bus";
1106                                 #address-cells = <1>;
1107                                 #size-cells = <1>;
1108                                 reg = <0x02240000 0x40000>;
1109                                 ranges;
1110
1111                                 dcic1: dcic@0220c000 {
1112                                         compatible = "fsl,imx6sx-dcic";
1113                                         reg = <0x0220c000 0x4000>;
1114                                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1115                                         clocks = <&clks IMX6SX_CLK_DCIC1>,
1116                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1117                                         clock-names = "dcic", "disp-axi";
1118                                         gpr = <&gpr>;
1119                                         status = "disabled";
1120                                 };
1121
1122                                 dcic2: dcic@02210000 {
1123                                         compatible = "fsl,imx6sx-dcic";
1124                                         reg = <0x02210000 0x4000>;
1125                                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1126                                         clocks = <&clks IMX6SX_CLK_DCIC2>,
1127                                                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1128                                         clock-names = "dcic", "disp-axi";
1129                                         gpr = <&gpr>;
1130                                         status = "disabled";
1131                                 };
1132
1133                                 csi1: csi@02214000 {
1134                                         reg = <0x02214000 0x4000>;
1135                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1136                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1137                                                  <&clks IMX6SX_CLK_CSI>,
1138                                                  <&clks IMX6SX_CLK_DCIC1>;
1139                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1140                                         status = "disabled";
1141                                 };
1142
1143                                 pxp: pxp@02218000 {
1144                                         compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
1145                                         reg = <0x02218000 0x4000>;
1146                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1147                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1148                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1149                                         clock-names = "pxp-axi", "disp-axi";
1150                                         status = "disabled";
1151                                 };
1152
1153                                 csi2: csi@0221c000 {
1154                                         reg = <0x0221c000 0x4000>;
1155                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1156                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1157                                                  <&clks IMX6SX_CLK_CSI>,
1158                                                  <&clks IMX6SX_CLK_DCIC2>;
1159                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1160                                         status = "disabled";
1161                                 };
1162
1163                                 lcdif1: lcdif@02220000 {
1164                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1165                                         reg = <0x02220000 0x4000>;
1166                                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1167                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1168                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1169                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1170                                         clock-names = "pix", "axi", "disp_axi";
1171                                         status = "disabled";
1172                                 };
1173
1174                                 lcdif2: lcdif@02224000 {
1175                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1176                                         reg = <0x02224000 0x4000>;
1177                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1178                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1179                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1180                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1181                                         clock-names = "pix", "axi", "disp_axi";
1182                                         status = "disabled";
1183                                 };
1184
1185                                 vadc: vadc@02228000 {
1186                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1187                                         reg-names = "vadc-vafe", "vadc-vdec";
1188                                         clocks = <&clks IMX6SX_CLK_VADC>,
1189                                                  <&clks IMX6SX_CLK_CSI>;
1190                                         clock-names = "vadc", "csi";
1191                                         status = "disabled";
1192                                 };
1193                         };
1194
1195                         adc1: adc@02280000 {
1196                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1197                                 reg = <0x02280000 0x4000>;
1198                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1199                                 clocks = <&clks IMX6SX_CLK_IPG>;
1200                                 num-channels = <4>;
1201                                 clock-names = "adc";
1202                                 status = "disabled";
1203                         };
1204
1205                         adc2: adc@02284000 {
1206                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1207                                 reg = <0x02284000 0x4000>;
1208                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1209                                 clocks = <&clks IMX6SX_CLK_IPG>;
1210                                 num-channels = <4>;
1211                                 clock-names = "adc";
1212                                 status = "disabled";
1213                         };
1214
1215                         wdog3: wdog@02288000 {
1216                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1217                                 reg = <0x02288000 0x4000>;
1218                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1219                                 clocks = <&clks IMX6SX_CLK_DUMMY>;
1220                                 status = "disabled";
1221                         };
1222
1223                         ecspi5: ecspi@0228c000 {
1224                                 #address-cells = <1>;
1225                                 #size-cells = <0>;
1226                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1227                                 reg = <0x0228c000 0x4000>;
1228                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1229                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1230                                          <&clks IMX6SX_CLK_ECSPI5>;
1231                                 clock-names = "ipg", "per";
1232                                 status = "disabled";
1233                         };
1234
1235                         uart6: serial@022a0000 {
1236                                 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1237                                 reg = <0x022a0000 0x4000>;
1238                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1239                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1240                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1241                                 clock-names = "ipg", "per";
1242                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1243                                 dma-names = "rx", "tx";
1244                                 status = "disabled";
1245                         };
1246
1247                         pwm5: pwm@022a4000 {
1248                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1249                                 reg = <0x022a4000 0x4000>;
1250                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1251                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1252                                          <&clks IMX6SX_CLK_PWM5>;
1253                                 clock-names = "ipg", "per";
1254                                 #pwm-cells = <2>;
1255                         };
1256
1257                         pwm6: pwm@022a8000 {
1258                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1259                                 reg = <0x022a8000 0x4000>;
1260                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1261                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1262                                          <&clks IMX6SX_CLK_PWM6>;
1263                                 clock-names = "ipg", "per";
1264                                 #pwm-cells = <2>;
1265                         };
1266
1267                         pwm7: pwm@022ac000 {
1268                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1269                                 reg = <0x022ac000 0x4000>;
1270                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1271                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1272                                          <&clks IMX6SX_CLK_PWM7>;
1273                                 clock-names = "ipg", "per";
1274                                 #pwm-cells = <2>;
1275                         };
1276
1277                         pwm8: pwm@0022b0000 {
1278                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1279                                 reg = <0x0022b0000 0x4000>;
1280                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1281                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1282                                          <&clks IMX6SX_CLK_PWM8>;
1283                                 clock-names = "ipg", "per";
1284                                 #pwm-cells = <2>;
1285                         };
1286                 };
1287
1288                 pcie: pcie@0x08000000 {
1289                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1290                         reg = <0x08ffc000 0x4000>; /* DBI */
1291                         #address-cells = <3>;
1292                         #size-cells = <2>;
1293                         device_type = "pci";
1294                                   /* configuration space */
1295                         ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1296                                   /* downstream I/O */
1297                                   0x81000000 0 0          0x08f80000 0 0x00010000
1298                                   /* non-prefetchable memory */
1299                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1300                         num-lanes = <1>;
1301                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1302                         clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1303                                  <&clks IMX6SX_CLK_PCIE_AXI>,
1304                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1305                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1306                         clock-names = "pcie_ref_125m", "pcie_axi",
1307                                       "lvds_gate", "display_axi";
1308                         status = "disabled";
1309                 };
1310         };
1311 };