2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
11 #include "imx6ul.dtsi"
14 model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
15 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
22 reg = <0x80000000 0x20000000>;
26 compatible = "pwm-backlight";
27 pwms = <&pwm1 0 5000000>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <6>;
34 compatible = "simple-bus";
38 reg_sd1_vmmc: sd1_regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "VSD_3V3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
49 compatible = "simple-audio-card";
50 simple-audio-card,name = "mx6ul-wm8960";
51 simple-audio-card,format = "i2s";
52 simple-audio-card,bitclock-master = <&dailink_master>;
53 simple-audio-card,frame-master = <&dailink_master>;
54 simple-audio-card,widgets =
55 "Microphone", "Mic Jack",
59 "Headphone", "Headphone Jack";
60 simple-audio-card,routing =
61 "Headphone Jack", "HP_L",
62 "Headphone Jack", "HP_R",
67 "LINPUT1", "Mic Jack",
68 "LINPUT3", "Mic Jack",
69 "RINPUT1", "Mic Jack",
70 "RINPUT2", "Mic Jack";
72 simple-audio-card,cpu {
76 dailink_master: simple-audio-card,codec {
78 clocks = <&clks IMX6UL_CLK_SAI2>;
84 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
85 assigned-clock-rates = <786432000>;
89 clock_frequency = <100000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_i2c2>;
95 #sound-dai-cells = <0>;
96 compatible = "wlf,wm8960";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_enet1>;
106 phy-handle = <ðphy0>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_enet2>;
114 phy-handle = <ðphy1>;
118 #address-cells = <1>;
121 ethphy0: ethernet-phy@2 {
125 ethphy1: ethernet-phy@1 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_lcdif_dat
135 &pinctrl_lcdif_ctrl>;
136 display = <&display0>;
140 bits-per-pixel = <16>;
144 native-mode = <&timing0>;
147 clock-frequency = <9200000>;
159 pixelclk-active = <0>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_pwm1>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_qspi>;
177 #address-cells = <1>;
179 compatible = "micron,n25q256a";
180 spi-max-frequency = <29000000>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_sai2>;
188 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
189 <&clks IMX6UL_CLK_SAI2>;
190 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
191 assigned-clock-rates = <0>, <12288000>;
192 fsl,sai-mclk-direction-output;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_tsc>;
203 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
204 measure-delay-time = <0xffff>;
205 pre-charge-time = <0xfff>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_uart1>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart2>;
229 disable-over-current;
234 fsl,tx-d-cal = <106>;
238 fsl,tx-d-cal = <106>;
242 pinctrl-names = "default", "state_100mhz", "state_200mhz";
243 pinctrl-0 = <&pinctrl_usdhc1>;
244 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
245 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
246 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
247 keep-power-in-suspend;
249 vmmc-supply = <®_sd1_vmmc>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_usdhc2>;
257 keep-power-in-suspend;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_wdog>;
265 fsl,ext-reset-output;
269 pinctrl-names = "default";
271 pinctrl_csi1: csi1grp {
273 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
274 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
275 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
276 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
277 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
278 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
279 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
280 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
281 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
282 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
283 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
284 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
288 pinctrl_enet1: enet1grp {
290 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
291 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
292 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
293 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
294 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
295 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
296 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
297 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
301 pinctrl_enet2: enet2grp {
303 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
304 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
305 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
306 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
307 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
308 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
309 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
310 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
311 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
312 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
313 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
317 pinctrl_flexcan1: flexcan1grp{
319 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
320 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
324 pinctrl_flexcan2: flexcan2grp{
326 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
327 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
331 pinctrl_i2c1: i2c1grp {
333 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
334 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
338 pinctrl_i2c2: i2c2grp {
340 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
341 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
345 pinctrl_lcdif_dat: lcdifdatgrp {
347 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
348 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
349 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
350 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
351 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
352 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
353 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
354 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
355 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
356 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
357 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
358 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
359 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
360 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
361 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
362 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
363 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
364 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
365 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
366 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
367 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
368 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
369 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
370 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
374 pinctrl_lcdif_ctrl: lcdifctrlgrp {
376 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
377 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
378 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
379 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
380 /* used for lcd reset */
381 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
385 pinctrl_qspi: qspigrp {
387 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
388 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
389 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
390 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
391 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
392 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
396 pinctrl_sai2: sai2grp {
398 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
399 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
400 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
401 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
402 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
403 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
407 pinctrl_pwm1: pwm1grp {
409 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
413 pinctrl_sim2: sim2grp {
415 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
416 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
417 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
418 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
419 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
420 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
424 pinctrl_tsc: tscgrp {
426 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
427 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
428 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
429 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
433 pinctrl_uart1: uart1grp {
435 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
436 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
440 pinctrl_uart2: uart2grp {
442 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
443 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
444 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
445 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
449 pinctrl_usdhc1: usdhc1grp {
451 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
452 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
453 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
454 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
455 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
456 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
457 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
458 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
459 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
463 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
465 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
466 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
467 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
468 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
469 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
470 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
475 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
477 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
478 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
479 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
480 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
481 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
482 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
486 pinctrl_usdhc2: usdhc2grp {
488 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
489 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
490 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
491 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
492 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
493 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
497 pinctrl_wdog: wdoggrp {
499 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0