2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/gpio/gpio.h>
44 #include <dt-bindings/input/input.h>
45 #include "imx6ul.dtsi"
49 reg = <0x80000000 0x08000000>;
53 compatible = "pwm-backlight";
54 pwms = <&pwm8 0 100000>;
55 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
56 10 11 12 13 14 15 16 17 18 19
57 20 21 22 23 24 25 26 27 28 29
58 30 31 32 33 34 35 36 37 38 39
59 40 41 42 43 44 45 46 47 48 49
60 50 51 52 53 54 55 56 57 58 59
61 60 61 62 63 64 65 66 67 68 69
62 70 71 72 73 74 75 76 77 78 79
63 80 81 82 83 84 85 86 87 88 89
64 90 91 92 93 94 95 96 97 98 99
66 default-brightness-level = <100>;
73 reg_1p8v: regulator-1p8v {
74 compatible = "regulator-fixed";
75 regulator-name = "1P8V";
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <1800000>;
82 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed";
84 regulator-name = "3P3V";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_flexcan1>;
95 xceiver-supply = <®_3p3v>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_flexcan2>;
101 xceiver-supply = <®_3p3v>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_enet1>;
108 phy-handle = <ðphy0>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_enet2>;
116 phy-handle = <ðphy1>;
120 #address-cells = <1>;
123 ethphy0: ethernet-phy@0 {
124 compatible = "ethernet-phy-ieee802.3-c22";
128 ethphy1: ethernet-phy@1 {
129 compatible = "ethernet-phy-ieee802.3-c22";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_gpmi_nand>;
143 clock-frequency = <100000>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_i2c1>;
150 clock_frequency = <100000>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c2>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_lcdif_dat
159 &pinctrl_lcdif_ctrl>;
160 display = <&display0>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_pwm8>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_tsc>;
172 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_sai2>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_uart1>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_uart2>;
194 dr_mode = "peripheral";
204 pinctrl-names = "default", "state_100mhz", "state_200mhz";
205 pinctrl-0 = <&pinctrl_usdhc1>;
206 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
207 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
209 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
215 pinctrl_enet1: enet1grp {
217 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
218 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
219 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
220 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
221 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
222 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
223 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
227 pinctrl_enet2: enet2grp {
229 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
230 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
231 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
232 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
233 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
234 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
235 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
236 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
237 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
238 MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
242 pinctrl_flexcan1: flexcan1grp {
244 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
245 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
249 pinctrl_flexcan2: flexcan2grp {
251 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
252 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
256 pinctrl_gpmi_nand: gpmi-nand {
258 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
259 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
260 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
261 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
262 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
263 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
264 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
265 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
266 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
267 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
268 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
269 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
270 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
271 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
272 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
276 pinctrl_i2c1: i2c1grp {
278 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
279 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
283 pinctrl_i2c2: i2c2grp {
285 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
286 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
290 pinctrl_lcdif_ctrl: lcdifctrlgrp {
292 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
293 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
294 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
295 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
299 pinctrl_lcdif_dat: lcdifdatgrp {
301 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
302 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
303 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
304 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
305 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
306 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
307 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
308 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
309 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
310 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
311 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
312 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
313 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
314 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
315 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
316 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
317 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
318 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
322 pinctrl_pwm8: pwm8grp {
324 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
328 pinctrl_tsc: tscgrp {
330 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
331 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
332 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
333 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
337 pinctrl_sai2: sai2grp {
339 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
340 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
341 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
342 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
343 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
347 pinctrl_uart1: uart1grp {
349 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
350 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
354 pinctrl_uart2: uart2grp {
356 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
357 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
358 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
359 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
363 pinctrl_usdhc1: usdhc1grp {
365 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
366 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
367 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
368 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
369 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
370 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
374 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
376 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
377 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
378 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
379 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
380 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
381 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
385 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
387 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
388 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
389 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
390 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
391 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
392 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
396 pinctrl_usdhc2: usdhc2grp {
398 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
399 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
400 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
401 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
402 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
403 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070