arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         aliases {
  18                 ethernet0 = &fec1;
  19                 ethernet1 = &fec2;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42                 spi3 = &ecspi4;
  43                 usbphy0 = &usbphy1;
  44                 usbphy1 = &usbphy2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <0>;
  55                         clock-latency = <61036>; /* two CLK32 periods */
  56                         operating-points = <
  57                                 /* kHz  uV */
  58                                 528000  1250000
  59                                 396000  1150000
  60                                 198000  1150000
  61                         >;
  62                         fsl,soc-operating-points = <
  63                                 /* KHz  uV */
  64                                 528000  1250000
  65                                 396000  1150000
  66                                 198000  1150000
  67                         >;
  68                         clocks = <&clks IMX6UL_CLK_ARM>,
  69                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  70                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  71                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  72                                  <&clks IMX6UL_CLK_STEP>,
  73                                  <&clks IMX6UL_CLK_PLL1_SW>,
  74                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  75                                  <&clks IMX6UL_PLL1_BYPASS>,
  76                                  <&clks IMX6UL_CLK_PLL1>,
  77                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  78                                  <&clks IMX6UL_CLK_OSC>;
  79                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  80                                       "secondary_sel", "step", "pll1_sw",
  81                                       "pll1_sys", "pll1_bypass", "pll1",
  82                                       "pll1_bypass_src", "osc";
  83                         arm-supply = <&reg_arm>;
  84                         soc-supply = <&reg_soc>;
  85                 };
  86         };
  87
  88         intc: interrupt-controller@00a01000 {
  89                 compatible = "arm,cortex-a7-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x00a01000 0x1000>,
  93                       <0x00a02000 0x1000>,
  94                       <0x00a04000 0x2000>,
  95                       <0x00a06000 0x2000>;
  96         };
  97
  98         ckil: clock-cli {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         ipp_di0: clock-di0 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <0>;
 116                 clock-output-names = "ipp_di0";
 117         };
 118
 119         ipp_di1: clock-di1 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "ipp_di1";
 124         };
 125
 126         soc {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 compatible = "simple-bus";
 130                 interrupt-parent = <&gpc>;
 131                 ranges;
 132
 133                 pmu {
 134                         compatible = "arm,cortex-a7-pmu";
 135                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 136                         status = "disabled";
 137                 };
 138
 139                 ocram: sram@00900000 {
 140                         compatible = "mmio-sram";
 141                         reg = <0x00900000 0x20000>;
 142                 };
 143
 144                 aips1: aips-bus@02000000 {
 145                         compatible = "fsl,aips-bus", "simple-bus";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148                         reg = <0x02000000 0x100000>;
 149                         ranges;
 150
 151                         spba-bus@02000000 {
 152                                 compatible = "fsl,spba-bus", "simple-bus";
 153                                 #address-cells = <1>;
 154                                 #size-cells = <1>;
 155                                 reg = <0x02000000 0x40000>;
 156                                 ranges;
 157
 158                                 ecspi1: ecspi@02008000 {
 159                                         #address-cells = <1>;
 160                                         #size-cells = <0>;
 161                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 162                                         reg = <0x02008000 0x4000>;
 163                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 164                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 165                                                  <&clks IMX6UL_CLK_ECSPI1>;
 166                                         clock-names = "ipg", "per";
 167                                         status = "disabled";
 168                                 };
 169
 170                                 ecspi2: ecspi@0200c000 {
 171                                         #address-cells = <1>;
 172                                         #size-cells = <0>;
 173                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 174                                         reg = <0x0200c000 0x4000>;
 175                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 176                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 177                                                  <&clks IMX6UL_CLK_ECSPI2>;
 178                                         clock-names = "ipg", "per";
 179                                         status = "disabled";
 180                                 };
 181
 182                                 ecspi3: ecspi@02010000 {
 183                                         #address-cells = <1>;
 184                                         #size-cells = <0>;
 185                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 186                                         reg = <0x02010000 0x4000>;
 187                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 188                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 189                                                  <&clks IMX6UL_CLK_ECSPI3>;
 190                                         clock-names = "ipg", "per";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 ecspi4: ecspi@02014000 {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 198                                         reg = <0x02014000 0x4000>;
 199                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 200                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 201                                                  <&clks IMX6UL_CLK_ECSPI4>;
 202                                         clock-names = "ipg", "per";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 uart7: serial@02018000 {
 207                                         compatible = "fsl,imx6ul-uart",
 208                                                      "fsl,imx6q-uart";
 209                                         reg = <0x02018000 0x4000>;
 210                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 211                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 212                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 213                                         clock-names = "ipg", "per";
 214                                         status = "disabled";
 215                                 };
 216
 217                                 uart1: serial@02020000 {
 218                                         compatible = "fsl,imx6ul-uart",
 219                                                      "fsl,imx6q-uart";
 220                                         reg = <0x02020000 0x4000>;
 221                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 222                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 223                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 224                                         clock-names = "ipg", "per";
 225                                         status = "disabled";
 226                                 };
 227
 228                                 uart8: serial@02024000 {
 229                                         compatible = "fsl,imx6ul-uart",
 230                                                      "fsl,imx6q-uart";
 231                                         reg = <0x02024000 0x4000>;
 232                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 234                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238                         };
 239
 240                         tsc: tsc@02040000 {
 241                                 compatible = "fsl,imx6ul-tsc";
 242                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 243                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 244                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 245                                 clocks = <&clks IMX6UL_CLK_IPG>,
 246                                          <&clks IMX6UL_CLK_ADC2>;
 247                                 clock-names = "tsc", "adc";
 248                                 status = "disabled";
 249                         };
 250
 251                         gpt1: gpt@02098000 {
 252                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 253                                 reg = <0x02098000 0x4000>;
 254                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 255                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 256                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 257                                 clock-names = "ipg", "per";
 258                         };
 259
 260                         gpio1: gpio@0209c000 {
 261                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 262                                 reg = <0x0209c000 0x4000>;
 263                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 264                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 265                                 gpio-controller;
 266                                 #gpio-cells = <2>;
 267                                 interrupt-controller;
 268                                 #interrupt-cells = <2>;
 269                         };
 270
 271                         gpio2: gpio@020a0000 {
 272                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 273                                 reg = <0x020a0000 0x4000>;
 274                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 275                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 276                                 gpio-controller;
 277                                 #gpio-cells = <2>;
 278                                 interrupt-controller;
 279                                 #interrupt-cells = <2>;
 280                         };
 281
 282                         gpio3: gpio@020a4000 {
 283                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 284                                 reg = <0x020a4000 0x4000>;
 285                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 286                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 287                                 gpio-controller;
 288                                 #gpio-cells = <2>;
 289                                 interrupt-controller;
 290                                 #interrupt-cells = <2>;
 291                         };
 292
 293                         gpio4: gpio@020a8000 {
 294                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 295                                 reg = <0x020a8000 0x4000>;
 296                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 297                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 298                                 gpio-controller;
 299                                 #gpio-cells = <2>;
 300                                 interrupt-controller;
 301                                 #interrupt-cells = <2>;
 302                         };
 303
 304                         gpio5: gpio@020ac000 {
 305                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 306                                 reg = <0x020ac000 0x4000>;
 307                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 308                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 309                                 gpio-controller;
 310                                 #gpio-cells = <2>;
 311                                 interrupt-controller;
 312                                 #interrupt-cells = <2>;
 313                         };
 314
 315                         fec2: ethernet@020b4000 {
 316                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 317                                 reg = <0x020b4000 0x4000>;
 318                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 319                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 320                                 clocks = <&clks IMX6UL_CLK_ENET>,
 321                                          <&clks IMX6UL_CLK_ENET_AHB>,
 322                                          <&clks IMX6UL_CLK_ENET_PTP>,
 323                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 324                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 325                                 clock-names = "ipg", "ahb", "ptp",
 326                                               "enet_clk_ref", "enet_out";
 327                                 fsl,num-tx-queues=<1>;
 328                                 fsl,num-rx-queues=<1>;
 329                                 status = "disabled";
 330                         };
 331
 332                         wdog1: wdog@020bc000 {
 333                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 334                                 reg = <0x020bc000 0x4000>;
 335                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 337                         };
 338
 339                         wdog2: wdog@020c0000 {
 340                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 341                                 reg = <0x020c0000 0x4000>;
 342                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 343                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 344                                 status = "disabled";
 345                         };
 346
 347                         clks: ccm@020c4000 {
 348                                 compatible = "fsl,imx6ul-ccm";
 349                                 reg = <0x020c4000 0x4000>;
 350                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 352                                 #clock-cells = <1>;
 353                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 354                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 355                         };
 356
 357                         anatop: anatop@020c8000 {
 358                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 359                                              "syscon", "simple-bus";
 360                                 reg = <0x020c8000 0x1000>;
 361                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 362                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 363                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 364
 365                                 reg_3p0: regulator-3p0@120 {
 366                                         compatible = "fsl,anatop-regulator";
 367                                         regulator-name = "vdd3p0";
 368                                         regulator-min-microvolt = <2625000>;
 369                                         regulator-max-microvolt = <3400000>;
 370                                         anatop-reg-offset = <0x120>;
 371                                         anatop-vol-bit-shift = <8>;
 372                                         anatop-vol-bit-width = <5>;
 373                                         anatop-min-bit-val = <0>;
 374                                         anatop-min-voltage = <2625000>;
 375                                         anatop-max-voltage = <3400000>;
 376                                         anatop-enable-bit = <0>;
 377                                 };
 378
 379                                 reg_arm: regulator-vddcore@140 {
 380                                         compatible = "fsl,anatop-regulator";
 381                                         regulator-name = "cpu";
 382                                         regulator-min-microvolt = <725000>;
 383                                         regulator-max-microvolt = <1450000>;
 384                                         regulator-always-on;
 385                                         anatop-reg-offset = <0x140>;
 386                                         anatop-vol-bit-shift = <0>;
 387                                         anatop-vol-bit-width = <5>;
 388                                         anatop-delay-reg-offset = <0x170>;
 389                                         anatop-delay-bit-shift = <24>;
 390                                         anatop-delay-bit-width = <2>;
 391                                         anatop-min-bit-val = <1>;
 392                                         anatop-min-voltage = <725000>;
 393                                         anatop-max-voltage = <1450000>;
 394                                 };
 395
 396                                 reg_soc: regulator-vddsoc@140 {
 397                                         compatible = "fsl,anatop-regulator";
 398                                         regulator-name = "vddsoc";
 399                                         regulator-min-microvolt = <725000>;
 400                                         regulator-max-microvolt = <1450000>;
 401                                         regulator-always-on;
 402                                         anatop-reg-offset = <0x140>;
 403                                         anatop-vol-bit-shift = <18>;
 404                                         anatop-vol-bit-width = <5>;
 405                                         anatop-delay-reg-offset = <0x170>;
 406                                         anatop-delay-bit-shift = <28>;
 407                                         anatop-delay-bit-width = <2>;
 408                                         anatop-min-bit-val = <1>;
 409                                         anatop-min-voltage = <725000>;
 410                                         anatop-max-voltage = <1450000>;
 411                                 };
 412                         };
 413
 414                         usbphy1: usbphy@020c9000 {
 415                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 416                                 reg = <0x020c9000 0x1000>;
 417                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 419                                 phy-3p0-supply = <&reg_3p0>;
 420                                 fsl,anatop = <&anatop>;
 421                         };
 422
 423                         usbphy2: usbphy@020ca000 {
 424                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 425                                 reg = <0x020ca000 0x1000>;
 426                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 427                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 428                                 phy-3p0-supply = <&reg_3p0>;
 429                                 fsl,anatop = <&anatop>;
 430                         };
 431
 432                         snvs: snvs@020cc000 {
 433                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 434                                 reg = <0x020cc000 0x4000>;
 435
 436                                 snvs_rtc: snvs-rtc-lp {
 437                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 438                                         regmap = <&snvs>;
 439                                         offset = <0x34>;
 440                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 441                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 442                                 };
 443
 444                                 snvs_poweroff: snvs-poweroff {
 445                                         compatible = "syscon-poweroff";
 446                                         regmap = <&snvs>;
 447                                         offset = <0x38>;
 448                                         mask = <0x60>;
 449                                         status = "disabled";
 450                                 };
 451
 452                                 snvs_pwrkey: snvs-powerkey {
 453                                         compatible = "fsl,sec-v4.0-pwrkey";
 454                                         regmap = <&snvs>;
 455                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 456                                         linux,keycode = <KEY_POWER>;
 457                                         wakeup-source;
 458                                 };
 459                         };
 460
 461                         epit1: epit@020d0000 {
 462                                 reg = <0x020d0000 0x4000>;
 463                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 464                         };
 465
 466                         epit2: epit@020d4000 {
 467                                 reg = <0x020d4000 0x4000>;
 468                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 469                         };
 470
 471                         src: src@020d8000 {
 472                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 473                                 reg = <0x020d8000 0x4000>;
 474                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 475                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 476                                 #reset-cells = <1>;
 477                         };
 478
 479                         gpc: gpc@020dc000 {
 480                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 481                                 reg = <0x020dc000 0x4000>;
 482                                 interrupt-controller;
 483                                 #interrupt-cells = <3>;
 484                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 485                                 interrupt-parent = <&intc>;
 486                         };
 487
 488                         iomuxc: iomuxc@020e0000 {
 489                                 compatible = "fsl,imx6ul-iomuxc";
 490                                 reg = <0x020e0000 0x4000>;
 491                         };
 492
 493                         gpr: iomuxc-gpr@020e4000 {
 494                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 495                                 reg = <0x020e4000 0x4000>;
 496                         };
 497
 498                         gpt2: gpt@020e8000 {
 499                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 500                                 reg = <0x020e8000 0x4000>;
 501                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 503                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 504                                 clock-names = "ipg", "per";
 505                         };
 506
 507                         pwm5: pwm@020f0000 {
 508                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 509                                 reg = <0x020f0000 0x4000>;
 510                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 511                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 512                                          <&clks IMX6UL_CLK_PWM5>;
 513                                 clock-names = "ipg", "per";
 514                                 #pwm-cells = <2>;
 515                                 status = "disabled";
 516                         };
 517
 518                         pwm6: pwm@020f4000 {
 519                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 520                                 reg = <0x020f4000 0x4000>;
 521                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 522                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 523                                          <&clks IMX6UL_CLK_PWM6>;
 524                                 clock-names = "ipg", "per";
 525                                 #pwm-cells = <2>;
 526                                 status = "disabled";
 527                         };
 528
 529                         pwm7: pwm@020f8000 {
 530                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 531                                 reg = <0x020f8000 0x4000>;
 532                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 533                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 534                                          <&clks IMX6UL_CLK_PWM7>;
 535                                 clock-names = "ipg", "per";
 536                                 #pwm-cells = <2>;
 537                                 status = "disabled";
 538                         };
 539
 540                         pwm8: pwm@020fc000 {
 541                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 542                                 reg = <0x020fc000 0x4000>;
 543                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 544                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 545                                          <&clks IMX6UL_CLK_PWM8>;
 546                                 clock-names = "ipg", "per";
 547                                 #pwm-cells = <2>;
 548                                 status = "disabled";
 549                         };
 550                 };
 551
 552                 aips2: aips-bus@02100000 {
 553                         compatible = "fsl,aips-bus", "simple-bus";
 554                         #address-cells = <1>;
 555                         #size-cells = <1>;
 556                         reg = <0x02100000 0x100000>;
 557                         ranges;
 558
 559                         usbotg1: usb@02184000 {
 560                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 561                                 reg = <0x02184000 0x200>;
 562                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 563                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 564                                 fsl,usbphy = <&usbphy1>;
 565                                 fsl,usbmisc = <&usbmisc 0>;
 566                                 fsl,anatop = <&anatop>;
 567                                 ahb-burst-config = <0x0>;
 568                                 tx-burst-size-dword = <0x10>;
 569                                 rx-burst-size-dword = <0x10>;
 570                                 status = "disabled";
 571                         };
 572
 573                         usbotg2: usb@02184200 {
 574                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 575                                 reg = <0x02184200 0x200>;
 576                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 577                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 578                                 fsl,usbphy = <&usbphy2>;
 579                                 fsl,usbmisc = <&usbmisc 1>;
 580                                 ahb-burst-config = <0x0>;
 581                                 tx-burst-size-dword = <0x10>;
 582                                 rx-burst-size-dword = <0x10>;
 583                                 status = "disabled";
 584                         };
 585
 586                         usbmisc: usbmisc@02184800 {
 587                                 #index-cells = <1>;
 588                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 589                                 reg = <0x02184800 0x200>;
 590                         };
 591
 592                         fec1: ethernet@02188000 {
 593                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 594                                 reg = <0x02188000 0x4000>;
 595                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 596                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 597                                 clocks = <&clks IMX6UL_CLK_ENET>,
 598                                          <&clks IMX6UL_CLK_ENET_AHB>,
 599                                          <&clks IMX6UL_CLK_ENET_PTP>,
 600                                          <&clks IMX6UL_CLK_ENET_REF>,
 601                                          <&clks IMX6UL_CLK_ENET_REF>;
 602                                 clock-names = "ipg", "ahb", "ptp",
 603                                               "enet_clk_ref", "enet_out";
 604                                 fsl,num-tx-queues=<1>;
 605                                 fsl,num-rx-queues=<1>;
 606                                 status = "disabled";
 607                         };
 608
 609                         usdhc1: usdhc@02190000 {
 610                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 611                                 reg = <0x02190000 0x4000>;
 612                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 614                                          <&clks IMX6UL_CLK_USDHC1>,
 615                                          <&clks IMX6UL_CLK_USDHC1>;
 616                                 clock-names = "ipg", "ahb", "per";
 617                                 bus-width = <4>;
 618                                 status = "disabled";
 619                         };
 620
 621                         usdhc2: usdhc@02194000 {
 622                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 623                                 reg = <0x02194000 0x4000>;
 624                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 626                                          <&clks IMX6UL_CLK_USDHC2>,
 627                                          <&clks IMX6UL_CLK_USDHC2>;
 628                                 clock-names = "ipg", "ahb", "per";
 629                                 bus-width = <4>;
 630                                 status = "disabled";
 631                         };
 632
 633                         adc1: adc@02198000 {
 634                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 635                                 reg = <0x02198000 0x4000>;
 636                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 638                                 num-channels = <2>;
 639                                 clock-names = "adc";
 640                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 641                                                          <20000000>;
 642                                 status = "disabled";
 643                         };
 644
 645                         i2c1: i2c@021a0000 {
 646                                 #address-cells = <1>;
 647                                 #size-cells = <0>;
 648                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 649                                 reg = <0x021a0000 0x4000>;
 650                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 651                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 652                                 status = "disabled";
 653                         };
 654
 655                         i2c2: i2c@021a4000 {
 656                                 #address-cells = <1>;
 657                                 #size-cells = <0>;
 658                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 659                                 reg = <0x021a4000 0x4000>;
 660                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 661                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 662                                 status = "disabled";
 663                         };
 664
 665                         i2c3: i2c@021a8000 {
 666                                 #address-cells = <1>;
 667                                 #size-cells = <0>;
 668                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 669                                 reg = <0x021a8000 0x4000>;
 670                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 672                                 status = "disabled";
 673                         };
 674
 675                         mmdc: mmdc@021b0000 {
 676                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 677                                 reg = <0x021b0000 0x4000>;
 678                         };
 679
 680                         qspi: qspi@021e0000 {
 681                                 #address-cells = <1>;
 682                                 #size-cells = <0>;
 683                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 684                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 685                                 reg-names = "QuadSPI", "QuadSPI-memory";
 686                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 687                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 688                                          <&clks IMX6UL_CLK_QSPI>;
 689                                 clock-names = "qspi_en", "qspi";
 690                                 status = "disabled";
 691                         };
 692
 693                         uart2: serial@021e8000 {
 694                                 compatible = "fsl,imx6ul-uart",
 695                                              "fsl,imx6q-uart";
 696                                 reg = <0x021e8000 0x4000>;
 697                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 698                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 699                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 700                                 clock-names = "ipg", "per";
 701                                 status = "disabled";
 702                         };
 703
 704                         uart3: serial@021ec000 {
 705                                 compatible = "fsl,imx6ul-uart",
 706                                              "fsl,imx6q-uart";
 707                                 reg = <0x021ec000 0x4000>;
 708                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 709                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 710                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 711                                 clock-names = "ipg", "per";
 712                                 status = "disabled";
 713                         };
 714
 715                         uart4: serial@021f0000 {
 716                                 compatible = "fsl,imx6ul-uart",
 717                                              "fsl,imx6q-uart";
 718                                 reg = <0x021f0000 0x4000>;
 719                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 721                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 722                                 clock-names = "ipg", "per";
 723                                 status = "disabled";
 724                         };
 725
 726                         uart5: serial@021f4000 {
 727                                 compatible = "fsl,imx6ul-uart",
 728                                              "fsl,imx6q-uart";
 729                                 reg = <0x021f4000 0x4000>;
 730                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 732                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 733                                 clock-names = "ipg", "per";
 734                                 status = "disabled";
 735                         };
 736
 737                         i2c4: i2c@021f8000 {
 738                                 #address-cells = <1>;
 739                                 #size-cells = <0>;
 740                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 741                                 reg = <0x021f8000 0x4000>;
 742                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 744                                 status = "disabled";
 745                         };
 746
 747                         uart6: serial@021fc000 {
 748                                 compatible = "fsl,imx6ul-uart",
 749                                              "fsl,imx6q-uart";
 750                                 reg = <0x021fc000 0x4000>;
 751                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 753                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 754                                 clock-names = "ipg", "per";
 755                                 status = "disabled";
 756                         };
 757                 };
 758         };
 759 };