2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
14 #include "skeleton.dtsi"
52 compatible = "arm,cortex-a7";
55 clock-latency = <61036>; /* two CLK32 periods */
62 fsl,soc-operating-points = <
68 clocks = <&clks IMX6UL_CLK_ARM>,
69 <&clks IMX6UL_CLK_PLL2_BUS>,
70 <&clks IMX6UL_CLK_PLL2_PFD2>,
71 <&clks IMX6UL_CA7_SECONDARY_SEL>,
72 <&clks IMX6UL_CLK_STEP>,
73 <&clks IMX6UL_CLK_PLL1_SW>,
74 <&clks IMX6UL_CLK_PLL1_SYS>,
75 <&clks IMX6UL_PLL1_BYPASS>,
76 <&clks IMX6UL_CLK_PLL1>,
77 <&clks IMX6UL_PLL1_BYPASS_SRC>,
78 <&clks IMX6UL_CLK_OSC>;
79 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
80 "secondary_sel", "step", "pll1_sw",
81 "pll1_sys", "pll1_bypass", "pll1",
82 "pll1_bypass_src", "osc";
83 arm-supply = <®_arm>;
84 soc-supply = <®_soc>;
88 intc: interrupt-controller@00a01000 {
89 compatible = "arm,cortex-a7-gic";
90 #interrupt-cells = <3>;
92 reg = <0x00a01000 0x1000>,
99 compatible = "fixed-clock";
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
106 compatible = "fixed-clock";
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
113 compatible = "fixed-clock";
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
120 compatible = "fixed-clock";
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
127 #address-cells = <1>;
129 compatible = "simple-bus";
130 interrupt-parent = <&gpc>;
134 compatible = "arm,cortex-a7-pmu";
135 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
139 ocram: sram@00900000 {
140 compatible = "mmio-sram";
141 reg = <0x00900000 0x20000>;
144 aips1: aips-bus@02000000 {
145 compatible = "fsl,aips-bus", "simple-bus";
146 #address-cells = <1>;
148 reg = <0x02000000 0x100000>;
152 compatible = "fsl,spba-bus", "simple-bus";
153 #address-cells = <1>;
155 reg = <0x02000000 0x40000>;
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
161 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&clks IMX6UL_CLK_ECSPI1>,
165 <&clks IMX6UL_CLK_ECSPI1>;
166 clock-names = "ipg", "per";
170 ecspi2: ecspi@0200c000 {
171 #address-cells = <1>;
173 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
174 reg = <0x0200c000 0x4000>;
175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6UL_CLK_ECSPI2>,
177 <&clks IMX6UL_CLK_ECSPI2>;
178 clock-names = "ipg", "per";
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
185 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clks IMX6UL_CLK_ECSPI3>,
189 <&clks IMX6UL_CLK_ECSPI3>;
190 clock-names = "ipg", "per";
194 ecspi4: ecspi@02014000 {
195 #address-cells = <1>;
197 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02014000 0x4000>;
199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6UL_CLK_ECSPI4>,
201 <&clks IMX6UL_CLK_ECSPI4>;
202 clock-names = "ipg", "per";
206 uart7: serial@02018000 {
207 compatible = "fsl,imx6ul-uart",
209 reg = <0x02018000 0x4000>;
210 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
212 <&clks IMX6UL_CLK_UART7_SERIAL>;
213 clock-names = "ipg", "per";
217 uart1: serial@02020000 {
218 compatible = "fsl,imx6ul-uart",
220 reg = <0x02020000 0x4000>;
221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
223 <&clks IMX6UL_CLK_UART1_SERIAL>;
224 clock-names = "ipg", "per";
228 uart8: serial@02024000 {
229 compatible = "fsl,imx6ul-uart",
231 reg = <0x02024000 0x4000>;
232 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
234 <&clks IMX6UL_CLK_UART8_SERIAL>;
235 clock-names = "ipg", "per";
241 compatible = "fsl,imx6ul-tsc";
242 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
243 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6UL_CLK_IPG>,
246 <&clks IMX6UL_CLK_ADC2>;
247 clock-names = "tsc", "adc";
252 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
253 reg = <0x02080000 0x4000>;
254 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_PWM1>,
256 <&clks IMX6UL_CLK_PWM1>;
257 clock-names = "ipg", "per";
263 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
264 reg = <0x02084000 0x4000>;
265 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6UL_CLK_PWM2>,
267 <&clks IMX6UL_CLK_PWM2>;
268 clock-names = "ipg", "per";
274 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
275 reg = <0x02088000 0x4000>;
276 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6UL_CLK_PWM3>,
278 <&clks IMX6UL_CLK_PWM3>;
279 clock-names = "ipg", "per";
285 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
286 reg = <0x0208c000 0x4000>;
287 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clks IMX6UL_CLK_PWM4>,
289 <&clks IMX6UL_CLK_PWM4>;
290 clock-names = "ipg", "per";
296 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
297 reg = <0x02098000 0x4000>;
298 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
300 <&clks IMX6UL_CLK_GPT1_SERIAL>;
301 clock-names = "ipg", "per";
304 gpio1: gpio@0209c000 {
305 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
306 reg = <0x0209c000 0x4000>;
307 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 gpio2: gpio@020a0000 {
316 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
317 reg = <0x020a0000 0x4000>;
318 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
326 gpio3: gpio@020a4000 {
327 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
328 reg = <0x020a4000 0x4000>;
329 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
337 gpio4: gpio@020a8000 {
338 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
339 reg = <0x020a8000 0x4000>;
340 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 gpio5: gpio@020ac000 {
349 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
350 reg = <0x020ac000 0x4000>;
351 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 fec2: ethernet@020b4000 {
360 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
361 reg = <0x020b4000 0x4000>;
362 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6UL_CLK_ENET>,
365 <&clks IMX6UL_CLK_ENET_AHB>,
366 <&clks IMX6UL_CLK_ENET_PTP>,
367 <&clks IMX6UL_CLK_ENET2_REF_125M>,
368 <&clks IMX6UL_CLK_ENET2_REF_125M>;
369 clock-names = "ipg", "ahb", "ptp",
370 "enet_clk_ref", "enet_out";
371 fsl,num-tx-queues=<1>;
372 fsl,num-rx-queues=<1>;
376 wdog1: wdog@020bc000 {
377 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
378 reg = <0x020bc000 0x4000>;
379 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6UL_CLK_WDOG1>;
383 wdog2: wdog@020c0000 {
384 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
385 reg = <0x020c0000 0x4000>;
386 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6UL_CLK_WDOG2>;
392 compatible = "fsl,imx6ul-ccm";
393 reg = <0x020c4000 0x4000>;
394 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
398 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
401 anatop: anatop@020c8000 {
402 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
403 "syscon", "simple-bus";
404 reg = <0x020c8000 0x1000>;
405 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
409 reg_3p0: regulator-3p0@120 {
410 compatible = "fsl,anatop-regulator";
411 regulator-name = "vdd3p0";
412 regulator-min-microvolt = <2625000>;
413 regulator-max-microvolt = <3400000>;
414 anatop-reg-offset = <0x120>;
415 anatop-vol-bit-shift = <8>;
416 anatop-vol-bit-width = <5>;
417 anatop-min-bit-val = <0>;
418 anatop-min-voltage = <2625000>;
419 anatop-max-voltage = <3400000>;
420 anatop-enable-bit = <0>;
423 reg_arm: regulator-vddcore@140 {
424 compatible = "fsl,anatop-regulator";
425 regulator-name = "cpu";
426 regulator-min-microvolt = <725000>;
427 regulator-max-microvolt = <1450000>;
429 anatop-reg-offset = <0x140>;
430 anatop-vol-bit-shift = <0>;
431 anatop-vol-bit-width = <5>;
432 anatop-delay-reg-offset = <0x170>;
433 anatop-delay-bit-shift = <24>;
434 anatop-delay-bit-width = <2>;
435 anatop-min-bit-val = <1>;
436 anatop-min-voltage = <725000>;
437 anatop-max-voltage = <1450000>;
440 reg_soc: regulator-vddsoc@140 {
441 compatible = "fsl,anatop-regulator";
442 regulator-name = "vddsoc";
443 regulator-min-microvolt = <725000>;
444 regulator-max-microvolt = <1450000>;
446 anatop-reg-offset = <0x140>;
447 anatop-vol-bit-shift = <18>;
448 anatop-vol-bit-width = <5>;
449 anatop-delay-reg-offset = <0x170>;
450 anatop-delay-bit-shift = <28>;
451 anatop-delay-bit-width = <2>;
452 anatop-min-bit-val = <1>;
453 anatop-min-voltage = <725000>;
454 anatop-max-voltage = <1450000>;
458 usbphy1: usbphy@020c9000 {
459 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
460 reg = <0x020c9000 0x1000>;
461 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6UL_CLK_USBPHY1>;
463 phy-3p0-supply = <®_3p0>;
464 fsl,anatop = <&anatop>;
467 usbphy2: usbphy@020ca000 {
468 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
469 reg = <0x020ca000 0x1000>;
470 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clks IMX6UL_CLK_USBPHY2>;
472 phy-3p0-supply = <®_3p0>;
473 fsl,anatop = <&anatop>;
476 snvs: snvs@020cc000 {
477 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
478 reg = <0x020cc000 0x4000>;
480 snvs_rtc: snvs-rtc-lp {
481 compatible = "fsl,sec-v4.0-mon-rtc-lp";
484 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
488 snvs_poweroff: snvs-poweroff {
489 compatible = "syscon-poweroff";
496 snvs_pwrkey: snvs-powerkey {
497 compatible = "fsl,sec-v4.0-pwrkey";
499 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
500 linux,keycode = <KEY_POWER>;
505 epit1: epit@020d0000 {
506 reg = <0x020d0000 0x4000>;
507 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
510 epit2: epit@020d4000 {
511 reg = <0x020d4000 0x4000>;
512 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
516 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
517 reg = <0x020d8000 0x4000>;
518 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
524 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
525 reg = <0x020dc000 0x4000>;
526 interrupt-controller;
527 #interrupt-cells = <3>;
528 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
529 interrupt-parent = <&intc>;
532 iomuxc: iomuxc@020e0000 {
533 compatible = "fsl,imx6ul-iomuxc";
534 reg = <0x020e0000 0x4000>;
537 gpr: iomuxc-gpr@020e4000 {
538 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
539 reg = <0x020e4000 0x4000>;
543 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
544 reg = <0x020e8000 0x4000>;
545 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
547 <&clks IMX6UL_CLK_GPT2_SERIAL>;
548 clock-names = "ipg", "per";
551 sdma: sdma@020ec000 {
552 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
554 reg = <0x020ec000 0x4000>;
555 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks IMX6UL_CLK_SDMA>,
557 <&clks IMX6UL_CLK_SDMA>;
558 clock-names = "ipg", "ahb";
560 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
564 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
565 reg = <0x020f0000 0x4000>;
566 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&clks IMX6UL_CLK_PWM5>,
568 <&clks IMX6UL_CLK_PWM5>;
569 clock-names = "ipg", "per";
575 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
576 reg = <0x020f4000 0x4000>;
577 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6UL_CLK_PWM6>,
579 <&clks IMX6UL_CLK_PWM6>;
580 clock-names = "ipg", "per";
586 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
587 reg = <0x020f8000 0x4000>;
588 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&clks IMX6UL_CLK_PWM7>,
590 <&clks IMX6UL_CLK_PWM7>;
591 clock-names = "ipg", "per";
597 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
598 reg = <0x020fc000 0x4000>;
599 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clks IMX6UL_CLK_PWM8>,
601 <&clks IMX6UL_CLK_PWM8>;
602 clock-names = "ipg", "per";
608 aips2: aips-bus@02100000 {
609 compatible = "fsl,aips-bus", "simple-bus";
610 #address-cells = <1>;
612 reg = <0x02100000 0x100000>;
615 usbotg1: usb@02184000 {
616 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
617 reg = <0x02184000 0x200>;
618 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&clks IMX6UL_CLK_USBOH3>;
620 fsl,usbphy = <&usbphy1>;
621 fsl,usbmisc = <&usbmisc 0>;
622 fsl,anatop = <&anatop>;
623 ahb-burst-config = <0x0>;
624 tx-burst-size-dword = <0x10>;
625 rx-burst-size-dword = <0x10>;
629 usbotg2: usb@02184200 {
630 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
631 reg = <0x02184200 0x200>;
632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&clks IMX6UL_CLK_USBOH3>;
634 fsl,usbphy = <&usbphy2>;
635 fsl,usbmisc = <&usbmisc 1>;
636 ahb-burst-config = <0x0>;
637 tx-burst-size-dword = <0x10>;
638 rx-burst-size-dword = <0x10>;
642 usbmisc: usbmisc@02184800 {
644 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
645 reg = <0x02184800 0x200>;
648 fec1: ethernet@02188000 {
649 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
650 reg = <0x02188000 0x4000>;
651 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6UL_CLK_ENET>,
654 <&clks IMX6UL_CLK_ENET_AHB>,
655 <&clks IMX6UL_CLK_ENET_PTP>,
656 <&clks IMX6UL_CLK_ENET_REF>,
657 <&clks IMX6UL_CLK_ENET_REF>;
658 clock-names = "ipg", "ahb", "ptp",
659 "enet_clk_ref", "enet_out";
660 fsl,num-tx-queues=<1>;
661 fsl,num-rx-queues=<1>;
665 usdhc1: usdhc@02190000 {
666 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
667 reg = <0x02190000 0x4000>;
668 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clks IMX6UL_CLK_USDHC1>,
670 <&clks IMX6UL_CLK_USDHC1>,
671 <&clks IMX6UL_CLK_USDHC1>;
672 clock-names = "ipg", "ahb", "per";
677 usdhc2: usdhc@02194000 {
678 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
679 reg = <0x02194000 0x4000>;
680 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX6UL_CLK_USDHC2>,
682 <&clks IMX6UL_CLK_USDHC2>,
683 <&clks IMX6UL_CLK_USDHC2>;
684 clock-names = "ipg", "ahb", "per";
690 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
691 reg = <0x02198000 0x4000>;
692 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX6UL_CLK_ADC1>;
696 fsl,adck-max-frequency = <30000000>, <40000000>,
702 #address-cells = <1>;
704 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
705 reg = <0x021a0000 0x4000>;
706 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clks IMX6UL_CLK_I2C1>;
712 #address-cells = <1>;
714 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
715 reg = <0x021a4000 0x4000>;
716 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&clks IMX6UL_CLK_I2C2>;
722 #address-cells = <1>;
724 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
725 reg = <0x021a8000 0x4000>;
726 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clks IMX6UL_CLK_I2C3>;
731 mmdc: mmdc@021b0000 {
732 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
733 reg = <0x021b0000 0x4000>;
736 qspi: qspi@021e0000 {
737 #address-cells = <1>;
739 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
740 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
741 reg-names = "QuadSPI", "QuadSPI-memory";
742 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6UL_CLK_QSPI>,
744 <&clks IMX6UL_CLK_QSPI>;
745 clock-names = "qspi_en", "qspi";
749 uart2: serial@021e8000 {
750 compatible = "fsl,imx6ul-uart",
752 reg = <0x021e8000 0x4000>;
753 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
755 <&clks IMX6UL_CLK_UART2_SERIAL>;
756 clock-names = "ipg", "per";
760 uart3: serial@021ec000 {
761 compatible = "fsl,imx6ul-uart",
763 reg = <0x021ec000 0x4000>;
764 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
766 <&clks IMX6UL_CLK_UART3_SERIAL>;
767 clock-names = "ipg", "per";
771 uart4: serial@021f0000 {
772 compatible = "fsl,imx6ul-uart",
774 reg = <0x021f0000 0x4000>;
775 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
777 <&clks IMX6UL_CLK_UART4_SERIAL>;
778 clock-names = "ipg", "per";
782 uart5: serial@021f4000 {
783 compatible = "fsl,imx6ul-uart",
785 reg = <0x021f4000 0x4000>;
786 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
788 <&clks IMX6UL_CLK_UART5_SERIAL>;
789 clock-names = "ipg", "per";
794 #address-cells = <1>;
796 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
797 reg = <0x021f8000 0x4000>;
798 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clks IMX6UL_CLK_I2C4>;
803 uart6: serial@021fc000 {
804 compatible = "fsl,imx6ul-uart",
806 reg = <0x021fc000 0x4000>;
807 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
809 <&clks IMX6UL_CLK_UART6_SERIAL>;
810 clock-names = "ipg", "per";