arch/arm/boot/dts/imx7d.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/imx7d-clock.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include "imx7d-pinfunc.h"
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         aliases {
  51                 gpio0 = &gpio1;
  52                 gpio1 = &gpio2;
  53                 gpio2 = &gpio3;
  54                 gpio3 = &gpio4;
  55                 gpio4 = &gpio5;
  56                 gpio5 = &gpio6;
  57                 gpio6 = &gpio7;
  58                 i2c0 = &i2c1;
  59                 i2c1 = &i2c2;
  60                 i2c2 = &i2c3;
  61                 i2c3 = &i2c4;
  62                 mmc0 = &usdhc1;
  63                 mmc1 = &usdhc2;
  64                 mmc2 = &usdhc3;
  65                 serial0 = &uart1;
  66                 serial1 = &uart2;
  67                 serial2 = &uart3;
  68                 serial3 = &uart4;
  69                 serial4 = &uart5;
  70                 serial5 = &uart6;
  71                 serial6 = &uart7;
  72         };
  73
  74         cpus {
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 cpu0: cpu@0 {
  79                         compatible = "arm,cortex-a7";
  80                         device_type = "cpu";
  81                         reg = <0>;
  82                         operating-points = <
  83                                 /* KHz  uV */
  84                                 996000  1075000
  85                                 792000  975000
  86                         >;
  87                         clock-latency = <61036>; /* two CLK32 periods */
  88                         clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
  89                                  <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
  90                         clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
  91                 };
  92
  93                 cpu1: cpu@1 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <1>;
  97                 };
  98         };
  99
 100         intc: interrupt-controller@31001000 {
 101                 compatible = "arm,cortex-a7-gic";
 102                 #interrupt-cells = <3>;
 103                 interrupt-controller;
 104                 reg = <0x31001000 0x1000>,
 105                       <0x31002000 0x1000>,
 106                       <0x31004000 0x2000>,
 107                       <0x31006000 0x2000>;
 108         };
 109
 110         ckil: clock-cki {
 111                 compatible = "fixed-clock";
 112                 #clock-cells = <0>;
 113                 clock-frequency = <32768>;
 114                 clock-output-names = "ckil";
 115         };
 116
 117         osc: clock-osc {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <24000000>;
 121                 clock-output-names = "osc";
 122         };
 123
 124         soc {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 compatible = "simple-bus";
 128                 interrupt-parent = <&intc>;
 129                 ranges;
 130
 131                 aips1: aips-bus@30000000 {
 132                         compatible = "fsl,aips-bus", "simple-bus";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         reg = <0x30000000 0x400000>;
 136                         ranges;
 137
 138                         gpio1: gpio@30200000 {
 139                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 140                                 reg = <0x30200000 0x10000>;
 141                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 142                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 143                                 gpio-controller;
 144                                 #gpio-cells = <2>;
 145                                 interrupt-controller;
 146                                 #interrupt-cells = <2>;
 147                         };
 148
 149                         gpio2: gpio@30210000 {
 150                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 151                                 reg = <0x30210000 0x10000>;
 152                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 153                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 154                                 gpio-controller;
 155                                 #gpio-cells = <2>;
 156                                 interrupt-controller;
 157                                 #interrupt-cells = <2>;
 158                         };
 159
 160                         gpio3: gpio@30220000 {
 161                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 162                                 reg = <0x30220000 0x10000>;
 163                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 164                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 165                                 gpio-controller;
 166                                 #gpio-cells = <2>;
 167                                 interrupt-controller;
 168                                 #interrupt-cells = <2>;
 169                         };
 170
 171                         gpio4: gpio@30230000 {
 172                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 173                                 reg = <0x30230000 0x10000>;
 174                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 175                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 176                                 gpio-controller;
 177                                 #gpio-cells = <2>;
 178                                 interrupt-controller;
 179                                 #interrupt-cells = <2>;
 180                         };
 181
 182                         gpio5: gpio@30240000 {
 183                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 184                                 reg = <0x30240000 0x10000>;
 185                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 186                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 187                                 gpio-controller;
 188                                 #gpio-cells = <2>;
 189                                 interrupt-controller;
 190                                 #interrupt-cells = <2>;
 191                         };
 192
 193                         gpio6: gpio@30250000 {
 194                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 195                                 reg = <0x30250000 0x10000>;
 196                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 197                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 198                                 gpio-controller;
 199                                 #gpio-cells = <2>;
 200                                 interrupt-controller;
 201                                 #interrupt-cells = <2>;
 202                         };
 203
 204                         gpio7: gpio@30260000 {
 205                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 206                                 reg = <0x30260000 0x10000>;
 207                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 208                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 209                                 gpio-controller;
 210                                 #gpio-cells = <2>;
 211                                 interrupt-controller;
 212                                 #interrupt-cells = <2>;
 213                         };
 214
 215                         wdog1: wdog@30280000 {
 216                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 217                                 reg = <0x30280000 0x10000>;
 218                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 219                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 220                         };
 221
 222                         wdog2: wdog@30290000 {
 223                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 224                                 reg = <0x30290000 0x10000>;
 225                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 226                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 227                                 status = "disabled";
 228                         };
 229
 230                         wdog3: wdog@302a0000 {
 231                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 232                                 reg = <0x302a0000 0x10000>;
 233                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 234                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 235                                 status = "disabled";
 236                         };
 237
 238                         wdog4: wdog@302b0000 {
 239                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 240                                 reg = <0x302b0000 0x10000>;
 241                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 242                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 243                                 status = "disabled";
 244                         };
 245
 246                         gpt1: gpt@302d0000 {
 247                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 248                                 reg = <0x302d0000 0x10000>;
 249                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 250                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 251                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 252                                 clock-names = "ipg", "per";
 253                         };
 254
 255                         gpt2: gpt@302e0000 {
 256                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 257                                 reg = <0x302e0000 0x10000>;
 258                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 259                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 260                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 261                                 clock-names = "ipg", "per";
 262                                 status = "disabled";
 263                         };
 264
 265                         gpt3: gpt@302f0000 {
 266                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 267                                 reg = <0x302f0000 0x10000>;
 268                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 269                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 270                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 271                                 clock-names = "ipg", "per";
 272                                 status = "disabled";
 273                         };
 274
 275                         gpt4: gpt@30300000 {
 276                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 277                                 reg = <0x30300000 0x10000>;
 278                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 279                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 280                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 281                                 clock-names = "ipg", "per";
 282                                 status = "disabled";
 283                         };
 284
 285                         iomuxc: iomuxc@30330000 {
 286                                 compatible = "fsl,imx7d-iomuxc";
 287                                 reg = <0x30330000 0x10000>;
 288                         };
 289
 290                         gpr: iomuxc-gpr@30340000 {
 291                                 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
 292                                 reg = <0x30340000 0x10000>;
 293                         };
 294
 295                         ocotp: ocotp-ctrl@30350000 {
 296                                 compatible = "syscon";
 297                                 reg = <0x30350000 0x10000>;
 298                                 clocks = <&clks IMX7D_CLK_DUMMY>;
 299                                 status = "disabled";
 300                         };
 301
 302                         anatop: anatop@30360000 {
 303                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 304                                         "syscon", "simple-bus";
 305                                 reg = <0x30360000 0x10000>;
 306                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 307                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 308
 309                                 reg_1p0d: regulator-vdd1p0d@210 {
 310                                         compatible = "fsl,anatop-regulator";
 311                                         regulator-name = "vdd1p0d";
 312                                         regulator-min-microvolt = <800000>;
 313                                         regulator-max-microvolt = <1200000>;
 314                                         anatop-reg-offset = <0x210>;
 315                                         anatop-vol-bit-shift = <8>;
 316                                         anatop-vol-bit-width = <5>;
 317                                         anatop-min-bit-val = <8>;
 318                                         anatop-min-voltage = <800000>;
 319                                         anatop-max-voltage = <1200000>;
 320                                         anatop-enable-bit = <31>;
 321                                 };
 322                         };
 323
 324                         snvs: snvs@30370000 {
 325                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 326                                 #address-cells = <1>;
 327                                 #size-cells = <1>;
 328                                 ranges = <0 0x30370000 0x10000>;
 329
 330                                 snvs-rtc-lp@34 {
 331                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 332                                         reg = <0x34 0x58>;
 333                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 334                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 335                                 };
 336                         };
 337
 338                         clks: ccm@30380000 {
 339                                 compatible = "fsl,imx7d-ccm";
 340                                 reg = <0x30380000 0x10000>;
 341                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 342                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 343                                 #clock-cells = <1>;
 344                                 clocks = <&ckil>, <&osc>;
 345                                 clock-names = "ckil", "osc";
 346                         };
 347
 348                         src: src@30390000 {
 349                                 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
 350                                 reg = <0x30390000 0x10000>;
 351                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 352                                 #reset-cells = <1>;
 353                         };
 354                 };
 355
 356                 aips3: aips-bus@30800000 {
 357                         compatible = "fsl,aips-bus", "simple-bus";
 358                         #address-cells = <1>;
 359                         #size-cells = <1>;
 360                         reg = <0x30800000 0x400000>;
 361                         ranges;
 362
 363                         uart1: serial@30860000 {
 364                                 compatible = "fsl,imx7d-uart",
 365                                              "fsl,imx6q-uart";
 366                                 reg = <0x30860000 0x10000>;
 367                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 369                                         <&clks IMX7D_UART1_ROOT_CLK>;
 370                                 clock-names = "ipg", "per";
 371                                 status = "disabled";
 372                         };
 373
 374                         uart2: serial@30870000 {
 375                                 compatible = "fsl,imx7d-uart",
 376                                              "fsl,imx6q-uart";
 377                                 reg = <0x30870000 0x10000>;
 378                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 380                                         <&clks IMX7D_UART2_ROOT_CLK>;
 381                                 clock-names = "ipg", "per";
 382                                 status = "disabled";
 383                         };
 384
 385                         uart3: serial@30880000 {
 386                                 compatible = "fsl,imx7d-uart",
 387                                              "fsl,imx6q-uart";
 388                                 reg = <0x30880000 0x10000>;
 389                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 390                                 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 391                                         <&clks IMX7D_UART3_ROOT_CLK>;
 392                                 clock-names = "ipg", "per";
 393                                 status = "disabled";
 394                         };
 395
 396                         i2c1: i2c@30a20000 {
 397                                 #address-cells = <1>;
 398                                 #size-cells = <0>;
 399                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 400                                 reg = <0x30a20000 0x10000>;
 401                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 403                                 status = "disabled";
 404                         };
 405
 406                         i2c2: i2c@30a30000 {
 407                                 #address-cells = <1>;
 408                                 #size-cells = <0>;
 409                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 410                                 reg = <0x30a30000 0x10000>;
 411                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 413                                 status = "disabled";
 414                         };
 415
 416                         i2c3: i2c@30a40000 {
 417                                 #address-cells = <1>;
 418                                 #size-cells = <0>;
 419                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 420                                 reg = <0x30a40000 0x10000>;
 421                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 423                                 status = "disabled";
 424                         };
 425
 426                         i2c4: i2c@30a50000 {
 427                                 #address-cells = <1>;
 428                                 #size-cells = <0>;
 429                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 430                                 reg = <0x30a50000 0x10000>;
 431                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 432                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 433                                 status = "disabled";
 434                         };
 435
 436                         uart4: serial@30a60000 {
 437                                 compatible = "fsl,imx7d-uart",
 438                                              "fsl,imx6q-uart";
 439                                 reg = <0x30a60000 0x10000>;
 440                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 442                                         <&clks IMX7D_UART4_ROOT_CLK>;
 443                                 clock-names = "ipg", "per";
 444                                 status = "disabled";
 445                         };
 446
 447                         uart5: serial@30a70000 {
 448                                 compatible = "fsl,imx7d-uart",
 449                                              "fsl,imx6q-uart";
 450                                 reg = <0x30a70000 0x10000>;
 451                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 453                                         <&clks IMX7D_UART5_ROOT_CLK>;
 454                                 clock-names = "ipg", "per";
 455                                 status = "disabled";
 456                         };
 457
 458                         uart6: serial@30a80000 {
 459                                 compatible = "fsl,imx7d-uart",
 460                                              "fsl,imx6q-uart";
 461                                 reg = <0x30a80000 0x10000>;
 462                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 463                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 464                                         <&clks IMX7D_UART6_ROOT_CLK>;
 465                                 clock-names = "ipg", "per";
 466                                 status = "disabled";
 467                         };
 468
 469                         uart7: serial@30a90000 {
 470                                 compatible = "fsl,imx7d-uart",
 471                                              "fsl,imx6q-uart";
 472                                 reg = <0x30a90000 0x10000>;
 473                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 474                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 475                                         <&clks IMX7D_UART7_ROOT_CLK>;
 476                                 clock-names = "ipg", "per";
 477                                 status = "disabled";
 478                         };
 479
 480                         usdhc1: usdhc@30b40000 {
 481                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 482                                 reg = <0x30b40000 0x10000>;
 483                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 484                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 485                                         <&clks IMX7D_CLK_DUMMY>,
 486                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
 487                                 clock-names = "ipg", "ahb", "per";
 488                                 bus-width = <4>;
 489                                 status = "disabled";
 490                         };
 491
 492                         usdhc2: usdhc@30b50000 {
 493                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 494                                 reg = <0x30b50000 0x10000>;
 495                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 496                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 497                                         <&clks IMX7D_CLK_DUMMY>,
 498                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
 499                                 clock-names = "ipg", "ahb", "per";
 500                                 bus-width = <4>;
 501                                 status = "disabled";
 502                         };
 503
 504                         usdhc3: usdhc@30b60000 {
 505                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 506                                 reg = <0x30b60000 0x10000>;
 507                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 508                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 509                                         <&clks IMX7D_CLK_DUMMY>,
 510                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
 511                                 clock-names = "ipg", "ahb", "per";
 512                                 bus-width = <4>;
 513                                 status = "disabled";
 514                         };
 515                 };
 516         };
 517 };