2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/imx7d-clock.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include "imx7d-pinfunc.h"
47 #include "skeleton.dtsi"
79 compatible = "arm,cortex-a7";
87 clock-latency = <61036>; /* two CLK32 periods */
88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
90 clock-names = "arm", "arm_root_src", "pll_arm", "pll_sys_main";
94 compatible = "arm,cortex-a7";
100 intc: interrupt-controller@31001000 {
101 compatible = "arm,cortex-a7-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x31001000 0x1000>,
111 compatible = "fixed-clock";
113 clock-frequency = <32768>;
114 clock-output-names = "ckil";
118 compatible = "fixed-clock";
120 clock-frequency = <24000000>;
121 clock-output-names = "osc";
125 #address-cells = <1>;
127 compatible = "simple-bus";
128 interrupt-parent = <&intc>;
131 aips1: aips-bus@30000000 {
132 compatible = "fsl,aips-bus", "simple-bus";
133 #address-cells = <1>;
135 reg = <0x30000000 0x400000>;
138 gpio1: gpio@30200000 {
139 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
140 reg = <0x30200000 0x10000>;
141 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
142 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
145 interrupt-controller;
146 #interrupt-cells = <2>;
149 gpio2: gpio@30210000 {
150 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
151 reg = <0x30210000 0x10000>;
152 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
160 gpio3: gpio@30220000 {
161 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
162 reg = <0x30220000 0x10000>;
163 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
171 gpio4: gpio@30230000 {
172 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
173 reg = <0x30230000 0x10000>;
174 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
182 gpio5: gpio@30240000 {
183 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
184 reg = <0x30240000 0x10000>;
185 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 gpio6: gpio@30250000 {
194 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
195 reg = <0x30250000 0x10000>;
196 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
204 gpio7: gpio@30260000 {
205 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
206 reg = <0x30260000 0x10000>;
207 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
215 wdog1: wdog@30280000 {
216 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
217 reg = <0x30280000 0x10000>;
218 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
222 wdog2: wdog@30290000 {
223 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
224 reg = <0x30290000 0x10000>;
225 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
230 wdog3: wdog@302a0000 {
231 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
232 reg = <0x302a0000 0x10000>;
233 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
238 wdog4: wdog@302b0000 {
239 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
240 reg = <0x302b0000 0x10000>;
241 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
247 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
248 reg = <0x302d0000 0x10000>;
249 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clks IMX7D_CLK_DUMMY>,
251 <&clks IMX7D_GPT1_ROOT_CLK>;
252 clock-names = "ipg", "per";
256 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
257 reg = <0x302e0000 0x10000>;
258 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX7D_CLK_DUMMY>,
260 <&clks IMX7D_GPT2_ROOT_CLK>;
261 clock-names = "ipg", "per";
266 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
267 reg = <0x302f0000 0x10000>;
268 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX7D_CLK_DUMMY>,
270 <&clks IMX7D_GPT3_ROOT_CLK>;
271 clock-names = "ipg", "per";
276 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
277 reg = <0x30300000 0x10000>;
278 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX7D_CLK_DUMMY>,
280 <&clks IMX7D_GPT4_ROOT_CLK>;
281 clock-names = "ipg", "per";
285 iomuxc: iomuxc@30330000 {
286 compatible = "fsl,imx7d-iomuxc";
287 reg = <0x30330000 0x10000>;
290 gpr: iomuxc-gpr@30340000 {
291 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
292 reg = <0x30340000 0x10000>;
295 ocotp: ocotp-ctrl@30350000 {
296 compatible = "syscon";
297 reg = <0x30350000 0x10000>;
298 clocks = <&clks IMX7D_CLK_DUMMY>;
302 anatop: anatop@30360000 {
303 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
304 "syscon", "simple-bus";
305 reg = <0x30360000 0x10000>;
306 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
309 reg_1p0d: regulator-vdd1p0d@210 {
310 compatible = "fsl,anatop-regulator";
311 regulator-name = "vdd1p0d";
312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1200000>;
314 anatop-reg-offset = <0x210>;
315 anatop-vol-bit-shift = <8>;
316 anatop-vol-bit-width = <5>;
317 anatop-min-bit-val = <8>;
318 anatop-min-voltage = <800000>;
319 anatop-max-voltage = <1200000>;
320 anatop-enable-bit = <31>;
324 snvs: snvs@30370000 {
325 compatible = "fsl,sec-v4.0-mon", "simple-bus";
326 #address-cells = <1>;
328 ranges = <0 0x30370000 0x10000>;
331 compatible = "fsl,sec-v4.0-mon-rtc-lp";
333 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
339 compatible = "fsl,imx7d-ccm";
340 reg = <0x30380000 0x10000>;
341 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&ckil>, <&osc>;
345 clock-names = "ckil", "osc";
349 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
350 reg = <0x30390000 0x10000>;
351 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
356 aips3: aips-bus@30800000 {
357 compatible = "fsl,aips-bus", "simple-bus";
358 #address-cells = <1>;
360 reg = <0x30800000 0x400000>;
363 uart1: serial@30860000 {
364 compatible = "fsl,imx7d-uart",
366 reg = <0x30860000 0x10000>;
367 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
369 <&clks IMX7D_UART1_ROOT_CLK>;
370 clock-names = "ipg", "per";
374 uart2: serial@30870000 {
375 compatible = "fsl,imx7d-uart",
377 reg = <0x30870000 0x10000>;
378 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
380 <&clks IMX7D_UART2_ROOT_CLK>;
381 clock-names = "ipg", "per";
385 uart3: serial@30880000 {
386 compatible = "fsl,imx7d-uart",
388 reg = <0x30880000 0x10000>;
389 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
391 <&clks IMX7D_UART3_ROOT_CLK>;
392 clock-names = "ipg", "per";
397 #address-cells = <1>;
399 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
400 reg = <0x30a20000 0x10000>;
401 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
407 #address-cells = <1>;
409 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
410 reg = <0x30a30000 0x10000>;
411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
417 #address-cells = <1>;
419 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
420 reg = <0x30a40000 0x10000>;
421 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
427 #address-cells = <1>;
429 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
430 reg = <0x30a50000 0x10000>;
431 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
436 uart4: serial@30a60000 {
437 compatible = "fsl,imx7d-uart",
439 reg = <0x30a60000 0x10000>;
440 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
442 <&clks IMX7D_UART4_ROOT_CLK>;
443 clock-names = "ipg", "per";
447 uart5: serial@30a70000 {
448 compatible = "fsl,imx7d-uart",
450 reg = <0x30a70000 0x10000>;
451 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
453 <&clks IMX7D_UART5_ROOT_CLK>;
454 clock-names = "ipg", "per";
458 uart6: serial@30a80000 {
459 compatible = "fsl,imx7d-uart",
461 reg = <0x30a80000 0x10000>;
462 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
464 <&clks IMX7D_UART6_ROOT_CLK>;
465 clock-names = "ipg", "per";
469 uart7: serial@30a90000 {
470 compatible = "fsl,imx7d-uart",
472 reg = <0x30a90000 0x10000>;
473 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
475 <&clks IMX7D_UART7_ROOT_CLK>;
476 clock-names = "ipg", "per";
480 usdhc1: usdhc@30b40000 {
481 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
482 reg = <0x30b40000 0x10000>;
483 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks IMX7D_CLK_DUMMY>,
485 <&clks IMX7D_CLK_DUMMY>,
486 <&clks IMX7D_USDHC1_ROOT_CLK>;
487 clock-names = "ipg", "ahb", "per";
492 usdhc2: usdhc@30b50000 {
493 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
494 reg = <0x30b50000 0x10000>;
495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX7D_CLK_DUMMY>,
497 <&clks IMX7D_CLK_DUMMY>,
498 <&clks IMX7D_USDHC2_ROOT_CLK>;
499 clock-names = "ipg", "ahb", "per";
504 usdhc3: usdhc@30b60000 {
505 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
506 reg = <0x30b60000 0x10000>;
507 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&clks IMX7D_CLK_DUMMY>,
509 <&clks IMX7D_CLK_DUMMY>,
510 <&clks IMX7D_USDHC3_ROOT_CLK>;
511 clock-names = "ipg", "ahb", "per";