arch/arm/boot/dts/imx7s-warp.dts

   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors.
   3  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 /dts-v1/;
  45
  46 #include <dt-bindings/input/input.h>
  47 #include "imx7s.dtsi"
  48
  49 / {
  50         model = "Warp i.MX7 Board";
  51         compatible = "warp,imx7s-warp", "fsl,imx7s";
  52
  53         memory {
  54                 reg = <0x80000000 0x20000000>;
  55         };
  56
  57         gpio-keys {
  58                 compatible = "gpio-keys";
  59                 pinctrl-0 = <&pinctrl_gpio>;
  60                 autorepeat;
  61
  62                 back {
  63                         label = "Back";
  64                         gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  65                         linux,code = <KEY_BACK>;
  66                         wakeup-source;
  67                 };
  68         };
  69
  70         reg_brcm: regulator-brcm {
  71                 compatible = "regulator-fixed";
  72                 enable-active-high;
  73                 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_brcm_reg>;
  76                 regulator-name = "brcm_reg";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 startup-delay-us = <200000>;
  80         };
  81
  82         sound {
  83                 compatible = "simple-audio-card";
  84                 simple-audio-card,name = "imx7-sgtl5000";
  85                 simple-audio-card,format = "i2s";
  86                 simple-audio-card,bitclock-master = <&dailink_master>;
  87                 simple-audio-card,frame-master = <&dailink_master>;
  88                 simple-audio-card,cpu {
  89                         sound-dai = <&sai1>;
  90                 };
  91
  92                 dailink_master: simple-audio-card,codec {
  93                         sound-dai = <&codec>;
  94                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  95                 };
  96         };
  97 };
  98
  99 &clks {
 100         assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 101         assigned-clock-rates = <884736000>;
 102 };
 103
 104 &cpu0 {
 105         arm-supply = <&sw1a_reg>;
 106 };
 107
 108 &i2c1 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_i2c1>;
 111         status = "okay";
 112
 113         pmic: pfuze3000@08 {
 114                 compatible = "fsl,pfuze3000";
 115                 reg = <0x08>;
 116
 117                 regulators {
 118                         sw1a_reg: sw1a {
 119                                 regulator-min-microvolt = <700000>;
 120                                 regulator-max-microvolt = <1475000>;
 121                                 regulator-boot-on;
 122                                 regulator-always-on;
 123                                 regulator-ramp-delay = <6250>;
 124                         };
 125
 126                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 127                         sw1c_reg: sw1b {
 128                                 regulator-min-microvolt = <700000>;
 129                                 regulator-max-microvolt = <1475000>;
 130                                 regulator-boot-on;
 131                                 regulator-always-on;
 132                                 regulator-ramp-delay = <6250>;
 133                         };
 134
 135                         sw2_reg: sw2 {
 136                                 regulator-min-microvolt = <1500000>;
 137                                 regulator-max-microvolt = <1850000>;
 138                                 regulator-boot-on;
 139                                 regulator-always-on;
 140                         };
 141
 142                         sw3a_reg: sw3 {
 143                                 regulator-min-microvolt = <900000>;
 144                                 regulator-max-microvolt = <1650000>;
 145                                 regulator-boot-on;
 146                                 regulator-always-on;
 147                         };
 148
 149                         swbst_reg: swbst {
 150                                 regulator-min-microvolt = <5000000>;
 151                                 regulator-max-microvolt = <5150000>;
 152                         };
 153
 154                         snvs_reg: vsnvs {
 155                                 regulator-min-microvolt = <1000000>;
 156                                 regulator-max-microvolt = <3000000>;
 157                                 regulator-boot-on;
 158                                 regulator-always-on;
 159                         };
 160
 161                         vref_reg: vrefddr {
 162                                 regulator-boot-on;
 163                                 regulator-always-on;
 164                         };
 165
 166                         vgen1_reg: vldo1 {
 167                                 regulator-min-microvolt = <1800000>;
 168                                 regulator-max-microvolt = <3300000>;
 169                                 regulator-always-on;
 170                         };
 171
 172                         vgen2_reg: vldo2 {
 173                                 regulator-min-microvolt = <800000>;
 174                                 regulator-max-microvolt = <1550000>;
 175                         };
 176
 177                         vgen3_reg: vccsd {
 178                                 regulator-min-microvolt = <2850000>;
 179                                 regulator-max-microvolt = <3300000>;
 180                                 regulator-always-on;
 181                         };
 182
 183                         vgen4_reg: v33 {
 184                                 regulator-min-microvolt = <2850000>;
 185                                 regulator-max-microvolt = <3300000>;
 186                                 regulator-always-on;
 187                         };
 188
 189                         vgen5_reg: vldo3 {
 190                                 regulator-min-microvolt = <1800000>;
 191                                 regulator-max-microvolt = <3300000>;
 192                                 regulator-always-on;
 193                         };
 194
 195                         vgen6_reg: vldo4 {
 196                                 regulator-min-microvolt = <1800000>;
 197                                 regulator-max-microvolt = <3300000>;
 198                                 regulator-always-on;
 199                         };
 200                 };
 201         };
 202 };
 203
 204 &i2c2 {
 205         clock-frequency = <100000>;
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_i2c2>;
 208         status = "okay";
 209 };
 210
 211 &i2c4 {
 212         clock-frequency = <100000>;
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_i2c4>;
 215         status = "okay";
 216
 217         codec: sgtl5000@0a {
 218                 #sound-dai-cells = <0>;
 219                 reg = <0x0a>;
 220                 compatible = "fsl,sgtl5000";
 221                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 224                 VDDA-supply = <&vgen4_reg>;
 225                 VDDIO-supply = <&vgen4_reg>;
 226                 VDDD-supply = <&vgen2_reg>;
 227         };
 228
 229         mpl3115@60 {
 230                 compatible = "fsl,mpl3115";
 231                 reg = <0x60>;
 232         };
 233 };
 234
 235 &sai1 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_sai1>;
 238         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 239                           <&clks IMX7D_SAI1_ROOT_CLK>;
 240         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 241         assigned-clock-rates = <0>, <36864000>;
 242         status = "okay";
 243 };
 244
 245 &uart1 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_uart1>;
 248         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 249         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 250         status = "okay";
 251 };
 252
 253 &usbotg1 {
 254         dr_mode = "peripheral";
 255         status = "okay";
 256 };
 257
 258 &usdhc1 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_usdhc1>;
 261         bus-width = <4>;
 262         keep-power-in-suspend;
 263         no-1-8-v;
 264         non-removable;
 265         vmmc-supply = <&reg_brcm>;
 266         status = "okay";
 267 };
 268
 269 &usdhc3 {
 270         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 271         pinctrl-0 = <&pinctrl_usdhc3>;
 272         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 273         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 274         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 275         assigned-clock-rates = <400000000>;
 276         bus-width = <8>;
 277         fsl,tuning-step = <2>;
 278         non-removable;
 279         status = "okay";
 280 };
 281
 282 &wdog1 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_wdog>;
 285         fsl,ext-reset-output;
 286         status = "okay";
 287 };
 288
 289 &iomuxc {
 290         pinctrl_brcm_reg: brcmreggrp {
 291                 fsl,pins = <
 292                         MX7D_PAD_SD2_WP__GPIO5_IO10     0x14 /* WL_REG_ON */
 293                 >;
 294         };
 295
 296         pinctrl_gpio: gpiogrp {
 297                 fsl,pins = <
 298                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1     0x14
 299                 >;
 300         };
 301
 302         pinctrl_i2c1: i2c1grp {
 303                 fsl,pins = <
 304                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 305                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 306                 >;
 307         };
 308
 309         pinctrl_i2c2: i2c2grp {
 310                 fsl,pins = <
 311                         MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
 312                         MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
 313                 >;
 314         };
 315
 316         pinctrl_i2c4: i2c4grp {
 317                 fsl,pins = <
 318                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
 319                         MX7D_PAD_I2C4_SDA__I2C4_SDA     0x4000007f
 320                 >;
 321         };
 322
 323         pinctrl_sai1: sai1grp {
 324                 fsl,pins = <
 325                         MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
 326                         MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
 327                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 328                         MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
 329                 >;
 330         };
 331
 332         pinctrl_sai1_mclk: sai1mclkgrp {
 333                 fsl,pins = <
 334                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 335                 >;
 336         };
 337
 338         pinctrl_uart1: uart1grp {
 339                 fsl,pins = <
 340                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 341                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 342                 >;
 343         };
 344
 345         pinctrl_usdhc1: usdhc1grp {
 346                 fsl,pins = <
 347                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 348                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 349                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 350                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 351                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 352                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 353                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
 354                 >;
 355         };
 356
 357         pinctrl_usdhc3: usdhc3grp {
 358                 fsl,pins = <
 359                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 360                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 361                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 362                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 363                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 364                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 365                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 366                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 367                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 368                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 369                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x19
 370                 >;
 371         };
 372
 373         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 374                 fsl,pins = <
 375                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 376                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 377                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 378                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 379                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 380                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 381                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 382                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 383                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 384                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 385                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1a
 386                 >;
 387         };
 388
 389         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 390                 fsl,pins = <
 391                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 392                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 393                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 394                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 395                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 396                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 397                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 398                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 399                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 400                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 401                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1b
 402                 >;
 403         };
 404
 405         pinctrl_wdog: wdoggrp {
 406                 fsl,pins = <
 407                         MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B       0x74
 408                 >;
 409         };
 410 };