1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,kirkwood";
7 interrupt-parent = <&intc>;
15 compatible = "marvell,feroceon";
16 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
17 clock-names = "cpu_clk", "ddrclk", "powersave";
27 compatible = "marvell,kirkwood-mbus", "simple-bus";
30 controller = <&mbusc>;
31 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
32 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
36 compatible = "simple-bus";
37 ranges = <0x00000000 0xf1000000 0x0100000
38 0xf4000000 0xf4000000 0x0000400
39 0xf5000000 0xf5000000 0x0000400>;
43 mbusc: mbus-controller@20000 {
44 compatible = "marvell,mbus-controller";
45 reg = <0x20000 0x80>, <0x1500 0x20>;
49 compatible = "marvell,orion-timer";
51 interrupt-parent = <&bridge_intc>;
52 interrupts = <1>, <2>;
53 clocks = <&core_clk 0>;
56 intc: main-interrupt-ctrl@20200 {
57 compatible = "marvell,orion-intc";
59 #interrupt-cells = <1>;
60 reg = <0x20200 0x10>, <0x20210 0x10>;
63 bridge_intc: bridge-interrupt-ctrl@20110 {
64 compatible = "marvell,orion-bridge-intc";
66 #interrupt-cells = <1>;
69 marvell,#interrupts = <6>;
72 core_clk: core-clocks@10030 {
73 compatible = "marvell,kirkwood-core-clock";
79 compatible = "marvell,orion-gpio";
85 #interrupt-cells = <2>;
86 interrupts = <35>, <36>, <37>, <38>;
87 clocks = <&gate_clk 7>;
91 compatible = "marvell,orion-gpio";
97 #interrupt-cells = <2>;
98 interrupts = <39>, <40>, <41>;
99 clocks = <&gate_clk 7>;
103 compatible = "ns16550a";
104 reg = <0x12000 0x100>;
107 clocks = <&gate_clk 7>;
112 compatible = "ns16550a";
113 reg = <0x12100 0x100>;
116 clocks = <&gate_clk 7>;
121 compatible = "marvell,orion-spi";
122 #address-cells = <1>;
126 reg = <0x10600 0x28>;
127 clocks = <&gate_clk 7>;
131 gate_clk: clock-gating-control@2011c {
132 compatible = "marvell,kirkwood-gating-clock";
134 clocks = <&core_clk 0>;
138 wdt: watchdog-timer@20300 {
139 compatible = "marvell,orion-wdt";
140 reg = <0x20300 0x28>;
141 interrupt-parent = <&bridge_intc>;
143 clocks = <&gate_clk 7>;
148 compatible = "marvell,orion-xor";
152 clocks = <&gate_clk 8>;
168 compatible = "marvell,orion-xor";
172 clocks = <&gate_clk 16>;
188 compatible = "marvell,orion-ehci";
189 reg = <0x50000 0x1000>;
191 clocks = <&gate_clk 3>;
196 #address-cells = <1>;
201 compatible = "marvell,orion-nand";
202 reg = <0xf4000000 0x400>;
204 /* set partition map and/or chip-delay in board dts */
205 clocks = <&gate_clk 7>;
210 compatible = "marvell,mv64xxx-i2c";
211 reg = <0x11000 0x20>;
212 #address-cells = <1>;
215 clock-frequency = <100000>;
216 clocks = <&gate_clk 7>;
221 compatible = "marvell,orion-crypto";
222 reg = <0x30000 0x10000>,
224 reg-names = "regs", "sram";
226 clocks = <&gate_clk 17>;
230 mdio: mdio-bus@72004 {
231 compatible = "marvell,orion-mdio";
232 #address-cells = <1>;
234 reg = <0x72004 0x84>;
236 clocks = <&gate_clk 0>;
239 /* add phy nodes in board file */
242 eth0: ethernet-controller@72000 {
243 compatible = "marvell,kirkwood-eth";
244 #address-cells = <1>;
246 reg = <0x72000 0x4000>;
247 clocks = <&gate_clk 0>;
248 marvell,tx-checksum-limit = <1600>;
252 device_type = "network";
253 compatible = "marvell,kirkwood-eth-port";
256 /* overwrite MAC address in bootloader */
257 local-mac-address = [00 00 00 00 00 00];
258 /* set phy-handle property in board file */
262 eth1: ethernet-controller@76000 {
263 compatible = "marvell,kirkwood-eth";
264 #address-cells = <1>;
266 reg = <0x76000 0x4000>;
267 clocks = <&gate_clk 19>;
268 marvell,tx-checksum-limit = <1600>;
272 device_type = "network";
273 compatible = "marvell,kirkwood-eth-port";
276 /* overwrite MAC address in bootloader */
277 local-mac-address = [00 00 00 00 00 00];
278 /* set phy-handle property in board file */