1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,kirkwood";
7 interrupt-parent = <&intc>;
15 compatible = "marvell,feroceon";
17 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
18 clock-names = "cpu_clk", "ddrclk", "powersave";
28 compatible = "marvell,kirkwood-mbus", "simple-bus";
31 controller = <&mbusc>;
32 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
33 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
37 compatible = "simple-bus";
38 ranges = <0x00000000 0xf1000000 0x0100000
39 0xf4000000 0xf4000000 0x0000400
40 0xf5000000 0xf5000000 0x0000400>;
44 mbusc: mbus-controller@20000 {
45 compatible = "marvell,mbus-controller";
46 reg = <0x20000 0x80>, <0x1500 0x20>;
50 compatible = "marvell,orion-timer";
52 interrupt-parent = <&bridge_intc>;
53 interrupts = <1>, <2>;
54 clocks = <&core_clk 0>;
57 intc: main-interrupt-ctrl@20200 {
58 compatible = "marvell,orion-intc";
60 #interrupt-cells = <1>;
61 reg = <0x20200 0x10>, <0x20210 0x10>;
64 bridge_intc: bridge-interrupt-ctrl@20110 {
65 compatible = "marvell,orion-bridge-intc";
67 #interrupt-cells = <1>;
70 marvell,#interrupts = <6>;
73 core_clk: core-clocks@10030 {
74 compatible = "marvell,kirkwood-core-clock";
80 compatible = "marvell,orion-gpio";
86 #interrupt-cells = <2>;
87 interrupts = <35>, <36>, <37>, <38>;
88 clocks = <&gate_clk 7>;
92 compatible = "marvell,orion-gpio";
98 #interrupt-cells = <2>;
99 interrupts = <39>, <40>, <41>;
100 clocks = <&gate_clk 7>;
104 compatible = "ns16550a";
105 reg = <0x12000 0x100>;
108 clocks = <&gate_clk 7>;
113 compatible = "ns16550a";
114 reg = <0x12100 0x100>;
117 clocks = <&gate_clk 7>;
122 compatible = "marvell,orion-spi";
123 #address-cells = <1>;
127 reg = <0x10600 0x28>;
128 clocks = <&gate_clk 7>;
132 gate_clk: clock-gating-control@2011c {
133 compatible = "marvell,kirkwood-gating-clock";
135 clocks = <&core_clk 0>;
139 wdt: watchdog-timer@20300 {
140 compatible = "marvell,orion-wdt";
141 reg = <0x20300 0x28>;
142 interrupt-parent = <&bridge_intc>;
144 clocks = <&gate_clk 7>;
149 compatible = "marvell,orion-xor";
153 clocks = <&gate_clk 8>;
169 compatible = "marvell,orion-xor";
173 clocks = <&gate_clk 16>;
189 compatible = "marvell,orion-ehci";
190 reg = <0x50000 0x1000>;
192 clocks = <&gate_clk 3>;
197 #address-cells = <1>;
202 compatible = "marvell,orion-nand";
203 reg = <0xf4000000 0x400>;
205 /* set partition map and/or chip-delay in board dts */
206 clocks = <&gate_clk 7>;
211 compatible = "marvell,mv64xxx-i2c";
212 reg = <0x11000 0x20>;
213 #address-cells = <1>;
216 clock-frequency = <100000>;
217 clocks = <&gate_clk 7>;
222 compatible = "marvell,orion-crypto";
223 reg = <0x30000 0x10000>,
225 reg-names = "regs", "sram";
227 clocks = <&gate_clk 17>;
231 mdio: mdio-bus@72004 {
232 compatible = "marvell,orion-mdio";
233 #address-cells = <1>;
235 reg = <0x72004 0x84>;
237 clocks = <&gate_clk 0>;
240 /* add phy nodes in board file */
243 eth0: ethernet-controller@72000 {
244 compatible = "marvell,kirkwood-eth";
245 #address-cells = <1>;
247 reg = <0x72000 0x4000>;
248 clocks = <&gate_clk 0>;
249 marvell,tx-checksum-limit = <1600>;
253 device_type = "network";
254 compatible = "marvell,kirkwood-eth-port";
257 /* overwrite MAC address in bootloader */
258 local-mac-address = [00 00 00 00 00 00];
259 /* set phy-handle property in board file */
263 eth1: ethernet-controller@76000 {
264 compatible = "marvell,kirkwood-eth";
265 #address-cells = <1>;
267 reg = <0x76000 0x4000>;
268 clocks = <&gate_clk 19>;
269 marvell,tx-checksum-limit = <1600>;
273 device_type = "network";
274 compatible = "marvell,kirkwood-eth-port";
277 /* overwrite MAC address in bootloader */
278 local-mac-address = [00 00 00 00 00 00];
279 /* set phy-handle property in board file */