arch/arm/boot/dts/kirkwood.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
   4
   5 / {
   6         compatible = "marvell,kirkwood";
   7         interrupt-parent = <&intc>;
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "marvell,feroceon";
  16                         clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  17                         clock-names = "cpu_clk", "ddrclk", "powersave";
  18                 };
  19         };
  20
  21         aliases {
  22                gpio0 = &gpio0;
  23                gpio1 = &gpio1;
  24         };
  25         intc: interrupt-controller {
  26                 compatible = "marvell,orion-intc", "marvell,intc";
  27                 interrupt-controller;
  28                 #interrupt-cells = <1>;
  29                 reg = <0xf1020204 0x04>,
  30                       <0xf1020214 0x04>;
  31         };
  32
  33         mbus {
  34                 compatible = "marvell,kirkwood-mbus", "simple-bus";
  35                 #address-cells = <2>;
  36                 #size-cells = <1>;
  37                 controller = <&mbusc>;
  38                 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
  39                 pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
  40         };
  41
  42         ocp@f1000000 {
  43                 compatible = "simple-bus";
  44                 ranges = <0x00000000 0xf1000000 0x0100000
  45                           0xf4000000 0xf4000000 0x0000400
  46                           0xf5000000 0xf5000000 0x0000400>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49
  50                 mbusc: mbus-controller@20000 {
  51                         compatible = "marvell,mbus-controller";
  52                         reg = <0x20000 0x80>, <0x1500 0x20>;
  53                 };
  54
  55                 core_clk: core-clocks@10030 {
  56                         compatible = "marvell,kirkwood-core-clock";
  57                         reg = <0x10030 0x4>;
  58                         #clock-cells = <1>;
  59                 };
  60
  61                 gpio0: gpio@10100 {
  62                         compatible = "marvell,orion-gpio";
  63                         #gpio-cells = <2>;
  64                         gpio-controller;
  65                         reg = <0x10100 0x40>;
  66                         ngpios = <32>;
  67                         interrupt-controller;
  68                         #interrupt-cells = <2>;
  69                         interrupts = <35>, <36>, <37>, <38>;
  70                         clocks = <&gate_clk 7>;
  71                 };
  72
  73                 gpio1: gpio@10140 {
  74                         compatible = "marvell,orion-gpio";
  75                         #gpio-cells = <2>;
  76                         gpio-controller;
  77                         reg = <0x10140 0x40>;
  78                         ngpios = <18>;
  79                         interrupt-controller;
  80                         #interrupt-cells = <2>;
  81                         interrupts = <39>, <40>, <41>;
  82                         clocks = <&gate_clk 7>;
  83                 };
  84
  85                 serial@12000 {
  86                         compatible = "ns16550a";
  87                         reg = <0x12000 0x100>;
  88                         reg-shift = <2>;
  89                         interrupts = <33>;
  90                         clocks = <&gate_clk 7>;
  91                         status = "disabled";
  92                 };
  93
  94                 serial@12100 {
  95                         compatible = "ns16550a";
  96                         reg = <0x12100 0x100>;
  97                         reg-shift = <2>;
  98                         interrupts = <34>;
  99                         clocks = <&gate_clk 7>;
 100                         status = "disabled";
 101                 };
 102
 103                 spi@10600 {
 104                         compatible = "marvell,orion-spi";
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         cell-index = <0>;
 108                         interrupts = <23>;
 109                         reg = <0x10600 0x28>;
 110                         clocks = <&gate_clk 7>;
 111                         status = "disabled";
 112                 };
 113
 114                 gate_clk: clock-gating-control@2011c {
 115                         compatible = "marvell,kirkwood-gating-clock";
 116                         reg = <0x2011c 0x4>;
 117                         clocks = <&core_clk 0>;
 118                         #clock-cells = <1>;
 119                 };
 120
 121                 wdt@20300 {
 122                         compatible = "marvell,orion-wdt";
 123                         reg = <0x20300 0x28>;
 124                         clocks = <&gate_clk 7>;
 125                         status = "okay";
 126                 };
 127
 128                 xor@60800 {
 129                         compatible = "marvell,orion-xor";
 130                         reg = <0x60800 0x100
 131                                0x60A00 0x100>;
 132                         status = "okay";
 133                         clocks = <&gate_clk 8>;
 134
 135                         xor00 {
 136                               interrupts = <5>;
 137                               dmacap,memcpy;
 138                               dmacap,xor;
 139                         };
 140                         xor01 {
 141                               interrupts = <6>;
 142                               dmacap,memcpy;
 143                               dmacap,xor;
 144                               dmacap,memset;
 145                         };
 146                 };
 147
 148                 xor@60900 {
 149                         compatible = "marvell,orion-xor";
 150                         reg = <0x60900 0x100
 151                                0xd0B00 0x100>;
 152                         status = "okay";
 153                         clocks = <&gate_clk 16>;
 154
 155                         xor00 {
 156                               interrupts = <7>;
 157                               dmacap,memcpy;
 158                               dmacap,xor;
 159                         };
 160                         xor01 {
 161                               interrupts = <8>;
 162                               dmacap,memcpy;
 163                               dmacap,xor;
 164                               dmacap,memset;
 165                         };
 166                 };
 167
 168                 ehci@50000 {
 169                         compatible = "marvell,orion-ehci";
 170                         reg = <0x50000 0x1000>;
 171                         interrupts = <19>;
 172                         clocks = <&gate_clk 3>;
 173                         status = "okay";
 174                 };
 175
 176                 nand@3000000 {
 177                         #address-cells = <1>;
 178                         #size-cells = <1>;
 179                         cle = <0>;
 180                         ale = <1>;
 181                         bank-width = <1>;
 182                         compatible = "marvell,orion-nand";
 183                         reg = <0xf4000000 0x400>;
 184                         chip-delay = <25>;
 185                         /* set partition map and/or chip-delay in board dts */
 186                         clocks = <&gate_clk 7>;
 187                         status = "disabled";
 188                 };
 189
 190                 i2c@11000 {
 191                         compatible = "marvell,mv64xxx-i2c";
 192                         reg = <0x11000 0x20>;
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         interrupts = <29>;
 196                         clock-frequency = <100000>;
 197                         clocks = <&gate_clk 7>;
 198                         status = "disabled";
 199                 };
 200
 201                 crypto@30000 {
 202                         compatible = "marvell,orion-crypto";
 203                         reg = <0x30000 0x10000>,
 204                               <0xf5000000 0x800>;
 205                         reg-names = "regs", "sram";
 206                         interrupts = <22>;
 207                         clocks = <&gate_clk 17>;
 208                         status = "okay";
 209                 };
 210         };
 211 };