arch/arm/boot/dts/lpc18xx.dtsi

   1 /*
   2  * Common base for NXP LPC18xx and LPC43xx devices.
   3  *
   4  * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
   5  *
   6  * This code is released using a dual license strategy: BSD/GPL
   7  * You can choose the licence that better fits your requirements.
   8  *
   9  * Released under the terms of 3-clause BSD License
  10  * Released under the terms of GNU General Public License Version 2.0
  11  *
  12  */
  13
  14 #include "armv7-m.dtsi"
  15
  16 #include "dt-bindings/clock/lpc18xx-cgu.h"
  17 #include "dt-bindings/clock/lpc18xx-ccu.h"
  18
  19 #define LPC_PIN(port, pin)      (0x##port * 32 + pin)
  20 #define LPC_GPIO(port, pin)     (port * 32 + pin)
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,cortex-m3";
  29                         device_type = "cpu";
  30                         reg = <0x0>;
  31                         clocks = <&ccu1 CLK_CPU_CORE>;
  32                 };
  33         };
  34
  35         clocks {
  36                 xtal: xtal {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <12000000>;
  40                 };
  41
  42                 xtal32: xtal32 {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <32768>;
  46                 };
  47
  48                 enet_rx_clk: enet_rx_clk {
  49                         compatible = "fixed-clock";
  50                         #clock-cells = <0>;
  51                         clock-frequency = <0>;
  52                         clock-output-names = "enet_rx_clk";
  53                 };
  54
  55                 enet_tx_clk: enet_tx_clk {
  56                         compatible = "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <0>;
  59                         clock-output-names = "enet_tx_clk";
  60                 };
  61
  62                 gp_clkin: gp_clkin {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <0>;
  66                         clock-output-names = "gp_clkin";
  67                 };
  68         };
  69
  70         soc {
  71                 mmcsd: mmcsd@40004000 {
  72                         compatible = "snps,dw-mshc";
  73                         reg = <0x40004000 0x1000>;
  74                         interrupts = <6>;
  75                         num-slots = <1>;
  76                         clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
  77                         clock-names = "ciu", "biu";
  78                         status = "disabled";
  79                 };
  80
  81                 usb0: ehci@40006100 {
  82                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
  83                         reg = <0x40006100 0x100>;
  84                         interrupts = <8>;
  85                         clocks = <&ccu1 CLK_CPU_USB0>;
  86                         has-transaction-translator;
  87                         status = "disabled";
  88                 };
  89
  90                 usb1: ehci@40007100 {
  91                         compatible = "nxp,lpc1850-ehci", "generic-ehci";
  92                         reg = <0x40007100 0x100>;
  93                         interrupts = <9>;
  94                         clocks = <&ccu1 CLK_CPU_USB1>;
  95                         status = "disabled";
  96                 };
  97
  98                 mac: ethernet@40010000 {
  99                         compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
 100                         reg = <0x40010000 0x2000>;
 101                         interrupts = <5>;
 102                         interrupt-names = "macirq";
 103                         clocks = <&ccu1 CLK_CPU_ETHERNET>;
 104                         clock-names = "stmmaceth";
 105                         status = "disabled";
 106                 };
 107
 108                 creg: syscon@40043000 {
 109                         compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
 110                         reg = <0x40043000 0x1000>;
 111                         clocks = <&ccu1 CLK_CPU_CREG>;
 112                 };
 113
 114                 cgu: clock-controller@40050000 {
 115                         compatible = "nxp,lpc1850-cgu";
 116                         reg = <0x40050000 0x1000>;
 117                         #clock-cells = <1>;
 118                         clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
 119                 };
 120
 121                 ccu1: clock-controller@40051000 {
 122                         compatible = "nxp,lpc1850-ccu";
 123                         reg = <0x40051000 0x1000>;
 124                         #clock-cells = <1>;
 125                         clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
 126                                  <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
 127                                  <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
 128                                  <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
 129                         clock-names = "base_apb3_clk",   "base_apb1_clk",
 130                                       "base_spifi_clk",  "base_cpu_clk",
 131                                       "base_periph_clk", "base_usb0_clk",
 132                                       "base_usb1_clk",   "base_spi_clk";
 133                 };
 134
 135                 ccu2: clock-controller@40052000 {
 136                         compatible = "nxp,lpc1850-ccu";
 137                         reg = <0x40052000 0x1000>;
 138                         #clock-cells = <1>;
 139                         clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
 140                                  <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
 141                                  <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
 142                                  <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
 143                         clock-names = "base_audio_clk", "base_uart3_clk",
 144                                       "base_uart2_clk", "base_uart1_clk",
 145                                       "base_uart0_clk", "base_ssp1_clk",
 146                                       "base_ssp0_clk",  "base_sdio_clk";
 147                 };
 148
 149                 uart0: serial@40081000 {
 150                         compatible = "nxp,lpc1850-uart", "ns16550a";
 151                         reg = <0x40081000 0x1000>;
 152                         reg-shift = <2>;
 153                         interrupts = <24>;
 154                         clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
 155                         clock-names = "uartclk", "reg";
 156                         status = "disabled";
 157                 };
 158
 159                 uart1: serial@40082000 {
 160                         compatible = "nxp,lpc1850-uart", "ns16550a";
 161                         reg = <0x40082000 0x1000>;
 162                         reg-shift = <2>;
 163                         interrupts = <25>;
 164                         clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
 165                         clock-names = "uartclk", "reg";
 166                         status = "disabled";
 167                 };
 168
 169                 ssp0: spi@40083000 {
 170                         compatible = "arm,pl022", "arm,primecell";
 171                         reg = <0x40083000 0x1000>;
 172                         interrupts = <22>;
 173                         clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
 174                         clock-names = "sspclk", "apb_pclk";
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         status = "disabled";
 178                 };
 179
 180                 timer0: timer@40084000 {
 181                         compatible = "nxp,lpc3220-timer";
 182                         reg = <0x40084000 0x1000>;
 183                         interrupts = <12>;
 184                         clocks = <&ccu1 CLK_CPU_TIMER0>;
 185                         clock-names = "timerclk";
 186                 };
 187
 188                 timer1: timer@40085000 {
 189                         compatible = "nxp,lpc3220-timer";
 190                         reg = <0x40085000 0x1000>;
 191                         interrupts = <13>;
 192                         clocks = <&ccu1 CLK_CPU_TIMER1>;
 193                         clock-names = "timerclk";
 194                 };
 195
 196                 pinctrl: pinctrl@40086000 {
 197                         compatible = "nxp,lpc1850-scu";
 198                         reg = <0x40086000 0x1000>;
 199                         clocks = <&ccu1 CLK_CPU_SCU>;
 200                 };
 201
 202                 can1: can@400a4000 {
 203                         compatible = "bosch,c_can";
 204                         reg = <0x400a4000 0x1000>;
 205                         interrupts = <43>;
 206                         clocks = <&ccu1 CLK_APB1_CAN1>;
 207                         status = "disabled";
 208                 };
 209
 210                 uart2: serial@400c1000 {
 211                         compatible = "nxp,lpc1850-uart", "ns16550a";
 212                         reg = <0x400c1000 0x1000>;
 213                         reg-shift = <2>;
 214                         interrupts = <26>;
 215                         clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
 216                         clock-names = "uartclk", "reg";
 217                         status = "disabled";
 218                 };
 219
 220                 uart3: serial@400c2000 {
 221                         compatible = "nxp,lpc1850-uart", "ns16550a";
 222                         reg = <0x400c2000 0x1000>;
 223                         reg-shift = <2>;
 224                         interrupts = <27>;
 225                         clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
 226                         clock-names = "uartclk", "reg";
 227                         status = "disabled";
 228                 };
 229
 230                 timer2: timer@400c3000 {
 231                         compatible = "nxp,lpc3220-timer";
 232                         reg = <0x400c3000 0x1000>;
 233                         interrupts = <14>;
 234                         clocks = <&ccu1 CLK_CPU_TIMER2>;
 235                         clock-names = "timerclk";
 236                 };
 237
 238                 timer3: timer@400c4000 {
 239                         compatible = "nxp,lpc3220-timer";
 240                         reg = <0x400c4000 0x1000>;
 241                         interrupts = <15>;
 242                         clocks = <&ccu1 CLK_CPU_TIMER3>;
 243                         clock-names = "timerclk";
 244                 };
 245
 246                 ssp1: spi@400c5000 {
 247                         compatible = "arm,pl022", "arm,primecell";
 248                         reg = <0x400c5000 0x1000>;
 249                         interrupts = <23>;
 250                         clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
 251                         clock-names = "sspclk", "apb_pclk";
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         status = "disabled";
 255                 };
 256
 257                 can0: can@400e2000 {
 258                         compatible = "bosch,c_can";
 259                         reg = <0x400e2000 0x1000>;
 260                         interrupts = <51>;
 261                         clocks = <&ccu1 CLK_APB3_CAN0>;
 262                         status = "disabled";
 263                 };
 264
 265                 gpio: gpio@400f4000 {
 266                         compatible = "nxp,lpc1850-gpio";
 267                         reg = <0x400f4000 0x4000>;
 268                         clocks = <&ccu1 CLK_CPU_GPIO>;
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271                         gpio-ranges =   <&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
 272                                         <&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
 273                                         <&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
 274                                         <&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
 275                                         <&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
 276                                         <&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
 277                                         <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
 278                                         <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
 279                                         <&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
 280                                         <&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
 281                                         <&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
 282                                         <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
 283                                         <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
 284                                         <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
 285                                         <&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
 286                                         <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
 287                                         <&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
 288                                         <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
 289                                         <&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
 290                                         <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
 291                                         <&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
 292                                         <&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
 293                                         <&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
 294                                         <&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
 295                                         <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
 296                                         <&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
 297                                         <&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
 298                                         <&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
 299                                         <&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
 300                                         <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
 301                                         <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
 302                                         <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
 303                                         <&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
 304                                         <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
 305                                         <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
 306                                         <&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
 307                                         <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
 308                                         <&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
 309                                         <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
 310                                         <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
 311                 };
 312         };
 313 };