2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Erin.Lo <erin.lo@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/clock/mt2701-clk.h>
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/mt2701-resets.h>
20 #include "skeleton64.dtsi"
21 #include "mt2701-pinfunc.h"
24 compatible = "mediatek,mt2701";
25 interrupt-parent = <&sysirq>;
30 enable-method = "mediatek,mt81xx-tz-smp";
34 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7";
44 compatible = "arm,cortex-a7";
49 compatible = "arm,cortex-a7";
59 trustzone-bootinfo@80002000 {
60 compatible = "mediatek,trustzone-bootinfo";
61 reg = <0 0x80002000 0 0x1000>;
65 system_clk: dummy13m {
66 compatible = "fixed-clock";
67 clock-frequency = <13000000>;
72 compatible = "fixed-clock";
73 clock-frequency = <32000>;
77 clk26m: oscillator@0 {
78 compatible = "fixed-clock";
80 clock-frequency = <26000000>;
81 clock-output-names = "clk26m";
84 rtc32k: oscillator@1 {
85 compatible = "fixed-clock";
87 clock-frequency = <32000>;
88 clock-output-names = "rtc32k";
92 cpu_thermal: cpu_thermal {
93 polling-delay-passive = <1000>; /* milliseconds */
94 polling-delay = <1000>; /* milliseconds */
96 thermal-sensors = <&thermal 0>;
97 sustainable-power = <1000>;
100 threshold: trip-point@0 {
101 temperature = <68000>;
106 target: trip-point@1 {
107 temperature = <85000>;
112 cpu_crit: cpu_crit@0 {
113 temperature = <115000>;
122 compatible = "arm,armv7-timer";
123 interrupt-parent = <&gic>;
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
130 topckgen: syscon@10000000 {
131 compatible = "mediatek,mt2701-topckgen", "syscon";
132 reg = <0 0x10000000 0 0x1000>;
136 infracfg: syscon@10001000 {
137 compatible = "mediatek,mt2701-infracfg", "syscon";
138 reg = <0 0x10001000 0 0x1000>;
143 pericfg: syscon@10003000 {
144 compatible = "mediatek,mt2701-pericfg", "syscon";
145 reg = <0 0x10003000 0 0x1000>;
150 syscfg_pctl_a: syscfg@10005000 {
151 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
152 reg = <0 0x10005000 0 0x1000>;
155 scpsys: scpsys@10006000 {
156 compatible = "mediatek,mt2701-scpsys", "syscon";
157 #power-domain-cells = <1>;
158 reg = <0 0x10006000 0 0x1000>;
159 infracfg = <&infracfg>;
160 clocks = <&topckgen CLK_TOP_MM_SEL>,
161 <&topckgen CLK_TOP_MFG_SEL>,
162 <&topckgen CLK_TOP_ETHIF_SEL>;
163 clock-names = "mm", "mfg", "ethif";
166 watchdog: watchdog@10007000 {
167 compatible = "mediatek,mt2701-wdt",
168 "mediatek,mt6589-wdt";
169 reg = <0 0x10007000 0 0x100>;
172 timer: timer@10008000 {
173 compatible = "mediatek,mt2701-timer",
174 "mediatek,mt6577-timer";
175 reg = <0 0x10008000 0 0x80>;
176 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
177 clocks = <&system_clk>, <&rtc_clk>;
178 clock-names = "system-clk", "rtc-clk";
181 pio: pinctrl@1000b000 {
182 compatible = "mediatek,mt2701-pinctrl";
183 reg = <0 0x1000b000 0 0x1000>;
184 mediatek,pctl-regmap = <&syscfg_pctl_a>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
194 smi_common: smi@1000c000 {
195 compatible = "mediatek,mt2701-smi-common";
196 reg = <0 0x1000c000 0 0x1000>;
197 clocks = <&infracfg CLK_INFRA_SMI>,
198 <&mmsys CLK_MM_SMI_COMMON>,
199 <&infracfg CLK_INFRA_SMI>;
200 clock-names = "apb", "smi", "async";
201 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
204 sysirq: interrupt-controller@10200100 {
205 compatible = "mediatek,mt2701-sysirq",
206 "mediatek,mt6577-sysirq";
207 interrupt-controller;
208 #interrupt-cells = <3>;
209 interrupt-parent = <&gic>;
210 reg = <0 0x10200100 0 0x1c>;
213 iommu: mmsys_iommu@10205000 {
214 compatible = "mediatek,mt2701-m4u";
215 reg = <0 0x10205000 0 0x1000>;
216 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
217 clocks = <&infracfg CLK_INFRA_M4U>;
218 clock-names = "bclk";
219 mediatek,larbs = <&larb0 &larb1 &larb2>;
223 apmixedsys: syscon@10209000 {
224 compatible = "mediatek,mt2701-apmixedsys", "syscon";
225 reg = <0 0x10209000 0 0x1000>;
229 gic: interrupt-controller@10211000 {
230 compatible = "arm,cortex-a7-gic";
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 interrupt-parent = <&gic>;
234 reg = <0 0x10211000 0 0x1000>,
235 <0 0x10212000 0 0x2000>,
236 <0 0x10214000 0 0x2000>,
237 <0 0x10216000 0 0x2000>;
240 auxadc: adc@11001000 {
241 compatible = "mediatek,mt2701-auxadc";
242 reg = <0 0x11001000 0 0x1000>;
243 clocks = <&pericfg CLK_PERI_AUXADC>;
244 clock-names = "main";
245 #io-channel-cells = <1>;
249 uart0: serial@11002000 {
250 compatible = "mediatek,mt2701-uart",
251 "mediatek,mt6577-uart";
252 reg = <0 0x11002000 0 0x400>;
253 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
254 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
255 clock-names = "baud", "bus";
259 uart1: serial@11003000 {
260 compatible = "mediatek,mt2701-uart",
261 "mediatek,mt6577-uart";
262 reg = <0 0x11003000 0 0x400>;
263 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
264 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
265 clock-names = "baud", "bus";
269 uart2: serial@11004000 {
270 compatible = "mediatek,mt2701-uart",
271 "mediatek,mt6577-uart";
272 reg = <0 0x11004000 0 0x400>;
273 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
274 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
275 clock-names = "baud", "bus";
279 uart3: serial@11005000 {
280 compatible = "mediatek,mt2701-uart",
281 "mediatek,mt6577-uart";
282 reg = <0 0x11005000 0 0x400>;
283 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
284 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
285 clock-names = "baud", "bus";
290 compatible = "mediatek,mt2701-spi";
291 #address-cells = <1>;
293 reg = <0 0x1100a000 0 0x100>;
294 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
295 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
296 <&topckgen CLK_TOP_SPI0_SEL>,
297 <&pericfg CLK_PERI_SPI0>;
298 clock-names = "parent-clk", "sel-clk", "spi-clk";
302 thermal: thermal@1100b000 {
303 #thermal-sensor-cells = <0>;
304 compatible = "mediatek,mt2701-thermal";
305 reg = <0 0x1100b000 0 0x1000>;
306 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
307 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
308 clock-names = "therm", "auxadc";
309 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
310 reset-names = "therm";
311 mediatek,auxadc = <&auxadc>;
312 mediatek,apmixedsys = <&apmixedsys>;
315 nandc: nfi@1100d000 {
316 compatible = "mediatek,mt2701-nfc";
317 reg = <0 0x1100d000 0 0x1000>;
318 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
319 clocks = <&pericfg CLK_PERI_NFI>,
320 <&pericfg CLK_PERI_NFI_PAD>;
321 clock-names = "nfi_clk", "pad_clk";
324 #address-cells = <1>;
329 compatible = "mediatek,mt2701-ecc";
330 reg = <0 0x1100e000 0 0x1000>;
331 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
332 clocks = <&pericfg CLK_PERI_NFI_ECC>;
333 clock-names = "nfiecc_clk";
338 compatible = "mediatek,mt2701-spi";
339 #address-cells = <1>;
341 reg = <0 0x11016000 0 0x100>;
342 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
344 <&topckgen CLK_TOP_SPI1_SEL>,
345 <&pericfg CLK_PERI_SPI1>;
346 clock-names = "parent-clk", "sel-clk", "spi-clk";
351 compatible = "mediatek,mt2701-spi";
352 #address-cells = <1>;
354 reg = <0 0x11017000 0 0x1000>;
355 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
356 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
357 <&topckgen CLK_TOP_SPI2_SEL>,
358 <&pericfg CLK_PERI_SPI2>;
359 clock-names = "parent-clk", "sel-clk", "spi-clk";
363 mmsys: syscon@14000000 {
364 compatible = "mediatek,mt2701-mmsys", "syscon";
365 reg = <0 0x14000000 0 0x1000>;
369 larb0: larb@14010000 {
370 compatible = "mediatek,mt2701-smi-larb";
371 reg = <0 0x14010000 0 0x1000>;
372 mediatek,smi = <&smi_common>;
373 clocks = <&mmsys CLK_MM_SMI_LARB0>,
374 <&mmsys CLK_MM_SMI_LARB0>;
375 clock-names = "apb", "smi";
376 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
379 imgsys: syscon@15000000 {
380 compatible = "mediatek,mt2701-imgsys", "syscon";
381 reg = <0 0x15000000 0 0x1000>;
385 larb2: larb@15001000 {
386 compatible = "mediatek,mt2701-smi-larb";
387 reg = <0 0x15001000 0 0x1000>;
388 mediatek,smi = <&smi_common>;
389 clocks = <&imgsys CLK_IMG_SMI_COMM>,
390 <&imgsys CLK_IMG_SMI_COMM>;
391 clock-names = "apb", "smi";
392 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
395 vdecsys: syscon@16000000 {
396 compatible = "mediatek,mt2701-vdecsys", "syscon";
397 reg = <0 0x16000000 0 0x1000>;
401 larb1: larb@16010000 {
402 compatible = "mediatek,mt2701-smi-larb";
403 reg = <0 0x16010000 0 0x1000>;
404 mediatek,smi = <&smi_common>;
405 clocks = <&vdecsys CLK_VDEC_CKGEN>,
406 <&vdecsys CLK_VDEC_LARB>;
407 clock-names = "apb", "smi";
408 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
411 hifsys: syscon@1a000000 {
412 compatible = "mediatek,mt2701-hifsys", "syscon";
413 reg = <0 0x1a000000 0 0x1000>;
417 ethsys: syscon@1b000000 {
418 compatible = "mediatek,mt2701-ethsys", "syscon";
419 reg = <0 0x1b000000 0 0x1000>;
423 bdpsys: syscon@1c000000 {
424 compatible = "mediatek,mt2701-bdpsys", "syscon";
425 reg = <0 0x1c000000 0 0x1000>;