2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Erin.Lo <erin.lo@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "skeleton64.dtsi"
20 compatible = "mediatek,mt2701";
21 interrupt-parent = <&sysirq>;
26 enable-method = "mediatek,mt81xx-tz-smp";
30 compatible = "arm,cortex-a7";
35 compatible = "arm,cortex-a7";
40 compatible = "arm,cortex-a7";
45 compatible = "arm,cortex-a7";
55 trustzone-bootinfo@80002000 {
56 compatible = "mediatek,trustzone-bootinfo";
57 reg = <0 0x80002000 0 0x1000>;
61 system_clk: dummy13m {
62 compatible = "fixed-clock";
63 clock-frequency = <13000000>;
68 compatible = "fixed-clock";
69 clock-frequency = <32000>;
74 compatible = "fixed-clock";
75 clock-frequency = <26000000>;
80 compatible = "arm,armv7-timer";
81 interrupt-parent = <&gic>;
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
88 watchdog: watchdog@10007000 {
89 compatible = "mediatek,mt2701-wdt",
90 "mediatek,mt6589-wdt";
91 reg = <0 0x10007000 0 0x100>;
94 timer: timer@10008000 {
95 compatible = "mediatek,mt2701-timer",
96 "mediatek,mt6577-timer";
97 reg = <0 0x10008000 0 0x80>;
98 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
99 clocks = <&system_clk>, <&rtc_clk>;
100 clock-names = "system-clk", "rtc-clk";
103 sysirq: interrupt-controller@10200100 {
104 compatible = "mediatek,mt2701-sysirq",
105 "mediatek,mt6577-sysirq";
106 interrupt-controller;
107 #interrupt-cells = <3>;
108 interrupt-parent = <&gic>;
109 reg = <0 0x10200100 0 0x1c>;
112 gic: interrupt-controller@10211000 {
113 compatible = "arm,cortex-a7-gic";
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 interrupt-parent = <&gic>;
117 reg = <0 0x10211000 0 0x1000>,
118 <0 0x10212000 0 0x1000>,
119 <0 0x10214000 0 0x2000>,
120 <0 0x10216000 0 0x2000>;
123 uart0: serial@11002000 {
124 compatible = "mediatek,mt2701-uart",
125 "mediatek,mt6577-uart";
126 reg = <0 0x11002000 0 0x400>;
127 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
128 clocks = <&uart_clk>;
132 uart1: serial@11003000 {
133 compatible = "mediatek,mt2701-uart",
134 "mediatek,mt6577-uart";
135 reg = <0 0x11003000 0 0x400>;
136 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
137 clocks = <&uart_clk>;
141 uart2: serial@11004000 {
142 compatible = "mediatek,mt2701-uart",
143 "mediatek,mt6577-uart";
144 reg = <0 0x11004000 0 0x400>;
145 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
146 clocks = <&uart_clk>;
150 uart3: serial@11005000 {
151 compatible = "mediatek,mt2701-uart",
152 "mediatek,mt6577-uart";
153 reg = <0 0x11005000 0 0x400>;
154 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
155 clocks = <&uart_clk>;