arch/arm/boot/dts/mt8135.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Joe.C <yingjoe.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/clock/mt8135-clk.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/reset-controller/mt8135-resets.h>
  19 #include "skeleton64.dtsi"
  20 #include "mt8135-pinfunc.h"
  21
  22 / {
  23         compatible = "mediatek,mt8135";
  24         interrupt-parent = <&sysirq>;
  25
  26         cpu-map {
  27                 cluster0 {
  28                         core0 {
  29                                 cpu = <&cpu0>;
  30                         };
  31                         core1 {
  32                                 cpu = <&cpu1>;
  33                         };
  34                 };
  35
  36                 cluster1 {
  37                         core0 {
  38                                 cpu = <&cpu2>;
  39                         };
  40                         core1 {
  41                                 cpu = <&cpu3>;
  42                         };
  43                 };
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0x000>;
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a7";
  59                         reg = <0x001>;
  60                 };
  61
  62                 cpu2: cpu@100 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x100>;
  66                 };
  67
  68                 cpu3: cpu@101 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a15";
  71                         reg = <0x101>;
  72                 };
  73         };
  74
  75         clocks {
  76                 #address-cells = <2>;
  77                 #size-cells = <2>;
  78                 compatible = "simple-bus";
  79                 ranges;
  80
  81                 system_clk: dummy13m {
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <13000000>;
  84                         #clock-cells = <0>;
  85                 };
  86
  87                 rtc_clk: dummy32k {
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <32000>;
  90                         #clock-cells = <0>;
  91                 };
  92
  93                 uart_clk: dummy26m {
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <26000000>;
  96                         #clock-cells = <0>;
  97                 };
  98
  99                 clk26m: clk26m {
 100                         compatible = "fixed-clock";
 101                         #clock-cells = <0>;
 102                         clock-frequency = <26000000>;
 103                 };
 104         };
 105
 106         soc {
 107                 #address-cells = <2>;
 108                 #size-cells = <2>;
 109                 compatible = "simple-bus";
 110                 ranges;
 111
 112                 topckgen: topckgen@10000000 {
 113                         compatible = "mediatek,mt8135-topckgen";
 114                         reg = <0 0x10000000 0 0x1000>;
 115                         #clock-cells = <1>;
 116                 };
 117
 118                 infracfg: infracfg@10001000 {
 119                         #reset-cells = <1>;
 120                         #clock-cells = <1>;
 121                         compatible = "mediatek,mt8135-infracfg", "syscon";
 122                         reg = <0 0x10001000 0 0x1000>;
 123                 };
 124
 125                 pericfg: pericfg@10003000 {
 126                         #reset-cells = <1>;
 127                         #clock-cells = <1>;
 128                         compatible = "mediatek,mt8135-pericfg", "syscon";
 129                         reg = <0 0x10003000 0 0x1000>;
 130                 };
 131
 132                 /*
 133                  * Pinctrl access register at 0x10005000 and 0x1020c000 through
 134                  * regmap. Register 0x1000b000 is used by EINT.
 135                  */
 136                 pio: pinctrl@10005000 {
 137                         compatible = "mediatek,mt8135-pinctrl";
 138                         reg = <0 0x1000b000 0 0x1000>;
 139                         mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
 140                         pins-are-numbered;
 141                         gpio-controller;
 142                         #gpio-cells = <2>;
 143                         interrupt-controller;
 144                         #interrupt-cells = <2>;
 145                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 148                 };
 149
 150                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 151                         compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 152                         reg = <0 0x10005000 0 0x1000>;
 153                 };
 154
 155                 timer: timer@10008000 {
 156                         compatible = "mediatek,mt8135-timer",
 157                                         "mediatek,mt6577-timer";
 158                         reg = <0 0x10008000 0 0x80>;
 159                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
 160                         clocks = <&system_clk>, <&rtc_clk>;
 161                         clock-names = "system-clk", "rtc-clk";
 162                 };
 163
 164                 pwrap: pwrap@1000f000 {
 165                         compatible = "mediatek,mt8135-pwrap";
 166                         reg = <0 0x1000f000 0 0x1000>,
 167                                 <0 0x11017000 0 0x1000>;
 168                         reg-names = "pwrap", "pwrap-bridge";
 169                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 170                         resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
 171                                         <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
 172                         reset-names = "pwrap", "pwrap-bridge";
 173                         clocks = <&clk26m>, <&clk26m>;
 174                         clock-names = "spi", "wrap";
 175                 };
 176
 177                 sysirq: interrupt-controller@10200030 {
 178                         compatible = "mediatek,mt8135-sysirq",
 179                                      "mediatek,mt6577-sysirq";
 180                         interrupt-controller;
 181                         #interrupt-cells = <3>;
 182                         interrupt-parent = <&gic>;
 183                         reg = <0 0x10200030 0 0x1c>;
 184                 };
 185
 186                 apmixedsys: apmixedsys@10209000 {
 187                         compatible = "mediatek,mt8135-apmixedsys";
 188                         reg = <0 0x10209000 0 0x1000>;
 189                         #clock-cells = <1>;
 190                 };
 191
 192                 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
 193                         compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 194                         reg = <0 0x1020c000 0 0x1000>;
 195                 };
 196
 197                 gic: interrupt-controller@10211000 {
 198                         compatible = "arm,cortex-a15-gic";
 199                         interrupt-controller;
 200                         #interrupt-cells = <3>;
 201                         interrupt-parent = <&gic>;
 202                         reg = <0 0x10211000 0 0x1000>,
 203                               <0 0x10212000 0 0x1000>,
 204                               <0 0x10214000 0 0x2000>,
 205                               <0 0x10216000 0 0x2000>;
 206                 };
 207
 208                 uart0: serial@11006000 {
 209                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 210                         reg = <0 0x11006000 0 0x400>;
 211                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 212                         clocks = <&uart_clk>;
 213                         status = "disabled";
 214                 };
 215
 216                 uart1: serial@11007000 {
 217                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 218                         reg = <0 0x11007000 0 0x400>;
 219                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 220                         clocks = <&uart_clk>;
 221                         status = "disabled";
 222                 };
 223
 224                 uart2: serial@11008000 {
 225                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 226                         reg = <0 0x11008000 0 0x400>;
 227                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 228                         clocks = <&uart_clk>;
 229                         status = "disabled";
 230                 };
 231
 232                 uart3: serial@11009000 {
 233                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 234                         reg = <0 0x11009000 0 0x400>;
 235                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 236                         clocks = <&uart_clk>;
 237                         status = "disabled";
 238                 };
 239
 240         };
 241 };