2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
44 gic: interrupt-controller@48241000 {
45 compatible = "arm,cortex-a9-gic";
47 #interrupt-cells = <3>;
48 reg = <0x48241000 0x1000>,
52 L2: l2-cache-controller@48242000 {
53 compatible = "arm,pl310-cache";
54 reg = <0x48242000 0x1000>;
59 local-timer@48240600 {
60 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x48240600 0x20>;
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
66 * The soc node represents the soc top level view. It is uses for IPs
67 * that are not memory mapped in the MPU view or for the MPU itself.
70 compatible = "ti,omap-infra";
72 compatible = "ti,omap4-mpu";
77 compatible = "ti,omap3-c64";
82 compatible = "ti,ivahd";
88 * XXX: Use a flat representation of the OMAP4 interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since that will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
95 compatible = "ti,omap4-l3-noc", "simple-bus";
99 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
100 reg = <0x44000000 0x1000>,
103 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106 counter32k: counter@4a304000 {
107 compatible = "ti,omap-counter32k";
108 reg = <0x4a304000 0x20>;
109 ti,hwmods = "counter_32k";
112 omap4_pmx_core: pinmux@4a100040 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a100040 0x0196>;
115 #address-cells = <1>;
117 #interrupt-cells = <1>;
118 interrupt-controller;
119 pinctrl-single,register-width = <16>;
120 pinctrl-single,function-mask = <0x7fff>;
122 omap4_pmx_wkup: pinmux@4a31e040 {
123 compatible = "ti,omap4-padconf", "pinctrl-single";
124 reg = <0x4a31e040 0x0038>;
125 #address-cells = <1>;
127 #interrupt-cells = <1>;
128 interrupt-controller;
129 pinctrl-single,register-width = <16>;
130 pinctrl-single,function-mask = <0x7fff>;
133 sdma: dma-controller@4a056000 {
134 compatible = "ti,omap4430-sdma";
135 reg = <0x4a056000 0x1000>;
136 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
141 #dma-channels = <32>;
142 #dma-requests = <127>;
145 gpio1: gpio@4a310000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x4a310000 0x200>;
148 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
157 gpio2: gpio@48055000 {
158 compatible = "ti,omap4-gpio";
159 reg = <0x48055000 0x200>;
160 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
168 gpio3: gpio@48057000 {
169 compatible = "ti,omap4-gpio";
170 reg = <0x48057000 0x200>;
171 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
179 gpio4: gpio@48059000 {
180 compatible = "ti,omap4-gpio";
181 reg = <0x48059000 0x200>;
182 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
190 gpio5: gpio@4805b000 {
191 compatible = "ti,omap4-gpio";
192 reg = <0x4805b000 0x200>;
193 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
201 gpio6: gpio@4805d000 {
202 compatible = "ti,omap4-gpio";
203 reg = <0x4805d000 0x200>;
204 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
212 gpmc: gpmc@50000000 {
213 compatible = "ti,omap4430-gpmc";
214 reg = <0x50000000 0x1000>;
215 #address-cells = <2>;
217 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
219 gpmc,num-waitpins = <4>;
223 uart1: serial@4806a000 {
224 compatible = "ti,omap4-uart";
225 reg = <0x4806a000 0x100>;
226 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
228 clock-frequency = <48000000>;
231 uart2: serial@4806c000 {
232 compatible = "ti,omap4-uart";
233 reg = <0x4806c000 0x100>;
234 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
236 clock-frequency = <48000000>;
239 uart3: serial@48020000 {
240 compatible = "ti,omap4-uart";
241 reg = <0x48020000 0x100>;
242 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
244 clock-frequency = <48000000>;
247 uart4: serial@4806e000 {
248 compatible = "ti,omap4-uart";
249 reg = <0x4806e000 0x100>;
250 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
252 clock-frequency = <48000000>;
256 compatible = "ti,omap4-i2c";
257 reg = <0x48070000 0x100>;
258 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
259 #address-cells = <1>;
265 compatible = "ti,omap4-i2c";
266 reg = <0x48072000 0x100>;
267 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
274 compatible = "ti,omap4-i2c";
275 reg = <0x48060000 0x100>;
276 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
277 #address-cells = <1>;
283 compatible = "ti,omap4-i2c";
284 reg = <0x48350000 0x100>;
285 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
286 #address-cells = <1>;
291 mcspi1: spi@48098000 {
292 compatible = "ti,omap4-mcspi";
293 reg = <0x48098000 0x200>;
294 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
297 ti,hwmods = "mcspi1";
307 dma-names = "tx0", "rx0", "tx1", "rx1",
308 "tx2", "rx2", "tx3", "rx3";
311 mcspi2: spi@4809a000 {
312 compatible = "ti,omap4-mcspi";
313 reg = <0x4809a000 0x200>;
314 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
317 ti,hwmods = "mcspi2";
323 dma-names = "tx0", "rx0", "tx1", "rx1";
326 mcspi3: spi@480b8000 {
327 compatible = "ti,omap4-mcspi";
328 reg = <0x480b8000 0x200>;
329 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
332 ti,hwmods = "mcspi3";
334 dmas = <&sdma 15>, <&sdma 16>;
335 dma-names = "tx0", "rx0";
338 mcspi4: spi@480ba000 {
339 compatible = "ti,omap4-mcspi";
340 reg = <0x480ba000 0x200>;
341 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
344 ti,hwmods = "mcspi4";
346 dmas = <&sdma 70>, <&sdma 71>;
347 dma-names = "tx0", "rx0";
351 compatible = "ti,omap4-hsmmc";
352 reg = <0x4809c000 0x400>;
353 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
356 ti,needs-special-reset;
357 dmas = <&sdma 61>, <&sdma 62>;
358 dma-names = "tx", "rx";
362 compatible = "ti,omap4-hsmmc";
363 reg = <0x480b4000 0x400>;
364 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
366 ti,needs-special-reset;
367 dmas = <&sdma 47>, <&sdma 48>;
368 dma-names = "tx", "rx";
372 compatible = "ti,omap4-hsmmc";
373 reg = <0x480ad000 0x400>;
374 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
376 ti,needs-special-reset;
377 dmas = <&sdma 77>, <&sdma 78>;
378 dma-names = "tx", "rx";
382 compatible = "ti,omap4-hsmmc";
383 reg = <0x480d1000 0x400>;
384 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
386 ti,needs-special-reset;
387 dmas = <&sdma 57>, <&sdma 58>;
388 dma-names = "tx", "rx";
392 compatible = "ti,omap4-hsmmc";
393 reg = <0x480d5000 0x400>;
394 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
396 ti,needs-special-reset;
397 dmas = <&sdma 59>, <&sdma 60>;
398 dma-names = "tx", "rx";
402 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
403 reg = <0x4a314000 0x80>;
404 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "wd_timer2";
408 mcpdm: mcpdm@40132000 {
409 compatible = "ti,omap4-mcpdm";
410 reg = <0x40132000 0x7f>, /* MPU private access */
411 <0x49032000 0x7f>; /* L3 Interconnect */
412 reg-names = "mpu", "dma";
413 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
417 dma-names = "up_link", "dn_link";
420 dmic: dmic@4012e000 {
421 compatible = "ti,omap4-dmic";
422 reg = <0x4012e000 0x7f>, /* MPU private access */
423 <0x4902e000 0x7f>; /* L3 Interconnect */
424 reg-names = "mpu", "dma";
425 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
428 dma-names = "up_link";
431 mcbsp1: mcbsp@40122000 {
432 compatible = "ti,omap4-mcbsp";
433 reg = <0x40122000 0xff>, /* MPU private access */
434 <0x49022000 0xff>; /* L3 Interconnect */
435 reg-names = "mpu", "dma";
436 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
437 interrupt-names = "common";
438 ti,buffer-size = <128>;
439 ti,hwmods = "mcbsp1";
442 dma-names = "tx", "rx";
445 mcbsp2: mcbsp@40124000 {
446 compatible = "ti,omap4-mcbsp";
447 reg = <0x40124000 0xff>, /* MPU private access */
448 <0x49024000 0xff>; /* L3 Interconnect */
449 reg-names = "mpu", "dma";
450 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-names = "common";
452 ti,buffer-size = <128>;
453 ti,hwmods = "mcbsp2";
456 dma-names = "tx", "rx";
459 mcbsp3: mcbsp@40126000 {
460 compatible = "ti,omap4-mcbsp";
461 reg = <0x40126000 0xff>, /* MPU private access */
462 <0x49026000 0xff>; /* L3 Interconnect */
463 reg-names = "mpu", "dma";
464 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "common";
466 ti,buffer-size = <128>;
467 ti,hwmods = "mcbsp3";
470 dma-names = "tx", "rx";
473 mcbsp4: mcbsp@48096000 {
474 compatible = "ti,omap4-mcbsp";
475 reg = <0x48096000 0xff>; /* L4 Interconnect */
477 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
478 interrupt-names = "common";
479 ti,buffer-size = <128>;
480 ti,hwmods = "mcbsp4";
483 dma-names = "tx", "rx";
486 keypad: keypad@4a31c000 {
487 compatible = "ti,omap4-keypad";
488 reg = <0x4a31c000 0x80>;
489 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
494 emif1: emif@4c000000 {
495 compatible = "ti,emif-4d";
496 reg = <0x4c000000 0x100>;
497 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
500 hw-caps-read-idle-ctrl;
501 hw-caps-ll-interface;
505 emif2: emif@4d000000 {
506 compatible = "ti,emif-4d";
507 reg = <0x4d000000 0x100>;
508 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
511 hw-caps-read-idle-ctrl;
512 hw-caps-ll-interface;
517 compatible = "ti,omap-ocp2scp";
518 reg = <0x4a0ad000 0x1f>;
519 #address-cells = <1>;
522 ti,hwmods = "ocp2scp_usb_phy";
523 usb2_phy: usb2phy@4a0ad080 {
524 compatible = "ti,omap-usb2";
525 reg = <0x4a0ad080 0x58>;
526 ctrl-module = <&omap_control_usb2phy>;
531 timer1: timer@4a318000 {
532 compatible = "ti,omap3430-timer";
533 reg = <0x4a318000 0x80>;
534 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "timer1";
539 timer2: timer@48032000 {
540 compatible = "ti,omap3430-timer";
541 reg = <0x48032000 0x80>;
542 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
543 ti,hwmods = "timer2";
546 timer3: timer@48034000 {
547 compatible = "ti,omap4430-timer";
548 reg = <0x48034000 0x80>;
549 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "timer3";
553 timer4: timer@48036000 {
554 compatible = "ti,omap4430-timer";
555 reg = <0x48036000 0x80>;
556 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
557 ti,hwmods = "timer4";
560 timer5: timer@40138000 {
561 compatible = "ti,omap4430-timer";
562 reg = <0x40138000 0x80>,
564 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "timer5";
569 timer6: timer@4013a000 {
570 compatible = "ti,omap4430-timer";
571 reg = <0x4013a000 0x80>,
573 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
574 ti,hwmods = "timer6";
578 timer7: timer@4013c000 {
579 compatible = "ti,omap4430-timer";
580 reg = <0x4013c000 0x80>,
582 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
583 ti,hwmods = "timer7";
587 timer8: timer@4013e000 {
588 compatible = "ti,omap4430-timer";
589 reg = <0x4013e000 0x80>,
591 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
592 ti,hwmods = "timer8";
597 timer9: timer@4803e000 {
598 compatible = "ti,omap4430-timer";
599 reg = <0x4803e000 0x80>;
600 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
601 ti,hwmods = "timer9";
605 timer10: timer@48086000 {
606 compatible = "ti,omap3430-timer";
607 reg = <0x48086000 0x80>;
608 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
609 ti,hwmods = "timer10";
613 timer11: timer@48088000 {
614 compatible = "ti,omap4430-timer";
615 reg = <0x48088000 0x80>;
616 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
617 ti,hwmods = "timer11";
621 usbhstll: usbhstll@4a062000 {
622 compatible = "ti,usbhs-tll";
623 reg = <0x4a062000 0x1000>;
624 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
625 ti,hwmods = "usb_tll_hs";
628 usbhshost: usbhshost@4a064000 {
629 compatible = "ti,usbhs-host";
630 reg = <0x4a064000 0x800>;
631 ti,hwmods = "usb_host_hs";
632 #address-cells = <1>;
636 usbhsohci: ohci@4a064800 {
637 compatible = "ti,ohci-omap3", "usb-ohci";
638 reg = <0x4a064800 0x400>;
639 interrupt-parent = <&gic>;
640 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
643 usbhsehci: ehci@4a064c00 {
644 compatible = "ti,ehci-omap", "usb-ehci";
645 reg = <0x4a064c00 0x400>;
646 interrupt-parent = <&gic>;
647 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
651 omap_control_usb2phy: control-phy@4a002300 {
652 compatible = "ti,control-phy-usb2";
653 reg = <0x4a002300 0x4>;
657 omap_control_usbotg: control-phy@4a00233c {
658 compatible = "ti,control-phy-otghs";
659 reg = <0x4a00233c 0x4>;
660 reg-names = "otghs_control";
663 usb_otg_hs: usb_otg_hs@4a0ab000 {
664 compatible = "ti,omap4-musb";
665 reg = <0x4a0ab000 0x7ff>;
666 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
667 interrupt-names = "mc", "dma";
668 ti,hwmods = "usb_otg_hs";
669 usb-phy = <&usb2_phy>;
671 phy-names = "usb2-phy";
675 ctrl-module = <&omap_control_usbotg>;
679 compatible = "ti,omap4-aes";
681 reg = <0x4b501000 0xa0>;
682 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
683 dmas = <&sdma 111>, <&sdma 110>;
684 dma-names = "tx", "rx";
688 compatible = "ti,omap4-des";
690 reg = <0x480a5000 0xa0>;
691 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
692 dmas = <&sdma 117>, <&sdma 116>;
693 dma-names = "tx", "rx";