2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a15";
53 clocks = <&dpll_mpu_ck>;
56 clock-latency = <300000>; /* From omap-cpufreq driver */
59 cooling-min-level = <0>;
60 cooling-max-level = <2>;
61 #cooling-cells = <2>; /* min followed by max */
65 compatible = "arm,cortex-a15";
71 #include "omap4-cpu-thermal.dtsi"
72 #include "omap5-gpu-thermal.dtsi"
73 #include "omap5-core-thermal.dtsi"
77 compatible = "arm,armv7-timer";
78 /* PPI secure/nonsecure IRQ */
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
85 gic: interrupt-controller@48211000 {
86 compatible = "arm,cortex-a15-gic";
88 #interrupt-cells = <3>;
89 reg = <0x48211000 0x1000>,
96 * The soc node represents the soc top level view. It is uses for IPs
97 * that are not memory mapped in the MPU view or for the MPU itself.
100 compatible = "ti,omap-infra";
102 compatible = "ti,omap5-mpu";
108 * XXX: Use a flat representation of the OMAP3 interconnect.
109 * The real OMAP interconnect network is quite complex.
110 * Since that will not bring real advantage to represent that in DT for
111 * the moment, just use a fake OCP bus entry to represent the whole bus
115 compatible = "ti,omap4-l3-noc", "simple-bus";
116 #address-cells = <1>;
119 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
120 reg = <0x44000000 0x2000>,
123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
127 compatible = "ti,omap5-prm";
128 reg = <0x4ae06000 0x3000>;
131 #address-cells = <1>;
135 prm_clockdomains: clockdomains {
139 cm_core_aon: cm_core_aon@4a004000 {
140 compatible = "ti,omap5-cm-core-aon";
141 reg = <0x4a004000 0x2000>;
143 cm_core_aon_clocks: clocks {
144 #address-cells = <1>;
148 cm_core_aon_clockdomains: clockdomains {
152 scrm: scrm@4ae0a000 {
153 compatible = "ti,omap5-scrm";
154 reg = <0x4ae0a000 0x2000>;
156 scrm_clocks: clocks {
157 #address-cells = <1>;
161 scrm_clockdomains: clockdomains {
165 cm_core: cm_core@4a008000 {
166 compatible = "ti,omap5-cm-core";
167 reg = <0x4a008000 0x3000>;
169 cm_core_clocks: clocks {
170 #address-cells = <1>;
174 cm_core_clockdomains: clockdomains {
178 counter32k: counter@4ae04000 {
179 compatible = "ti,omap-counter32k";
180 reg = <0x4ae04000 0x40>;
181 ti,hwmods = "counter_32k";
184 omap5_pmx_core: pinmux@4a002840 {
185 compatible = "ti,omap4-padconf", "pinctrl-single";
186 reg = <0x4a002840 0x01b6>;
187 #address-cells = <1>;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
192 omap5_pmx_wkup: pinmux@4ae0c840 {
193 compatible = "ti,omap4-padconf", "pinctrl-single";
194 reg = <0x4ae0c840 0x0038>;
195 #address-cells = <1>;
197 pinctrl-single,register-width = <16>;
198 pinctrl-single,function-mask = <0x7fff>;
201 sdma: dma-controller@4a056000 {
202 compatible = "ti,omap4430-sdma";
203 reg = <0x4a056000 0x1000>;
204 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
209 #dma-channels = <32>;
210 #dma-requests = <127>;
213 gpio1: gpio@4ae10000 {
214 compatible = "ti,omap4-gpio";
215 reg = <0x4ae10000 0x200>;
216 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
225 gpio2: gpio@48055000 {
226 compatible = "ti,omap4-gpio";
227 reg = <0x48055000 0x200>;
228 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
236 gpio3: gpio@48057000 {
237 compatible = "ti,omap4-gpio";
238 reg = <0x48057000 0x200>;
239 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
247 gpio4: gpio@48059000 {
248 compatible = "ti,omap4-gpio";
249 reg = <0x48059000 0x200>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
258 gpio5: gpio@4805b000 {
259 compatible = "ti,omap4-gpio";
260 reg = <0x4805b000 0x200>;
261 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
269 gpio6: gpio@4805d000 {
270 compatible = "ti,omap4-gpio";
271 reg = <0x4805d000 0x200>;
272 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
280 gpio7: gpio@48051000 {
281 compatible = "ti,omap4-gpio";
282 reg = <0x48051000 0x200>;
283 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
291 gpio8: gpio@48053000 {
292 compatible = "ti,omap4-gpio";
293 reg = <0x48053000 0x200>;
294 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
302 gpmc: gpmc@50000000 {
303 compatible = "ti,omap4430-gpmc";
304 reg = <0x50000000 0x1000>;
305 #address-cells = <2>;
307 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
309 gpmc,num-waitpins = <4>;
311 clocks = <&l3_iclk_div>;
316 compatible = "ti,omap4-i2c";
317 reg = <0x48070000 0x100>;
318 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
325 compatible = "ti,omap4-i2c";
326 reg = <0x48072000 0x100>;
327 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
334 compatible = "ti,omap4-i2c";
335 reg = <0x48060000 0x100>;
336 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
337 #address-cells = <1>;
343 compatible = "ti,omap4-i2c";
344 reg = <0x4807a000 0x100>;
345 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
352 compatible = "ti,omap4-i2c";
353 reg = <0x4807c000 0x100>;
354 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
360 hwspinlock: spinlock@4a0f6000 {
361 compatible = "ti,omap4-hwspinlock";
362 reg = <0x4a0f6000 0x1000>;
363 ti,hwmods = "spinlock";
367 mcspi1: spi@48098000 {
368 compatible = "ti,omap4-mcspi";
369 reg = <0x48098000 0x200>;
370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
373 ti,hwmods = "mcspi1";
383 dma-names = "tx0", "rx0", "tx1", "rx1",
384 "tx2", "rx2", "tx3", "rx3";
387 mcspi2: spi@4809a000 {
388 compatible = "ti,omap4-mcspi";
389 reg = <0x4809a000 0x200>;
390 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
393 ti,hwmods = "mcspi2";
399 dma-names = "tx0", "rx0", "tx1", "rx1";
402 mcspi3: spi@480b8000 {
403 compatible = "ti,omap4-mcspi";
404 reg = <0x480b8000 0x200>;
405 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
408 ti,hwmods = "mcspi3";
410 dmas = <&sdma 15>, <&sdma 16>;
411 dma-names = "tx0", "rx0";
414 mcspi4: spi@480ba000 {
415 compatible = "ti,omap4-mcspi";
416 reg = <0x480ba000 0x200>;
417 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
420 ti,hwmods = "mcspi4";
422 dmas = <&sdma 70>, <&sdma 71>;
423 dma-names = "tx0", "rx0";
426 uart1: serial@4806a000 {
427 compatible = "ti,omap4-uart";
428 reg = <0x4806a000 0x100>;
429 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
431 clock-frequency = <48000000>;
434 uart2: serial@4806c000 {
435 compatible = "ti,omap4-uart";
436 reg = <0x4806c000 0x100>;
437 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
439 clock-frequency = <48000000>;
442 uart3: serial@48020000 {
443 compatible = "ti,omap4-uart";
444 reg = <0x48020000 0x100>;
445 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
447 clock-frequency = <48000000>;
450 uart4: serial@4806e000 {
451 compatible = "ti,omap4-uart";
452 reg = <0x4806e000 0x100>;
453 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
455 clock-frequency = <48000000>;
458 uart5: serial@48066000 {
459 compatible = "ti,omap4-uart";
460 reg = <0x48066000 0x100>;
461 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
463 clock-frequency = <48000000>;
466 uart6: serial@48068000 {
467 compatible = "ti,omap4-uart";
468 reg = <0x48068000 0x100>;
469 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
471 clock-frequency = <48000000>;
475 compatible = "ti,omap4-hsmmc";
476 reg = <0x4809c000 0x400>;
477 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
480 ti,needs-special-reset;
481 dmas = <&sdma 61>, <&sdma 62>;
482 dma-names = "tx", "rx";
486 compatible = "ti,omap4-hsmmc";
487 reg = <0x480b4000 0x400>;
488 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
490 ti,needs-special-reset;
491 dmas = <&sdma 47>, <&sdma 48>;
492 dma-names = "tx", "rx";
496 compatible = "ti,omap4-hsmmc";
497 reg = <0x480ad000 0x400>;
498 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
500 ti,needs-special-reset;
501 dmas = <&sdma 77>, <&sdma 78>;
502 dma-names = "tx", "rx";
506 compatible = "ti,omap4-hsmmc";
507 reg = <0x480d1000 0x400>;
508 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
510 ti,needs-special-reset;
511 dmas = <&sdma 57>, <&sdma 58>;
512 dma-names = "tx", "rx";
516 compatible = "ti,omap4-hsmmc";
517 reg = <0x480d5000 0x400>;
518 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
520 ti,needs-special-reset;
521 dmas = <&sdma 59>, <&sdma 60>;
522 dma-names = "tx", "rx";
525 mmu_dsp: mmu@4a066000 {
526 compatible = "ti,omap4-iommu";
527 reg = <0x4a066000 0x100>;
528 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
529 ti,hwmods = "mmu_dsp";
532 mmu_ipu: mmu@55082000 {
533 compatible = "ti,omap4-iommu";
534 reg = <0x55082000 0x100>;
535 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
536 ti,hwmods = "mmu_ipu";
537 ti,iommu-bus-err-back;
540 keypad: keypad@4ae1c000 {
541 compatible = "ti,omap4-keypad";
542 reg = <0x4ae1c000 0x400>;
546 mcpdm: mcpdm@40132000 {
547 compatible = "ti,omap4-mcpdm";
548 reg = <0x40132000 0x7f>, /* MPU private access */
549 <0x49032000 0x7f>; /* L3 Interconnect */
550 reg-names = "mpu", "dma";
551 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
555 dma-names = "up_link", "dn_link";
559 dmic: dmic@4012e000 {
560 compatible = "ti,omap4-dmic";
561 reg = <0x4012e000 0x7f>, /* MPU private access */
562 <0x4902e000 0x7f>; /* L3 Interconnect */
563 reg-names = "mpu", "dma";
564 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
567 dma-names = "up_link";
571 mcbsp1: mcbsp@40122000 {
572 compatible = "ti,omap4-mcbsp";
573 reg = <0x40122000 0xff>, /* MPU private access */
574 <0x49022000 0xff>; /* L3 Interconnect */
575 reg-names = "mpu", "dma";
576 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "common";
578 ti,buffer-size = <128>;
579 ti,hwmods = "mcbsp1";
582 dma-names = "tx", "rx";
586 mcbsp2: mcbsp@40124000 {
587 compatible = "ti,omap4-mcbsp";
588 reg = <0x40124000 0xff>, /* MPU private access */
589 <0x49024000 0xff>; /* L3 Interconnect */
590 reg-names = "mpu", "dma";
591 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
592 interrupt-names = "common";
593 ti,buffer-size = <128>;
594 ti,hwmods = "mcbsp2";
597 dma-names = "tx", "rx";
601 mcbsp3: mcbsp@40126000 {
602 compatible = "ti,omap4-mcbsp";
603 reg = <0x40126000 0xff>, /* MPU private access */
604 <0x49026000 0xff>; /* L3 Interconnect */
605 reg-names = "mpu", "dma";
606 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
607 interrupt-names = "common";
608 ti,buffer-size = <128>;
609 ti,hwmods = "mcbsp3";
612 dma-names = "tx", "rx";
616 timer1: timer@4ae18000 {
617 compatible = "ti,omap5430-timer";
618 reg = <0x4ae18000 0x80>;
619 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
620 ti,hwmods = "timer1";
624 timer2: timer@48032000 {
625 compatible = "ti,omap5430-timer";
626 reg = <0x48032000 0x80>;
627 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
628 ti,hwmods = "timer2";
631 timer3: timer@48034000 {
632 compatible = "ti,omap5430-timer";
633 reg = <0x48034000 0x80>;
634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
635 ti,hwmods = "timer3";
638 timer4: timer@48036000 {
639 compatible = "ti,omap5430-timer";
640 reg = <0x48036000 0x80>;
641 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
642 ti,hwmods = "timer4";
645 timer5: timer@40138000 {
646 compatible = "ti,omap5430-timer";
647 reg = <0x40138000 0x80>,
649 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "timer5";
655 timer6: timer@4013a000 {
656 compatible = "ti,omap5430-timer";
657 reg = <0x4013a000 0x80>,
659 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
660 ti,hwmods = "timer6";
665 timer7: timer@4013c000 {
666 compatible = "ti,omap5430-timer";
667 reg = <0x4013c000 0x80>,
669 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
670 ti,hwmods = "timer7";
674 timer8: timer@4013e000 {
675 compatible = "ti,omap5430-timer";
676 reg = <0x4013e000 0x80>,
678 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
679 ti,hwmods = "timer8";
684 timer9: timer@4803e000 {
685 compatible = "ti,omap5430-timer";
686 reg = <0x4803e000 0x80>;
687 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
688 ti,hwmods = "timer9";
692 timer10: timer@48086000 {
693 compatible = "ti,omap5430-timer";
694 reg = <0x48086000 0x80>;
695 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "timer10";
700 timer11: timer@48088000 {
701 compatible = "ti,omap5430-timer";
702 reg = <0x48088000 0x80>;
703 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
704 ti,hwmods = "timer11";
709 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
710 reg = <0x4ae14000 0x80>;
711 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
712 ti,hwmods = "wd_timer2";
716 compatible = "ti,omap5-dmm";
717 reg = <0x4e000000 0x800>;
718 interrupts = <0 113 0x4>;
722 emif1: emif@4c000000 {
723 compatible = "ti,emif-4d5";
726 phy-type = <2>; /* DDR PHY type: Intelli PHY */
727 reg = <0x4c000000 0x400>;
728 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
729 hw-caps-read-idle-ctrl;
730 hw-caps-ll-interface;
734 emif2: emif@4d000000 {
735 compatible = "ti,emif-4d5";
738 phy-type = <2>; /* DDR PHY type: Intelli PHY */
739 reg = <0x4d000000 0x400>;
740 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
741 hw-caps-read-idle-ctrl;
742 hw-caps-ll-interface;
746 omap_control_usb2phy: control-phy@4a002300 {
747 compatible = "ti,control-phy-usb2";
748 reg = <0x4a002300 0x4>;
752 omap_control_usb3phy: control-phy@4a002370 {
753 compatible = "ti,control-phy-pipe3";
754 reg = <0x4a002370 0x4>;
758 usb3: omap_dwc3@4a020000 {
759 compatible = "ti,dwc3";
760 ti,hwmods = "usb_otg_ss";
761 reg = <0x4a020000 0x10000>;
762 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
763 #address-cells = <1>;
768 compatible = "snps,dwc3";
769 reg = <0x4a030000 0x10000>;
770 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
771 phys = <&usb2_phy>, <&usb3_phy>;
772 phy-names = "usb2-phy", "usb3-phy";
773 dr_mode = "peripheral";
779 compatible = "ti,omap-ocp2scp";
780 #address-cells = <1>;
782 reg = <0x4a080000 0x20>;
784 ti,hwmods = "ocp2scp1";
785 usb2_phy: usb2phy@4a084000 {
786 compatible = "ti,omap-usb2";
787 reg = <0x4a084000 0x7c>;
788 ctrl-module = <&omap_control_usb2phy>;
792 usb3_phy: usb3phy@4a084400 {
793 compatible = "ti,omap-usb3";
794 reg = <0x4a084400 0x80>,
797 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
798 ctrl-module = <&omap_control_usb3phy>;
803 usbhstll: usbhstll@4a062000 {
804 compatible = "ti,usbhs-tll";
805 reg = <0x4a062000 0x1000>;
806 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
807 ti,hwmods = "usb_tll_hs";
810 usbhshost: usbhshost@4a064000 {
811 compatible = "ti,usbhs-host";
812 reg = <0x4a064000 0x800>;
813 ti,hwmods = "usb_host_hs";
814 #address-cells = <1>;
818 usbhsohci: ohci@4a064800 {
819 compatible = "ti,ohci-omap3";
820 reg = <0x4a064800 0x400>;
821 interrupt-parent = <&gic>;
822 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
825 usbhsehci: ehci@4a064c00 {
826 compatible = "ti,ehci-omap";
827 reg = <0x4a064c00 0x400>;
828 interrupt-parent = <&gic>;
829 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
833 bandgap: bandgap@4a0021e0 {
834 reg = <0x4a0021e0 0xc
838 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
839 compatible = "ti,omap5430-bandgap";
841 #thermal-sensor-cells = <1>;
846 /include/ "omap54xx-clocks.dtsi"