2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a15";
55 compatible = "arm,cortex-a15";
61 compatible = "arm,armv7-timer";
62 /* PPI secure/nonsecure IRQ */
63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
69 gic: interrupt-controller@48211000 {
70 compatible = "arm,cortex-a15-gic";
72 #interrupt-cells = <3>;
73 reg = <0x48211000 0x1000>,
80 * The soc node represents the soc top level view. It is uses for IPs
81 * that are not memory mapped in the MPU view or for the MPU itself.
84 compatible = "ti,omap-infra";
86 compatible = "ti,omap5-mpu";
92 * XXX: Use a flat representation of the OMAP3 interconnect.
93 * The real OMAP interconnect network is quite complex.
94 * Since that will not bring real advantage to represent that in DT for
95 * the moment, just use a fake OCP bus entry to represent the whole bus
99 compatible = "ti,omap4-l3-noc", "simple-bus";
100 #address-cells = <1>;
103 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
104 reg = <0x44000000 0x2000>,
107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
110 counter32k: counter@4ae04000 {
111 compatible = "ti,omap-counter32k";
112 reg = <0x4ae04000 0x40>;
113 ti,hwmods = "counter_32k";
116 omap5_pmx_core: pinmux@4a002840 {
117 compatible = "ti,omap4-padconf", "pinctrl-single";
118 reg = <0x4a002840 0x01b6>;
119 #address-cells = <1>;
121 pinctrl-single,register-width = <16>;
122 pinctrl-single,function-mask = <0x7fff>;
124 omap5_pmx_wkup: pinmux@4ae0c840 {
125 compatible = "ti,omap4-padconf", "pinctrl-single";
126 reg = <0x4ae0c840 0x0038>;
127 #address-cells = <1>;
129 pinctrl-single,register-width = <16>;
130 pinctrl-single,function-mask = <0x7fff>;
133 sdma: dma-controller@4a056000 {
134 compatible = "ti,omap4430-sdma";
135 reg = <0x4a056000 0x1000>;
136 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
141 #dma-channels = <32>;
142 #dma-requests = <127>;
145 gpio1: gpio@4ae10000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x4ae10000 0x200>;
148 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
157 gpio2: gpio@48055000 {
158 compatible = "ti,omap4-gpio";
159 reg = <0x48055000 0x200>;
160 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
168 gpio3: gpio@48057000 {
169 compatible = "ti,omap4-gpio";
170 reg = <0x48057000 0x200>;
171 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
179 gpio4: gpio@48059000 {
180 compatible = "ti,omap4-gpio";
181 reg = <0x48059000 0x200>;
182 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
190 gpio5: gpio@4805b000 {
191 compatible = "ti,omap4-gpio";
192 reg = <0x4805b000 0x200>;
193 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
201 gpio6: gpio@4805d000 {
202 compatible = "ti,omap4-gpio";
203 reg = <0x4805d000 0x200>;
204 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
212 gpio7: gpio@48051000 {
213 compatible = "ti,omap4-gpio";
214 reg = <0x48051000 0x200>;
215 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
223 gpio8: gpio@48053000 {
224 compatible = "ti,omap4-gpio";
225 reg = <0x48053000 0x200>;
226 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
234 gpmc: gpmc@50000000 {
235 compatible = "ti,omap4430-gpmc";
236 reg = <0x50000000 0x1000>;
237 #address-cells = <2>;
239 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
241 gpmc,num-waitpins = <4>;
246 compatible = "ti,omap4-i2c";
247 reg = <0x48070000 0x100>;
248 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>;
255 compatible = "ti,omap4-i2c";
256 reg = <0x48072000 0x100>;
257 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
258 #address-cells = <1>;
264 compatible = "ti,omap4-i2c";
265 reg = <0x48060000 0x100>;
266 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
267 #address-cells = <1>;
273 compatible = "ti,omap4-i2c";
274 reg = <0x4807a000 0x100>;
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
282 compatible = "ti,omap4-i2c";
283 reg = <0x4807c000 0x100>;
284 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
285 #address-cells = <1>;
290 hwspinlock: spinlock@4a0f6000 {
291 compatible = "ti,omap4-hwspinlock";
292 reg = <0x4a0f6000 0x1000>;
293 ti,hwmods = "spinlock";
296 mcspi1: spi@48098000 {
297 compatible = "ti,omap4-mcspi";
298 reg = <0x48098000 0x200>;
299 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
302 ti,hwmods = "mcspi1";
312 dma-names = "tx0", "rx0", "tx1", "rx1",
313 "tx2", "rx2", "tx3", "rx3";
316 mcspi2: spi@4809a000 {
317 compatible = "ti,omap4-mcspi";
318 reg = <0x4809a000 0x200>;
319 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 ti,hwmods = "mcspi2";
328 dma-names = "tx0", "rx0", "tx1", "rx1";
331 mcspi3: spi@480b8000 {
332 compatible = "ti,omap4-mcspi";
333 reg = <0x480b8000 0x200>;
334 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
337 ti,hwmods = "mcspi3";
339 dmas = <&sdma 15>, <&sdma 16>;
340 dma-names = "tx0", "rx0";
343 mcspi4: spi@480ba000 {
344 compatible = "ti,omap4-mcspi";
345 reg = <0x480ba000 0x200>;
346 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
349 ti,hwmods = "mcspi4";
351 dmas = <&sdma 70>, <&sdma 71>;
352 dma-names = "tx0", "rx0";
355 uart1: serial@4806a000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4806a000 0x100>;
358 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
360 clock-frequency = <48000000>;
363 uart2: serial@4806c000 {
364 compatible = "ti,omap4-uart";
365 reg = <0x4806c000 0x100>;
366 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 clock-frequency = <48000000>;
371 uart3: serial@48020000 {
372 compatible = "ti,omap4-uart";
373 reg = <0x48020000 0x100>;
374 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
376 clock-frequency = <48000000>;
379 uart4: serial@4806e000 {
380 compatible = "ti,omap4-uart";
381 reg = <0x4806e000 0x100>;
382 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
384 clock-frequency = <48000000>;
387 uart5: serial@48066000 {
388 compatible = "ti,omap4-uart";
389 reg = <0x48066000 0x100>;
390 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
392 clock-frequency = <48000000>;
395 uart6: serial@48068000 {
396 compatible = "ti,omap4-uart";
397 reg = <0x48068000 0x100>;
398 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
400 clock-frequency = <48000000>;
404 compatible = "ti,omap4-hsmmc";
405 reg = <0x4809c000 0x400>;
406 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
409 ti,needs-special-reset;
410 dmas = <&sdma 61>, <&sdma 62>;
411 dma-names = "tx", "rx";
415 compatible = "ti,omap4-hsmmc";
416 reg = <0x480b4000 0x400>;
417 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
419 ti,needs-special-reset;
420 dmas = <&sdma 47>, <&sdma 48>;
421 dma-names = "tx", "rx";
425 compatible = "ti,omap4-hsmmc";
426 reg = <0x480ad000 0x400>;
427 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
429 ti,needs-special-reset;
430 dmas = <&sdma 77>, <&sdma 78>;
431 dma-names = "tx", "rx";
435 compatible = "ti,omap4-hsmmc";
436 reg = <0x480d1000 0x400>;
437 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
439 ti,needs-special-reset;
440 dmas = <&sdma 57>, <&sdma 58>;
441 dma-names = "tx", "rx";
445 compatible = "ti,omap4-hsmmc";
446 reg = <0x480d5000 0x400>;
447 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
449 ti,needs-special-reset;
450 dmas = <&sdma 59>, <&sdma 60>;
451 dma-names = "tx", "rx";
454 keypad: keypad@4ae1c000 {
455 compatible = "ti,omap4-keypad";
456 reg = <0x4ae1c000 0x400>;
460 mcpdm: mcpdm@40132000 {
461 compatible = "ti,omap4-mcpdm";
462 reg = <0x40132000 0x7f>, /* MPU private access */
463 <0x49032000 0x7f>; /* L3 Interconnect */
464 reg-names = "mpu", "dma";
465 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
469 dma-names = "up_link", "dn_link";
472 dmic: dmic@4012e000 {
473 compatible = "ti,omap4-dmic";
474 reg = <0x4012e000 0x7f>, /* MPU private access */
475 <0x4902e000 0x7f>; /* L3 Interconnect */
476 reg-names = "mpu", "dma";
477 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
480 dma-names = "up_link";
483 mcbsp1: mcbsp@40122000 {
484 compatible = "ti,omap4-mcbsp";
485 reg = <0x40122000 0xff>, /* MPU private access */
486 <0x49022000 0xff>; /* L3 Interconnect */
487 reg-names = "mpu", "dma";
488 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
489 interrupt-names = "common";
490 ti,buffer-size = <128>;
491 ti,hwmods = "mcbsp1";
494 dma-names = "tx", "rx";
497 mcbsp2: mcbsp@40124000 {
498 compatible = "ti,omap4-mcbsp";
499 reg = <0x40124000 0xff>, /* MPU private access */
500 <0x49024000 0xff>; /* L3 Interconnect */
501 reg-names = "mpu", "dma";
502 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "common";
504 ti,buffer-size = <128>;
505 ti,hwmods = "mcbsp2";
508 dma-names = "tx", "rx";
511 mcbsp3: mcbsp@40126000 {
512 compatible = "ti,omap4-mcbsp";
513 reg = <0x40126000 0xff>, /* MPU private access */
514 <0x49026000 0xff>; /* L3 Interconnect */
515 reg-names = "mpu", "dma";
516 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
517 interrupt-names = "common";
518 ti,buffer-size = <128>;
519 ti,hwmods = "mcbsp3";
522 dma-names = "tx", "rx";
525 timer1: timer@4ae18000 {
526 compatible = "ti,omap5430-timer";
527 reg = <0x4ae18000 0x80>;
528 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
529 ti,hwmods = "timer1";
533 timer2: timer@48032000 {
534 compatible = "ti,omap5430-timer";
535 reg = <0x48032000 0x80>;
536 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
537 ti,hwmods = "timer2";
540 timer3: timer@48034000 {
541 compatible = "ti,omap5430-timer";
542 reg = <0x48034000 0x80>;
543 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
544 ti,hwmods = "timer3";
547 timer4: timer@48036000 {
548 compatible = "ti,omap5430-timer";
549 reg = <0x48036000 0x80>;
550 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "timer4";
554 timer5: timer@40138000 {
555 compatible = "ti,omap5430-timer";
556 reg = <0x40138000 0x80>,
558 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
559 ti,hwmods = "timer5";
564 timer6: timer@4013a000 {
565 compatible = "ti,omap5430-timer";
566 reg = <0x4013a000 0x80>,
568 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
569 ti,hwmods = "timer6";
574 timer7: timer@4013c000 {
575 compatible = "ti,omap5430-timer";
576 reg = <0x4013c000 0x80>,
578 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
579 ti,hwmods = "timer7";
583 timer8: timer@4013e000 {
584 compatible = "ti,omap5430-timer";
585 reg = <0x4013e000 0x80>,
587 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "timer8";
593 timer9: timer@4803e000 {
594 compatible = "ti,omap5430-timer";
595 reg = <0x4803e000 0x80>;
596 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
597 ti,hwmods = "timer9";
601 timer10: timer@48086000 {
602 compatible = "ti,omap5430-timer";
603 reg = <0x48086000 0x80>;
604 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "timer10";
609 timer11: timer@48088000 {
610 compatible = "ti,omap5430-timer";
611 reg = <0x48088000 0x80>;
612 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
613 ti,hwmods = "timer11";
618 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
619 reg = <0x4ae14000 0x80>;
620 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
621 ti,hwmods = "wd_timer2";
624 emif1: emif@4c000000 {
625 compatible = "ti,emif-4d5";
628 phy-type = <2>; /* DDR PHY type: Intelli PHY */
629 reg = <0x4c000000 0x400>;
630 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
631 hw-caps-read-idle-ctrl;
632 hw-caps-ll-interface;
636 emif2: emif@4d000000 {
637 compatible = "ti,emif-4d5";
640 phy-type = <2>; /* DDR PHY type: Intelli PHY */
641 reg = <0x4d000000 0x400>;
642 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
643 hw-caps-read-idle-ctrl;
644 hw-caps-ll-interface;
648 omap_control_usb2phy: control-phy@4a002300 {
649 compatible = "ti,control-phy-usb2";
650 reg = <0x4a002300 0x4>;
654 omap_control_usb3phy: control-phy@4a002370 {
655 compatible = "ti,control-phy-pipe3";
656 reg = <0x4a002370 0x4>;
660 usb3: omap_dwc3@4a020000 {
661 compatible = "ti,dwc3";
662 ti,hwmods = "usb_otg_ss";
663 reg = <0x4a020000 0x10000>;
664 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
670 compatible = "snps,dwc3";
671 reg = <0x4a030000 0x10000>;
672 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
673 usb-phy = <&usb2_phy>, <&usb3_phy>;
674 dr_mode = "peripheral";
680 compatible = "ti,omap-ocp2scp";
681 #address-cells = <1>;
683 reg = <0x4a080000 0x20>;
685 ti,hwmods = "ocp2scp1";
686 usb2_phy: usb2phy@4a084000 {
687 compatible = "ti,omap-usb2";
688 reg = <0x4a084000 0x7c>;
689 ctrl-module = <&omap_control_usb2phy>;
692 usb3_phy: usb3phy@4a084400 {
693 compatible = "ti,omap-usb3";
694 reg = <0x4a084400 0x80>,
697 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
698 ctrl-module = <&omap_control_usb3phy>;
702 usbhstll: usbhstll@4a062000 {
703 compatible = "ti,usbhs-tll";
704 reg = <0x4a062000 0x1000>;
705 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
706 ti,hwmods = "usb_tll_hs";
709 usbhshost: usbhshost@4a064000 {
710 compatible = "ti,usbhs-host";
711 reg = <0x4a064000 0x800>;
712 ti,hwmods = "usb_host_hs";
713 #address-cells = <1>;
717 usbhsohci: ohci@4a064800 {
718 compatible = "ti,ohci-omap3", "usb-ohci";
719 reg = <0x4a064800 0x400>;
720 interrupt-parent = <&gic>;
721 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
724 usbhsehci: ehci@4a064c00 {
725 compatible = "ti,ehci-omap", "usb-ehci";
726 reg = <0x4a064c00 0x400>;
727 interrupt-parent = <&gic>;
728 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
733 reg = <0x4a0021e0 0xc
737 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
738 compatible = "ti,omap5430-bandgap";