2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a15";
53 clocks = <&dpll_mpu_ck>;
56 clock-latency = <300000>; /* From omap-cpufreq driver */
59 cooling-min-level = <0>;
60 cooling-max-level = <2>;
61 #cooling-cells = <2>; /* min followed by max */
65 compatible = "arm,cortex-a15";
71 #include "omap4-cpu-thermal.dtsi"
72 #include "omap5-gpu-thermal.dtsi"
73 #include "omap5-core-thermal.dtsi"
77 compatible = "arm,armv7-timer";
78 /* PPI secure/nonsecure IRQ */
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
85 gic: interrupt-controller@48211000 {
86 compatible = "arm,cortex-a15-gic";
88 #interrupt-cells = <3>;
89 reg = <0x48211000 0x1000>,
96 * The soc node represents the soc top level view. It is uses for IPs
97 * that are not memory mapped in the MPU view or for the MPU itself.
100 compatible = "ti,omap-infra";
102 compatible = "ti,omap5-mpu";
108 * XXX: Use a flat representation of the OMAP3 interconnect.
109 * The real OMAP interconnect network is quite complex.
110 * Since that will not bring real advantage to represent that in DT for
111 * the moment, just use a fake OCP bus entry to represent the whole bus
115 compatible = "ti,omap4-l3-noc", "simple-bus";
116 #address-cells = <1>;
119 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
120 reg = <0x44000000 0x2000>,
123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
127 compatible = "ti,omap5-prm";
128 reg = <0x4ae06000 0x3000>;
131 #address-cells = <1>;
135 prm_clockdomains: clockdomains {
139 cm_core_aon: cm_core_aon@4a004000 {
140 compatible = "ti,omap5-cm-core-aon";
141 reg = <0x4a004000 0x2000>;
143 cm_core_aon_clocks: clocks {
144 #address-cells = <1>;
148 cm_core_aon_clockdomains: clockdomains {
152 scrm: scrm@4ae0a000 {
153 compatible = "ti,omap5-scrm";
154 reg = <0x4ae0a000 0x2000>;
156 scrm_clocks: clocks {
157 #address-cells = <1>;
161 scrm_clockdomains: clockdomains {
165 cm_core: cm_core@4a008000 {
166 compatible = "ti,omap5-cm-core";
167 reg = <0x4a008000 0x3000>;
169 cm_core_clocks: clocks {
170 #address-cells = <1>;
174 cm_core_clockdomains: clockdomains {
178 counter32k: counter@4ae04000 {
179 compatible = "ti,omap-counter32k";
180 reg = <0x4ae04000 0x40>;
181 ti,hwmods = "counter_32k";
184 omap5_pmx_core: pinmux@4a002840 {
185 compatible = "ti,omap4-padconf", "pinctrl-single";
186 reg = <0x4a002840 0x01b6>;
187 #address-cells = <1>;
189 pinctrl-single,register-width = <16>;
190 pinctrl-single,function-mask = <0x7fff>;
192 omap5_pmx_wkup: pinmux@4ae0c840 {
193 compatible = "ti,omap4-padconf", "pinctrl-single";
194 reg = <0x4ae0c840 0x0038>;
195 #address-cells = <1>;
197 pinctrl-single,register-width = <16>;
198 pinctrl-single,function-mask = <0x7fff>;
201 sdma: dma-controller@4a056000 {
202 compatible = "ti,omap4430-sdma";
203 reg = <0x4a056000 0x1000>;
204 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
209 #dma-channels = <32>;
210 #dma-requests = <127>;
213 gpio1: gpio@4ae10000 {
214 compatible = "ti,omap4-gpio";
215 reg = <0x4ae10000 0x200>;
216 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
225 gpio2: gpio@48055000 {
226 compatible = "ti,omap4-gpio";
227 reg = <0x48055000 0x200>;
228 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-controller;
233 #interrupt-cells = <2>;
236 gpio3: gpio@48057000 {
237 compatible = "ti,omap4-gpio";
238 reg = <0x48057000 0x200>;
239 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
247 gpio4: gpio@48059000 {
248 compatible = "ti,omap4-gpio";
249 reg = <0x48059000 0x200>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
258 gpio5: gpio@4805b000 {
259 compatible = "ti,omap4-gpio";
260 reg = <0x4805b000 0x200>;
261 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
269 gpio6: gpio@4805d000 {
270 compatible = "ti,omap4-gpio";
271 reg = <0x4805d000 0x200>;
272 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
280 gpio7: gpio@48051000 {
281 compatible = "ti,omap4-gpio";
282 reg = <0x48051000 0x200>;
283 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
291 gpio8: gpio@48053000 {
292 compatible = "ti,omap4-gpio";
293 reg = <0x48053000 0x200>;
294 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
302 gpmc: gpmc@50000000 {
303 compatible = "ti,omap4430-gpmc";
304 reg = <0x50000000 0x1000>;
305 #address-cells = <2>;
307 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
309 gpmc,num-waitpins = <4>;
314 compatible = "ti,omap4-i2c";
315 reg = <0x48070000 0x100>;
316 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
323 compatible = "ti,omap4-i2c";
324 reg = <0x48072000 0x100>;
325 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
332 compatible = "ti,omap4-i2c";
333 reg = <0x48060000 0x100>;
334 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
341 compatible = "ti,omap4-i2c";
342 reg = <0x4807a000 0x100>;
343 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
350 compatible = "ti,omap4-i2c";
351 reg = <0x4807c000 0x100>;
352 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
358 hwspinlock: spinlock@4a0f6000 {
359 compatible = "ti,omap4-hwspinlock";
360 reg = <0x4a0f6000 0x1000>;
361 ti,hwmods = "spinlock";
365 mcspi1: spi@48098000 {
366 compatible = "ti,omap4-mcspi";
367 reg = <0x48098000 0x200>;
368 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
371 ti,hwmods = "mcspi1";
381 dma-names = "tx0", "rx0", "tx1", "rx1",
382 "tx2", "rx2", "tx3", "rx3";
385 mcspi2: spi@4809a000 {
386 compatible = "ti,omap4-mcspi";
387 reg = <0x4809a000 0x200>;
388 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
391 ti,hwmods = "mcspi2";
397 dma-names = "tx0", "rx0", "tx1", "rx1";
400 mcspi3: spi@480b8000 {
401 compatible = "ti,omap4-mcspi";
402 reg = <0x480b8000 0x200>;
403 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 ti,hwmods = "mcspi3";
408 dmas = <&sdma 15>, <&sdma 16>;
409 dma-names = "tx0", "rx0";
412 mcspi4: spi@480ba000 {
413 compatible = "ti,omap4-mcspi";
414 reg = <0x480ba000 0x200>;
415 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
418 ti,hwmods = "mcspi4";
420 dmas = <&sdma 70>, <&sdma 71>;
421 dma-names = "tx0", "rx0";
424 uart1: serial@4806a000 {
425 compatible = "ti,omap4-uart";
426 reg = <0x4806a000 0x100>;
427 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
429 clock-frequency = <48000000>;
432 uart2: serial@4806c000 {
433 compatible = "ti,omap4-uart";
434 reg = <0x4806c000 0x100>;
435 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
437 clock-frequency = <48000000>;
440 uart3: serial@48020000 {
441 compatible = "ti,omap4-uart";
442 reg = <0x48020000 0x100>;
443 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
445 clock-frequency = <48000000>;
448 uart4: serial@4806e000 {
449 compatible = "ti,omap4-uart";
450 reg = <0x4806e000 0x100>;
451 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <48000000>;
456 uart5: serial@48066000 {
457 compatible = "ti,omap4-uart";
458 reg = <0x48066000 0x100>;
459 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
461 clock-frequency = <48000000>;
464 uart6: serial@48068000 {
465 compatible = "ti,omap4-uart";
466 reg = <0x48068000 0x100>;
467 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
469 clock-frequency = <48000000>;
473 compatible = "ti,omap4-hsmmc";
474 reg = <0x4809c000 0x400>;
475 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
478 ti,needs-special-reset;
479 dmas = <&sdma 61>, <&sdma 62>;
480 dma-names = "tx", "rx";
484 compatible = "ti,omap4-hsmmc";
485 reg = <0x480b4000 0x400>;
486 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
488 ti,needs-special-reset;
489 dmas = <&sdma 47>, <&sdma 48>;
490 dma-names = "tx", "rx";
494 compatible = "ti,omap4-hsmmc";
495 reg = <0x480ad000 0x400>;
496 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
498 ti,needs-special-reset;
499 dmas = <&sdma 77>, <&sdma 78>;
500 dma-names = "tx", "rx";
504 compatible = "ti,omap4-hsmmc";
505 reg = <0x480d1000 0x400>;
506 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
508 ti,needs-special-reset;
509 dmas = <&sdma 57>, <&sdma 58>;
510 dma-names = "tx", "rx";
514 compatible = "ti,omap4-hsmmc";
515 reg = <0x480d5000 0x400>;
516 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
518 ti,needs-special-reset;
519 dmas = <&sdma 59>, <&sdma 60>;
520 dma-names = "tx", "rx";
523 keypad: keypad@4ae1c000 {
524 compatible = "ti,omap4-keypad";
525 reg = <0x4ae1c000 0x400>;
529 mcpdm: mcpdm@40132000 {
530 compatible = "ti,omap4-mcpdm";
531 reg = <0x40132000 0x7f>, /* MPU private access */
532 <0x49032000 0x7f>; /* L3 Interconnect */
533 reg-names = "mpu", "dma";
534 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
538 dma-names = "up_link", "dn_link";
542 dmic: dmic@4012e000 {
543 compatible = "ti,omap4-dmic";
544 reg = <0x4012e000 0x7f>, /* MPU private access */
545 <0x4902e000 0x7f>; /* L3 Interconnect */
546 reg-names = "mpu", "dma";
547 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
550 dma-names = "up_link";
554 mcbsp1: mcbsp@40122000 {
555 compatible = "ti,omap4-mcbsp";
556 reg = <0x40122000 0xff>, /* MPU private access */
557 <0x49022000 0xff>; /* L3 Interconnect */
558 reg-names = "mpu", "dma";
559 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-names = "common";
561 ti,buffer-size = <128>;
562 ti,hwmods = "mcbsp1";
565 dma-names = "tx", "rx";
569 mcbsp2: mcbsp@40124000 {
570 compatible = "ti,omap4-mcbsp";
571 reg = <0x40124000 0xff>, /* MPU private access */
572 <0x49024000 0xff>; /* L3 Interconnect */
573 reg-names = "mpu", "dma";
574 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "common";
576 ti,buffer-size = <128>;
577 ti,hwmods = "mcbsp2";
580 dma-names = "tx", "rx";
584 mcbsp3: mcbsp@40126000 {
585 compatible = "ti,omap4-mcbsp";
586 reg = <0x40126000 0xff>, /* MPU private access */
587 <0x49026000 0xff>; /* L3 Interconnect */
588 reg-names = "mpu", "dma";
589 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
590 interrupt-names = "common";
591 ti,buffer-size = <128>;
592 ti,hwmods = "mcbsp3";
595 dma-names = "tx", "rx";
599 timer1: timer@4ae18000 {
600 compatible = "ti,omap5430-timer";
601 reg = <0x4ae18000 0x80>;
602 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
603 ti,hwmods = "timer1";
607 timer2: timer@48032000 {
608 compatible = "ti,omap5430-timer";
609 reg = <0x48032000 0x80>;
610 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
611 ti,hwmods = "timer2";
614 timer3: timer@48034000 {
615 compatible = "ti,omap5430-timer";
616 reg = <0x48034000 0x80>;
617 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
618 ti,hwmods = "timer3";
621 timer4: timer@48036000 {
622 compatible = "ti,omap5430-timer";
623 reg = <0x48036000 0x80>;
624 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
625 ti,hwmods = "timer4";
628 timer5: timer@40138000 {
629 compatible = "ti,omap5430-timer";
630 reg = <0x40138000 0x80>,
632 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
633 ti,hwmods = "timer5";
638 timer6: timer@4013a000 {
639 compatible = "ti,omap5430-timer";
640 reg = <0x4013a000 0x80>,
642 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "timer6";
648 timer7: timer@4013c000 {
649 compatible = "ti,omap5430-timer";
650 reg = <0x4013c000 0x80>,
652 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "timer7";
657 timer8: timer@4013e000 {
658 compatible = "ti,omap5430-timer";
659 reg = <0x4013e000 0x80>,
661 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
662 ti,hwmods = "timer8";
667 timer9: timer@4803e000 {
668 compatible = "ti,omap5430-timer";
669 reg = <0x4803e000 0x80>;
670 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
671 ti,hwmods = "timer9";
675 timer10: timer@48086000 {
676 compatible = "ti,omap5430-timer";
677 reg = <0x48086000 0x80>;
678 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
679 ti,hwmods = "timer10";
683 timer11: timer@48088000 {
684 compatible = "ti,omap5430-timer";
685 reg = <0x48088000 0x80>;
686 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
687 ti,hwmods = "timer11";
692 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
693 reg = <0x4ae14000 0x80>;
694 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
695 ti,hwmods = "wd_timer2";
699 compatible = "ti,omap5-dmm";
700 reg = <0x4e000000 0x800>;
701 interrupts = <0 113 0x4>;
705 emif1: emif@4c000000 {
706 compatible = "ti,emif-4d5";
709 phy-type = <2>; /* DDR PHY type: Intelli PHY */
710 reg = <0x4c000000 0x400>;
711 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
712 hw-caps-read-idle-ctrl;
713 hw-caps-ll-interface;
717 emif2: emif@4d000000 {
718 compatible = "ti,emif-4d5";
721 phy-type = <2>; /* DDR PHY type: Intelli PHY */
722 reg = <0x4d000000 0x400>;
723 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
724 hw-caps-read-idle-ctrl;
725 hw-caps-ll-interface;
729 omap_control_usb2phy: control-phy@4a002300 {
730 compatible = "ti,control-phy-usb2";
731 reg = <0x4a002300 0x4>;
735 omap_control_usb3phy: control-phy@4a002370 {
736 compatible = "ti,control-phy-pipe3";
737 reg = <0x4a002370 0x4>;
741 usb3: omap_dwc3@4a020000 {
742 compatible = "ti,dwc3";
743 ti,hwmods = "usb_otg_ss";
744 reg = <0x4a020000 0x10000>;
745 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
746 #address-cells = <1>;
751 compatible = "snps,dwc3";
752 reg = <0x4a030000 0x10000>;
753 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
754 phys = <&usb2_phy>, <&usb3_phy>;
755 phy-names = "usb2-phy", "usb3-phy";
756 dr_mode = "peripheral";
762 compatible = "ti,omap-ocp2scp";
763 #address-cells = <1>;
765 reg = <0x4a080000 0x20>;
767 ti,hwmods = "ocp2scp1";
768 usb2_phy: usb2phy@4a084000 {
769 compatible = "ti,omap-usb2";
770 reg = <0x4a084000 0x7c>;
771 ctrl-module = <&omap_control_usb2phy>;
775 usb3_phy: usb3phy@4a084400 {
776 compatible = "ti,omap-usb3";
777 reg = <0x4a084400 0x80>,
780 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
781 ctrl-module = <&omap_control_usb3phy>;
786 usbhstll: usbhstll@4a062000 {
787 compatible = "ti,usbhs-tll";
788 reg = <0x4a062000 0x1000>;
789 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "usb_tll_hs";
793 usbhshost: usbhshost@4a064000 {
794 compatible = "ti,usbhs-host";
795 reg = <0x4a064000 0x800>;
796 ti,hwmods = "usb_host_hs";
797 #address-cells = <1>;
801 usbhsohci: ohci@4a064800 {
802 compatible = "ti,ohci-omap3";
803 reg = <0x4a064800 0x400>;
804 interrupt-parent = <&gic>;
805 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
808 usbhsehci: ehci@4a064c00 {
809 compatible = "ti,ehci-omap";
810 reg = <0x4a064c00 0x400>;
811 interrupt-parent = <&gic>;
812 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
816 bandgap: bandgap@4a0021e0 {
817 reg = <0x4a0021e0 0xc
821 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
822 compatible = "ti,omap5430-bandgap";
824 #thermal-sensor-cells = <1>;
829 /include/ "omap54xx-clocks.dtsi"