2 * Device Tree Source for OMAP5 clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 pad_clks_src_ck: pad_clks_src_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <12000000>;
17 pad_clks_ck: pad_clks_ck {
19 compatible = "ti,gate-clock";
20 clocks = <&pad_clks_src_ck>;
25 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
31 slimbus_src_clk: slimbus_src_clk {
33 compatible = "fixed-clock";
34 clock-frequency = <12000000>;
37 slimbus_clk: slimbus_clk {
39 compatible = "ti,gate-clock";
40 clocks = <&slimbus_src_clk>;
45 sys_32k_ck: sys_32k_ck {
47 compatible = "fixed-clock";
48 clock-frequency = <32768>;
51 virt_12000000_ck: virt_12000000_ck {
53 compatible = "fixed-clock";
54 clock-frequency = <12000000>;
57 virt_13000000_ck: virt_13000000_ck {
59 compatible = "fixed-clock";
60 clock-frequency = <13000000>;
63 virt_16800000_ck: virt_16800000_ck {
65 compatible = "fixed-clock";
66 clock-frequency = <16800000>;
69 virt_19200000_ck: virt_19200000_ck {
71 compatible = "fixed-clock";
72 clock-frequency = <19200000>;
75 virt_26000000_ck: virt_26000000_ck {
77 compatible = "fixed-clock";
78 clock-frequency = <26000000>;
81 virt_27000000_ck: virt_27000000_ck {
83 compatible = "fixed-clock";
84 clock-frequency = <27000000>;
87 virt_38400000_ck: virt_38400000_ck {
89 compatible = "fixed-clock";
90 clock-frequency = <38400000>;
93 xclk60mhsp1_ck: xclk60mhsp1_ck {
95 compatible = "fixed-clock";
96 clock-frequency = <60000000>;
99 xclk60mhsp2_ck: xclk60mhsp2_ck {
101 compatible = "fixed-clock";
102 clock-frequency = <60000000>;
105 dpll_abe_ck: dpll_abe_ck {
107 compatible = "ti,omap4-dpll-m4xen-clock";
108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
109 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
112 dpll_abe_x2_ck: dpll_abe_x2_ck {
114 compatible = "ti,omap4-dpll-x2-clock";
115 clocks = <&dpll_abe_ck>;
118 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
120 compatible = "ti,divider-clock";
121 clocks = <&dpll_abe_x2_ck>;
123 ti,autoidle-shift = <8>;
125 ti,index-starts-at-one;
126 ti,invert-autoidle-bit;
129 abe_24m_fclk: abe_24m_fclk {
131 compatible = "fixed-factor-clock";
132 clocks = <&dpll_abe_m2x2_ck>;
139 compatible = "ti,divider-clock";
140 clocks = <&dpll_abe_m2x2_ck>;
143 ti,index-power-of-two;
148 compatible = "fixed-factor-clock";
154 abe_lp_clk_div: abe_lp_clk_div {
156 compatible = "fixed-factor-clock";
157 clocks = <&dpll_abe_m2x2_ck>;
162 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
164 compatible = "ti,divider-clock";
165 clocks = <&dpll_abe_x2_ck>;
167 ti,autoidle-shift = <8>;
169 ti,index-starts-at-one;
170 ti,invert-autoidle-bit;
173 dpll_core_ck: dpll_core_ck {
175 compatible = "ti,omap4-dpll-core-clock";
176 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
177 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
180 dpll_core_x2_ck: dpll_core_x2_ck {
182 compatible = "ti,omap4-dpll-x2-clock";
183 clocks = <&dpll_core_ck>;
186 dpll_core_h21x2_ck: dpll_core_h21x2_ck {
188 compatible = "ti,divider-clock";
189 clocks = <&dpll_core_x2_ck>;
191 ti,autoidle-shift = <8>;
193 ti,index-starts-at-one;
194 ti,invert-autoidle-bit;
199 compatible = "fixed-factor-clock";
200 clocks = <&dpll_core_h21x2_ck>;
207 compatible = "fixed-factor-clock";
208 clocks = <&c2c_fclk>;
213 dpll_core_h11x2_ck: dpll_core_h11x2_ck {
215 compatible = "ti,divider-clock";
216 clocks = <&dpll_core_x2_ck>;
218 ti,autoidle-shift = <8>;
220 ti,index-starts-at-one;
221 ti,invert-autoidle-bit;
224 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_core_x2_ck>;
229 ti,autoidle-shift = <8>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
235 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_core_x2_ck>;
240 ti,autoidle-shift = <8>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
246 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
248 compatible = "ti,divider-clock";
249 clocks = <&dpll_core_x2_ck>;
251 ti,autoidle-shift = <8>;
253 ti,index-starts-at-one;
254 ti,invert-autoidle-bit;
257 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
259 compatible = "ti,divider-clock";
260 clocks = <&dpll_core_x2_ck>;
262 ti,autoidle-shift = <8>;
264 ti,index-starts-at-one;
265 ti,invert-autoidle-bit;
268 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
270 compatible = "ti,divider-clock";
271 clocks = <&dpll_core_x2_ck>;
273 ti,autoidle-shift = <8>;
275 ti,index-starts-at-one;
276 ti,invert-autoidle-bit;
279 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
281 compatible = "ti,divider-clock";
282 clocks = <&dpll_core_x2_ck>;
284 ti,autoidle-shift = <8>;
286 ti,index-starts-at-one;
287 ti,invert-autoidle-bit;
290 dpll_core_m2_ck: dpll_core_m2_ck {
292 compatible = "ti,divider-clock";
293 clocks = <&dpll_core_ck>;
295 ti,autoidle-shift = <8>;
297 ti,index-starts-at-one;
298 ti,invert-autoidle-bit;
301 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
303 compatible = "ti,divider-clock";
304 clocks = <&dpll_core_x2_ck>;
306 ti,autoidle-shift = <8>;
308 ti,index-starts-at-one;
309 ti,invert-autoidle-bit;
312 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_core_h12x2_ck>;
320 dpll_iva_ck: dpll_iva_ck {
322 compatible = "ti,omap4-dpll-clock";
323 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
324 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
327 dpll_iva_x2_ck: dpll_iva_x2_ck {
329 compatible = "ti,omap4-dpll-x2-clock";
330 clocks = <&dpll_iva_ck>;
333 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
335 compatible = "ti,divider-clock";
336 clocks = <&dpll_iva_x2_ck>;
338 ti,autoidle-shift = <8>;
340 ti,index-starts-at-one;
341 ti,invert-autoidle-bit;
344 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
346 compatible = "ti,divider-clock";
347 clocks = <&dpll_iva_x2_ck>;
349 ti,autoidle-shift = <8>;
351 ti,index-starts-at-one;
352 ti,invert-autoidle-bit;
355 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
357 compatible = "fixed-factor-clock";
358 clocks = <&dpll_core_h12x2_ck>;
363 dpll_mpu_ck: dpll_mpu_ck {
365 compatible = "ti,omap4-dpll-clock";
366 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
367 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
370 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
372 compatible = "ti,divider-clock";
373 clocks = <&dpll_mpu_ck>;
375 ti,autoidle-shift = <8>;
377 ti,index-starts-at-one;
378 ti,invert-autoidle-bit;
381 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
383 compatible = "fixed-factor-clock";
384 clocks = <&dpll_abe_m3x2_ck>;
389 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
391 compatible = "fixed-factor-clock";
392 clocks = <&dpll_abe_m3x2_ck>;
397 l3_iclk_div: l3_iclk_div {
399 compatible = "fixed-factor-clock";
400 clocks = <&dpll_core_h12x2_ck>;
405 gpu_l3_iclk: gpu_l3_iclk {
407 compatible = "fixed-factor-clock";
408 clocks = <&l3_iclk_div>;
413 l4_root_clk_div: l4_root_clk_div {
415 compatible = "fixed-factor-clock";
416 clocks = <&l3_iclk_div>;
421 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
423 compatible = "ti,gate-clock";
424 clocks = <&slimbus_clk>;
429 aess_fclk: aess_fclk {
431 compatible = "ti,divider-clock";
438 dmic_sync_mux_ck: dmic_sync_mux_ck {
440 compatible = "ti,mux-clock";
441 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
446 dmic_gfclk: dmic_gfclk {
448 compatible = "ti,mux-clock";
449 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
454 mcasp_sync_mux_ck: mcasp_sync_mux_ck {
456 compatible = "ti,mux-clock";
457 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
462 mcasp_gfclk: mcasp_gfclk {
464 compatible = "ti,mux-clock";
465 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
470 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
472 compatible = "ti,mux-clock";
473 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
478 mcbsp1_gfclk: mcbsp1_gfclk {
480 compatible = "ti,mux-clock";
481 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
486 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
488 compatible = "ti,mux-clock";
489 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
494 mcbsp2_gfclk: mcbsp2_gfclk {
496 compatible = "ti,mux-clock";
497 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
502 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
504 compatible = "ti,mux-clock";
505 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
510 mcbsp3_gfclk: mcbsp3_gfclk {
512 compatible = "ti,mux-clock";
513 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
518 timer5_gfclk_mux: timer5_gfclk_mux {
520 compatible = "ti,mux-clock";
521 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
526 timer6_gfclk_mux: timer6_gfclk_mux {
528 compatible = "ti,mux-clock";
529 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
534 timer7_gfclk_mux: timer7_gfclk_mux {
536 compatible = "ti,mux-clock";
537 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
542 timer8_gfclk_mux: timer8_gfclk_mux {
544 compatible = "ti,mux-clock";
545 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
552 compatible = "fixed-clock";
553 clock-frequency = <0>;
557 sys_clkin: sys_clkin {
559 compatible = "ti,mux-clock";
560 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
562 ti,index-starts-at-one;
565 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
567 compatible = "ti,mux-clock";
568 clocks = <&sys_clkin>, <&sys_32k_ck>;
572 abe_dpll_clk_mux: abe_dpll_clk_mux {
574 compatible = "ti,mux-clock";
575 clocks = <&sys_clkin>, <&sys_32k_ck>;
579 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
581 compatible = "fixed-factor-clock";
582 clocks = <&sys_clkin>;
587 dss_syc_gfclk_div: dss_syc_gfclk_div {
589 compatible = "fixed-factor-clock";
590 clocks = <&sys_clkin>;
595 wkupaon_iclk_mux: wkupaon_iclk_mux {
597 compatible = "ti,mux-clock";
598 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
602 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
604 compatible = "fixed-factor-clock";
605 clocks = <&wkupaon_iclk_mux>;
610 gpio1_dbclk: gpio1_dbclk {
612 compatible = "ti,gate-clock";
613 clocks = <&sys_32k_ck>;
618 timer1_gfclk_mux: timer1_gfclk_mux {
620 compatible = "ti,mux-clock";
621 clocks = <&sys_clkin>, <&sys_32k_ck>;
627 dpll_per_ck: dpll_per_ck {
629 compatible = "ti,omap4-dpll-clock";
630 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
631 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
634 dpll_per_x2_ck: dpll_per_x2_ck {
636 compatible = "ti,omap4-dpll-x2-clock";
637 clocks = <&dpll_per_ck>;
640 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
642 compatible = "ti,divider-clock";
643 clocks = <&dpll_per_x2_ck>;
645 ti,autoidle-shift = <8>;
647 ti,index-starts-at-one;
648 ti,invert-autoidle-bit;
651 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
653 compatible = "ti,divider-clock";
654 clocks = <&dpll_per_x2_ck>;
656 ti,autoidle-shift = <8>;
658 ti,index-starts-at-one;
659 ti,invert-autoidle-bit;
662 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
664 compatible = "ti,divider-clock";
665 clocks = <&dpll_per_x2_ck>;
667 ti,autoidle-shift = <8>;
669 ti,index-starts-at-one;
670 ti,invert-autoidle-bit;
673 dpll_per_m2_ck: dpll_per_m2_ck {
675 compatible = "ti,divider-clock";
676 clocks = <&dpll_per_ck>;
678 ti,autoidle-shift = <8>;
680 ti,index-starts-at-one;
681 ti,invert-autoidle-bit;
684 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
686 compatible = "ti,divider-clock";
687 clocks = <&dpll_per_x2_ck>;
689 ti,autoidle-shift = <8>;
691 ti,index-starts-at-one;
692 ti,invert-autoidle-bit;
695 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
697 compatible = "ti,divider-clock";
698 clocks = <&dpll_per_x2_ck>;
700 ti,autoidle-shift = <8>;
702 ti,index-starts-at-one;
703 ti,invert-autoidle-bit;
706 dpll_unipro1_ck: dpll_unipro1_ck {
708 compatible = "ti,omap4-dpll-clock";
709 clocks = <&sys_clkin>, <&sys_clkin>;
710 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
713 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
715 compatible = "fixed-factor-clock";
716 clocks = <&dpll_unipro1_ck>;
721 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
723 compatible = "ti,divider-clock";
724 clocks = <&dpll_unipro1_ck>;
726 ti,autoidle-shift = <8>;
728 ti,index-starts-at-one;
729 ti,invert-autoidle-bit;
732 dpll_unipro2_ck: dpll_unipro2_ck {
734 compatible = "ti,omap4-dpll-clock";
735 clocks = <&sys_clkin>, <&sys_clkin>;
736 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
739 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
741 compatible = "fixed-factor-clock";
742 clocks = <&dpll_unipro2_ck>;
747 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
749 compatible = "ti,divider-clock";
750 clocks = <&dpll_unipro2_ck>;
752 ti,autoidle-shift = <8>;
754 ti,index-starts-at-one;
755 ti,invert-autoidle-bit;
758 dpll_usb_ck: dpll_usb_ck {
760 compatible = "ti,omap4-dpll-j-type-clock";
761 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
762 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
765 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
767 compatible = "fixed-factor-clock";
768 clocks = <&dpll_usb_ck>;
773 dpll_usb_m2_ck: dpll_usb_m2_ck {
775 compatible = "ti,divider-clock";
776 clocks = <&dpll_usb_ck>;
778 ti,autoidle-shift = <8>;
780 ti,index-starts-at-one;
781 ti,invert-autoidle-bit;
784 func_128m_clk: func_128m_clk {
786 compatible = "fixed-factor-clock";
787 clocks = <&dpll_per_h11x2_ck>;
792 func_12m_fclk: func_12m_fclk {
794 compatible = "fixed-factor-clock";
795 clocks = <&dpll_per_m2x2_ck>;
800 func_24m_clk: func_24m_clk {
802 compatible = "fixed-factor-clock";
803 clocks = <&dpll_per_m2_ck>;
808 func_48m_fclk: func_48m_fclk {
810 compatible = "fixed-factor-clock";
811 clocks = <&dpll_per_m2x2_ck>;
816 func_96m_fclk: func_96m_fclk {
818 compatible = "fixed-factor-clock";
819 clocks = <&dpll_per_m2x2_ck>;
824 l3init_60m_fclk: l3init_60m_fclk {
826 compatible = "ti,divider-clock";
827 clocks = <&dpll_usb_m2_ck>;
829 ti,dividers = <1>, <8>;
832 dss_32khz_clk: dss_32khz_clk {
834 compatible = "ti,gate-clock";
835 clocks = <&sys_32k_ck>;
840 dss_48mhz_clk: dss_48mhz_clk {
842 compatible = "ti,gate-clock";
843 clocks = <&func_48m_fclk>;
848 dss_dss_clk: dss_dss_clk {
850 compatible = "ti,gate-clock";
851 clocks = <&dpll_per_h12x2_ck>;
856 dss_sys_clk: dss_sys_clk {
858 compatible = "ti,gate-clock";
859 clocks = <&dss_syc_gfclk_div>;
864 gpio2_dbclk: gpio2_dbclk {
866 compatible = "ti,gate-clock";
867 clocks = <&sys_32k_ck>;
872 gpio3_dbclk: gpio3_dbclk {
874 compatible = "ti,gate-clock";
875 clocks = <&sys_32k_ck>;
880 gpio4_dbclk: gpio4_dbclk {
882 compatible = "ti,gate-clock";
883 clocks = <&sys_32k_ck>;
888 gpio5_dbclk: gpio5_dbclk {
890 compatible = "ti,gate-clock";
891 clocks = <&sys_32k_ck>;
896 gpio6_dbclk: gpio6_dbclk {
898 compatible = "ti,gate-clock";
899 clocks = <&sys_32k_ck>;
904 gpio7_dbclk: gpio7_dbclk {
906 compatible = "ti,gate-clock";
907 clocks = <&sys_32k_ck>;
912 gpio8_dbclk: gpio8_dbclk {
914 compatible = "ti,gate-clock";
915 clocks = <&sys_32k_ck>;
920 iss_ctrlclk: iss_ctrlclk {
922 compatible = "ti,gate-clock";
923 clocks = <&func_96m_fclk>;
928 lli_txphy_clk: lli_txphy_clk {
930 compatible = "ti,gate-clock";
931 clocks = <&dpll_unipro1_clkdcoldo>;
936 lli_txphy_ls_clk: lli_txphy_ls_clk {
938 compatible = "ti,gate-clock";
939 clocks = <&dpll_unipro1_m2_ck>;
944 mmc1_32khz_clk: mmc1_32khz_clk {
946 compatible = "ti,gate-clock";
947 clocks = <&sys_32k_ck>;
952 sata_ref_clk: sata_ref_clk {
954 compatible = "ti,gate-clock";
955 clocks = <&sys_clkin>;
960 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
962 compatible = "ti,gate-clock";
963 clocks = <&dpll_usb_m2_ck>;
968 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
970 compatible = "ti,gate-clock";
971 clocks = <&dpll_usb_m2_ck>;
976 usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
978 compatible = "ti,gate-clock";
979 clocks = <&dpll_usb_m2_ck>;
984 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
986 compatible = "ti,gate-clock";
987 clocks = <&l3init_60m_fclk>;
992 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
994 compatible = "ti,gate-clock";
995 clocks = <&l3init_60m_fclk>;
1000 usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
1002 compatible = "ti,gate-clock";
1003 clocks = <&l3init_60m_fclk>;
1008 utmi_p1_gfclk: utmi_p1_gfclk {
1010 compatible = "ti,mux-clock";
1011 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
1012 ti,bit-shift = <24>;
1016 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
1018 compatible = "ti,gate-clock";
1019 clocks = <&utmi_p1_gfclk>;
1024 utmi_p2_gfclk: utmi_p2_gfclk {
1026 compatible = "ti,mux-clock";
1027 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
1028 ti,bit-shift = <25>;
1032 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
1034 compatible = "ti,gate-clock";
1035 clocks = <&utmi_p2_gfclk>;
1040 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
1042 compatible = "ti,gate-clock";
1043 clocks = <&l3init_60m_fclk>;
1044 ti,bit-shift = <10>;
1048 usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
1050 compatible = "ti,gate-clock";
1051 clocks = <&dpll_usb_clkdcoldo>;
1056 usb_phy_cm_clk32k: usb_phy_cm_clk32k {
1058 compatible = "ti,gate-clock";
1059 clocks = <&sys_32k_ck>;
1064 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
1066 compatible = "ti,gate-clock";
1067 clocks = <&l3init_60m_fclk>;
1072 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
1074 compatible = "ti,gate-clock";
1075 clocks = <&l3init_60m_fclk>;
1080 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
1082 compatible = "ti,gate-clock";
1083 clocks = <&l3init_60m_fclk>;
1084 ti,bit-shift = <10>;
1088 fdif_fclk: fdif_fclk {
1090 compatible = "ti,divider-clock";
1091 clocks = <&dpll_per_h11x2_ck>;
1092 ti,bit-shift = <24>;
1097 gpu_core_gclk_mux: gpu_core_gclk_mux {
1099 compatible = "ti,mux-clock";
1100 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1101 ti,bit-shift = <24>;
1105 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1107 compatible = "ti,mux-clock";
1108 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
1109 ti,bit-shift = <25>;
1113 hsi_fclk: hsi_fclk {
1115 compatible = "ti,divider-clock";
1116 clocks = <&dpll_per_m2x2_ck>;
1117 ti,bit-shift = <24>;
1122 mmc1_fclk_mux: mmc1_fclk_mux {
1124 compatible = "ti,mux-clock";
1125 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1126 ti,bit-shift = <24>;
1130 mmc1_fclk: mmc1_fclk {
1132 compatible = "ti,divider-clock";
1133 clocks = <&mmc1_fclk_mux>;
1134 ti,bit-shift = <25>;
1139 mmc2_fclk_mux: mmc2_fclk_mux {
1141 compatible = "ti,mux-clock";
1142 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1143 ti,bit-shift = <24>;
1147 mmc2_fclk: mmc2_fclk {
1149 compatible = "ti,divider-clock";
1150 clocks = <&mmc2_fclk_mux>;
1151 ti,bit-shift = <25>;
1156 timer10_gfclk_mux: timer10_gfclk_mux {
1158 compatible = "ti,mux-clock";
1159 clocks = <&sys_clkin>, <&sys_32k_ck>;
1160 ti,bit-shift = <24>;
1164 timer11_gfclk_mux: timer11_gfclk_mux {
1166 compatible = "ti,mux-clock";
1167 clocks = <&sys_clkin>, <&sys_32k_ck>;
1168 ti,bit-shift = <24>;
1172 timer2_gfclk_mux: timer2_gfclk_mux {
1174 compatible = "ti,mux-clock";
1175 clocks = <&sys_clkin>, <&sys_32k_ck>;
1176 ti,bit-shift = <24>;
1180 timer3_gfclk_mux: timer3_gfclk_mux {
1182 compatible = "ti,mux-clock";
1183 clocks = <&sys_clkin>, <&sys_32k_ck>;
1184 ti,bit-shift = <24>;
1188 timer4_gfclk_mux: timer4_gfclk_mux {
1190 compatible = "ti,mux-clock";
1191 clocks = <&sys_clkin>, <&sys_32k_ck>;
1192 ti,bit-shift = <24>;
1196 timer9_gfclk_mux: timer9_gfclk_mux {
1198 compatible = "ti,mux-clock";
1199 clocks = <&sys_clkin>, <&sys_32k_ck>;
1200 ti,bit-shift = <24>;
1205 &cm_core_clockdomains {
1206 l3init_clkdm: l3init_clkdm {
1207 compatible = "ti,clockdomain";
1208 clocks = <&dpll_usb_ck>;
1213 auxclk0_src_gate_ck: auxclk0_src_gate_ck {
1215 compatible = "ti,composite-no-wait-gate-clock";
1216 clocks = <&dpll_core_m3x2_ck>;
1221 auxclk0_src_mux_ck: auxclk0_src_mux_ck {
1223 compatible = "ti,composite-mux-clock";
1224 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1229 auxclk0_src_ck: auxclk0_src_ck {
1231 compatible = "ti,composite-clock";
1232 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
1235 auxclk0_ck: auxclk0_ck {
1237 compatible = "ti,divider-clock";
1238 clocks = <&auxclk0_src_ck>;
1239 ti,bit-shift = <16>;
1244 auxclk1_src_gate_ck: auxclk1_src_gate_ck {
1246 compatible = "ti,composite-no-wait-gate-clock";
1247 clocks = <&dpll_core_m3x2_ck>;
1252 auxclk1_src_mux_ck: auxclk1_src_mux_ck {
1254 compatible = "ti,composite-mux-clock";
1255 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1260 auxclk1_src_ck: auxclk1_src_ck {
1262 compatible = "ti,composite-clock";
1263 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
1266 auxclk1_ck: auxclk1_ck {
1268 compatible = "ti,divider-clock";
1269 clocks = <&auxclk1_src_ck>;
1270 ti,bit-shift = <16>;
1275 auxclk2_src_gate_ck: auxclk2_src_gate_ck {
1277 compatible = "ti,composite-no-wait-gate-clock";
1278 clocks = <&dpll_core_m3x2_ck>;
1283 auxclk2_src_mux_ck: auxclk2_src_mux_ck {
1285 compatible = "ti,composite-mux-clock";
1286 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1291 auxclk2_src_ck: auxclk2_src_ck {
1293 compatible = "ti,composite-clock";
1294 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
1297 auxclk2_ck: auxclk2_ck {
1299 compatible = "ti,divider-clock";
1300 clocks = <&auxclk2_src_ck>;
1301 ti,bit-shift = <16>;
1306 auxclk3_src_gate_ck: auxclk3_src_gate_ck {
1308 compatible = "ti,composite-no-wait-gate-clock";
1309 clocks = <&dpll_core_m3x2_ck>;
1314 auxclk3_src_mux_ck: auxclk3_src_mux_ck {
1316 compatible = "ti,composite-mux-clock";
1317 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1322 auxclk3_src_ck: auxclk3_src_ck {
1324 compatible = "ti,composite-clock";
1325 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1328 auxclk3_ck: auxclk3_ck {
1330 compatible = "ti,divider-clock";
1331 clocks = <&auxclk3_src_ck>;
1332 ti,bit-shift = <16>;
1337 auxclk4_src_gate_ck: auxclk4_src_gate_ck {
1339 compatible = "ti,composite-no-wait-gate-clock";
1340 clocks = <&dpll_core_m3x2_ck>;
1345 auxclk4_src_mux_ck: auxclk4_src_mux_ck {
1347 compatible = "ti,composite-mux-clock";
1348 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1353 auxclk4_src_ck: auxclk4_src_ck {
1355 compatible = "ti,composite-clock";
1356 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1359 auxclk4_ck: auxclk4_ck {
1361 compatible = "ti,divider-clock";
1362 clocks = <&auxclk4_src_ck>;
1363 ti,bit-shift = <16>;
1368 auxclkreq0_ck: auxclkreq0_ck {
1370 compatible = "ti,mux-clock";
1371 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1376 auxclkreq1_ck: auxclkreq1_ck {
1378 compatible = "ti,mux-clock";
1379 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1384 auxclkreq2_ck: auxclkreq2_ck {
1386 compatible = "ti,mux-clock";
1387 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1392 auxclkreq3_ck: auxclkreq3_ck {
1394 compatible = "ti,mux-clock";
1395 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;