2 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
4 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
6 * Licensed under GPLv2 or later
9 /include/ "skeleton.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "oxsemi,ox820";
18 enable-method = "oxsemi,ox820-smp";
22 compatible = "arm,arm11mpcore";
29 compatible = "arm,arm11mpcore";
36 /* Max 512MB @ 0x60000000 */
37 reg = <0x60000000 0x20000000>;
42 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
48 compatible = "fixed-clock";
50 clock-frequency = <125000000>;
54 compatible = "fixed-factor-clock";
62 compatible = "fixed-clock";
64 clock-frequency = <850000000>;
68 compatible = "fixed-factor-clock";
79 compatible = "simple-bus";
81 interrupt-parent = <&gic>;
83 nandc: nand-controller@41000000 {
84 compatible = "oxsemi,ox820-nand";
85 reg = <0x41000000 0x100000>;
86 clocks = <&stdclk 11>;
93 etha: ethernet@40400000 {
94 compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
95 reg = <0x40400000 0x2000>;
96 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-names = "macirq", "eth_wake_irq";
99 mac-address = [000000000000]; /* Filled in by U-Boot */
102 clocks = <&stdclk 9>, <&gmacclk>;
103 clock-names = "gmac", "stmmaceth";
106 /* Regmap for sys registers */
107 oxsemi,sys-ctrl = <&sys>;
112 apb-bridge@44000000 {
113 #address-cells = <1>;
115 compatible = "simple-bus";
116 ranges = <0 0x44000000 0x1000000>;
119 compatible = "oxsemi,ox820-pinctrl";
121 /* Regmap for sys registers */
122 oxsemi,sys-ctrl = <&sys>;
124 pinctrl_uart0: uart0 {
126 pins = "gpio30", "gpio31";
131 pinctrl_uart0_modem: uart0_modem {
133 pins = "gpio24", "gpio24", "gpio26", "gpio27";
137 pins = "gpio28", "gpio29";
142 pinctrl_uart1: uart1 {
144 pins = "gpio7", "gpio8";
149 pinctrl_uart1_modem: uart1_modem {
151 pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
156 pinctrl_etha_mdio: etha_mdio {
158 pins = "gpio3", "gpio4";
165 pins = "gpio12", "gpio13", "gpio14", "gpio15",
166 "gpio16", "gpio17", "gpio18", "gpio19",
167 "gpio20", "gpio21", "gpio22", "gpio23",
175 compatible = "oxsemi,ox820-gpio";
176 reg = <0x000000 0x100000>;
177 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
183 oxsemi,gpio-bank = <0>;
184 gpio-ranges = <&pinctrl 0 0 32>;
188 compatible = "oxsemi,ox820-gpio";
189 reg = <0x100000 0x100000>;
190 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
196 oxsemi,gpio-bank = <1>;
197 gpio-ranges = <&pinctrl 0 32 18>;
200 uart0: serial@200000 {
201 compatible = "ns16550a";
202 reg = <0x200000 0x100000>;
203 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
207 current-speed = <115200>;
211 resets = <&reset 17>;
214 uart1: serial@300000 {
215 compatible = "ns16550a";
216 reg = <0x200000 0x100000>;
217 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
221 current-speed = <115200>;
225 resets = <&reset 18>;
229 #address-cells = <1>;
231 compatible = "simple-bus";
232 ranges = <0 0x400000 0x100000>;
234 intc: interrupt-controller@0 {
235 compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
236 interrupt-controller;
238 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
239 #interrupt-cells = <1>;
240 valid-mask = <0xFFFFFFFF>;
245 compatible = "oxsemi,ox820-rps-timer";
248 interrupt-parent = <&intc>;
253 sys: sys-ctrl@e00000 {
254 compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
255 reg = <0xe00000 0x200000>;
257 reset: reset-controller {
258 compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
263 compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
269 apb-bridge@47000000 {
270 #address-cells = <1>;
272 compatible = "simple-bus";
273 ranges = <0 0x47000000 0x1000000>;
276 compatible = "arm,arm11mp-scu";
281 compatible = "arm,arm11mp-twd-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
288 compatible = "arm,arm11mp-gic";
289 interrupt-controller;
290 #interrupt-cells = <3>;
291 reg = <0x1000 0x1000>,