2 * DTS file for CSR SiRFprimaII SoC
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 /include/ "skeleton.dtsi"
11 compatible = "sirf,prima2";
14 interrupt-parent = <&intc>;
21 compatible = "arm,cortex-a9";
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
29 timebase-frequency = <0>;
31 clock-frequency = <0>;
36 compatible = "simple-bus";
39 ranges = <0x40000000 0x40000000 0x80000000>;
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
43 reg = <0x80040000 0x1000>;
45 arm,tag-latency = <1 1 1>;
46 arm,data-latency = <1 1 1>;
47 arm,filter-ranges = <0 0x40000000>;
50 intc: interrupt-controller@80020000 {
51 #interrupt-cells = <1>;
53 compatible = "sirf,prima2-intc";
54 reg = <0x80020000 0x1000>;
58 compatible = "simple-bus";
61 ranges = <0x88000000 0x88000000 0x40000>;
63 clks: clock-controller@88000000 {
64 compatible = "sirf,prima2-clkc";
65 reg = <0x88000000 0x1000>;
70 reset-controller@88010000 {
71 compatible = "sirf,prima2-rstc";
72 reg = <0x88010000 0x1000>;
75 rsc-controller@88020000 {
76 compatible = "sirf,prima2-rsc";
77 reg = <0x88020000 0x1000>;
81 compatible = "sirf,prima2-cphifbg";
82 reg = <0x88030000 0x1000>;
87 compatible = "simple-bus";
90 ranges = <0x90000000 0x90000000 0x10000>;
92 memory-controller@90000000 {
93 compatible = "sirf,prima2-memc";
94 reg = <0x90000000 0x2000>;
100 compatible = "sirf,prima2-memcmon";
101 reg = <0x90002000 0x200>;
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0x90010000 0x90010000 0x30000>;
114 compatible = "sirf,prima2-lcd";
115 reg = <0x90010000 0x20000>;
120 compatible = "sirf,prima2-vpp";
121 reg = <0x90020000 0x10000>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
131 ranges = <0x98000000 0x98000000 0x8000000>;
134 compatible = "powervr,sgx531";
135 reg = <0x98000000 0x8000000>;
142 compatible = "simple-bus";
143 #address-cells = <1>;
145 ranges = <0xa0000000 0xa0000000 0x8000000>;
147 multimedia@a0000000 {
148 compatible = "sirf,prima2-video-codec";
149 reg = <0xa0000000 0x8000000>;
156 compatible = "simple-bus";
157 #address-cells = <1>;
159 ranges = <0xa8000000 0xa8000000 0x2000000>;
162 compatible = "sirf,prima2-dspif";
163 reg = <0xa8000000 0x10000>;
168 compatible = "sirf,prima2-gps";
169 reg = <0xa8010000 0x10000>;
175 compatible = "sirf,prima2-dsp";
176 reg = <0xa9000000 0x1000000>;
183 compatible = "simple-bus";
184 #address-cells = <1>;
186 ranges = <0xb0000000 0xb0000000 0x180000>,
187 <0x56000000 0x56000000 0x1b00000>;
190 compatible = "sirf,prima2-tick";
191 reg = <0xb0020000 0x1000>;
196 compatible = "sirf,prima2-nand";
197 reg = <0xb0030000 0x10000>;
203 compatible = "sirf,prima2-audio";
204 reg = <0xb0040000 0x10000>;
209 uart0: uart@b0050000 {
211 compatible = "sirf,prima2-uart";
212 reg = <0xb0050000 0x1000>;
216 sirf,uart-dma-rx-channel = <21>;
217 sirf,uart-dma-tx-channel = <2>;
220 uart1: uart@b0060000 {
222 compatible = "sirf,prima2-uart";
223 reg = <0xb0060000 0x1000>;
229 uart2: uart@b0070000 {
231 compatible = "sirf,prima2-uart";
232 reg = <0xb0070000 0x1000>;
236 sirf,uart-dma-rx-channel = <6>;
237 sirf,uart-dma-tx-channel = <7>;
242 compatible = "sirf,prima2-usp";
243 reg = <0xb0080000 0x10000>;
247 sirf,usp-dma-rx-channel = <17>;
248 sirf,usp-dma-tx-channel = <18>;
253 compatible = "sirf,prima2-usp";
254 reg = <0xb0090000 0x10000>;
258 sirf,usp-dma-rx-channel = <14>;
259 sirf,usp-dma-tx-channel = <15>;
264 compatible = "sirf,prima2-usp";
265 reg = <0xb00a0000 0x10000>;
269 sirf,usp-dma-rx-channel = <10>;
270 sirf,usp-dma-tx-channel = <11>;
273 dmac0: dma-controller@b00b0000 {
275 compatible = "sirf,prima2-dmac";
276 reg = <0xb00b0000 0x10000>;
281 dmac1: dma-controller@b0160000 {
283 compatible = "sirf,prima2-dmac";
284 reg = <0xb0160000 0x10000>;
290 compatible = "sirf,prima2-vip";
291 reg = <0xb00C0000 0x10000>;
294 sirf,vip-dma-rx-channel = <16>;
299 compatible = "sirf,prima2-spi";
300 reg = <0xb00d0000 0x10000>;
302 sirf,spi-num-chipselects = <1>;
303 sirf,spi-dma-rx-channel = <25>;
304 sirf,spi-dma-tx-channel = <20>;
305 #address-cells = <1>;
313 compatible = "sirf,prima2-spi";
314 reg = <0xb0170000 0x10000>;
316 sirf,spi-num-chipselects = <1>;
317 sirf,spi-dma-rx-channel = <12>;
318 sirf,spi-dma-tx-channel = <13>;
319 #address-cells = <1>;
327 compatible = "sirf,prima2-i2c";
328 reg = <0xb00e0000 0x10000>;
331 #address-cells = <1>;
337 compatible = "sirf,prima2-i2c";
338 reg = <0xb00f0000 0x10000>;
341 #address-cells = <1>;
346 compatible = "sirf,prima2-tsc";
347 reg = <0xb0110000 0x10000>;
352 gpio: pinctrl@b0120000 {
354 #interrupt-cells = <2>;
355 compatible = "sirf,prima2-pinctrl";
356 reg = <0xb0120000 0x10000>;
357 interrupts = <43 44 45 46 47>;
359 interrupt-controller;
361 lcd_16pins_a: lcd0@0 {
363 sirf,pins = "lcd_16bitsgrp";
364 sirf,function = "lcd_16bits";
367 lcd_18pins_a: lcd0@1 {
369 sirf,pins = "lcd_18bitsgrp";
370 sirf,function = "lcd_18bits";
373 lcd_24pins_a: lcd0@2 {
375 sirf,pins = "lcd_24bitsgrp";
376 sirf,function = "lcd_24bits";
379 lcdrom_pins_a: lcdrom0@0 {
381 sirf,pins = "lcdromgrp";
382 sirf,function = "lcdrom";
385 uart0_pins_a: uart0@0 {
387 sirf,pins = "uart0grp";
388 sirf,function = "uart0";
391 uart1_pins_a: uart1@0 {
393 sirf,pins = "uart1grp";
394 sirf,function = "uart1";
397 uart2_pins_a: uart2@0 {
399 sirf,pins = "uart2grp";
400 sirf,function = "uart2";
403 uart2_noflow_pins_a: uart2@1 {
405 sirf,pins = "uart2_nostreamctrlgrp";
406 sirf,function = "uart2_nostreamctrl";
409 spi0_pins_a: spi0@0 {
411 sirf,pins = "spi0grp";
412 sirf,function = "spi0";
415 spi1_pins_a: spi1@0 {
417 sirf,pins = "spi1grp";
418 sirf,function = "spi1";
421 i2c0_pins_a: i2c0@0 {
423 sirf,pins = "i2c0grp";
424 sirf,function = "i2c0";
427 i2c1_pins_a: i2c1@0 {
429 sirf,pins = "i2c1grp";
430 sirf,function = "i2c1";
433 pwm0_pins_a: pwm0@0 {
435 sirf,pins = "pwm0grp";
436 sirf,function = "pwm0";
439 pwm1_pins_a: pwm1@0 {
441 sirf,pins = "pwm1grp";
442 sirf,function = "pwm1";
445 pwm2_pins_a: pwm2@0 {
447 sirf,pins = "pwm2grp";
448 sirf,function = "pwm2";
451 pwm3_pins_a: pwm3@0 {
453 sirf,pins = "pwm3grp";
454 sirf,function = "pwm3";
459 sirf,pins = "gpsgrp";
460 sirf,function = "gps";
465 sirf,pins = "vipgrp";
466 sirf,function = "vip";
469 sdmmc0_pins_a: sdmmc0@0 {
471 sirf,pins = "sdmmc0grp";
472 sirf,function = "sdmmc0";
475 sdmmc1_pins_a: sdmmc1@0 {
477 sirf,pins = "sdmmc1grp";
478 sirf,function = "sdmmc1";
481 sdmmc2_pins_a: sdmmc2@0 {
483 sirf,pins = "sdmmc2grp";
484 sirf,function = "sdmmc2";
487 sdmmc3_pins_a: sdmmc3@0 {
489 sirf,pins = "sdmmc3grp";
490 sirf,function = "sdmmc3";
493 sdmmc4_pins_a: sdmmc4@0 {
495 sirf,pins = "sdmmc4grp";
496 sirf,function = "sdmmc4";
499 sdmmc5_pins_a: sdmmc5@0 {
501 sirf,pins = "sdmmc5grp";
502 sirf,function = "sdmmc5";
507 sirf,pins = "i2sgrp";
508 sirf,function = "i2s";
511 ac97_pins_a: ac97@0 {
513 sirf,pins = "ac97grp";
514 sirf,function = "ac97";
517 nand_pins_a: nand@0 {
519 sirf,pins = "nandgrp";
520 sirf,function = "nand";
523 usp0_pins_a: usp0@0 {
525 sirf,pins = "usp0grp";
526 sirf,function = "usp0";
529 usp1_pins_a: usp1@0 {
531 sirf,pins = "usp1grp";
532 sirf,function = "usp1";
535 usp2_pins_a: usp2@0 {
537 sirf,pins = "usp2grp";
538 sirf,function = "usp2";
541 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
543 sirf,pins = "usb0_utmi_drvbusgrp";
544 sirf,function = "usb0_utmi_drvbus";
547 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
549 sirf,pins = "usb1_utmi_drvbusgrp";
550 sirf,function = "usb1_utmi_drvbus";
553 warm_rst_pins_a: warm_rst@0 {
555 sirf,pins = "warm_rstgrp";
556 sirf,function = "warm_rst";
559 pulse_count_pins_a: pulse_count@0 {
561 sirf,pins = "pulse_countgrp";
562 sirf,function = "pulse_count";
565 cko0_pins_a: cko0@0 {
567 sirf,pins = "cko0grp";
568 sirf,function = "cko0";
571 cko1_pins_a: cko1@0 {
573 sirf,pins = "cko1grp";
574 sirf,function = "cko1";
580 compatible = "sirf,prima2-pwm";
581 reg = <0xb0130000 0x10000>;
586 compatible = "sirf,prima2-efuse";
587 reg = <0xb0140000 0x10000>;
592 compatible = "sirf,prima2-pulsec";
593 reg = <0xb0150000 0x10000>;
599 compatible = "sirf,prima2-pciiobg", "simple-bus";
600 #address-cells = <1>;
602 ranges = <0x56000000 0x56000000 0x1b00000>;
604 sd0: sdhci@56000000 {
606 compatible = "sirf,prima2-sdhc";
607 reg = <0x56000000 0x100000>;
611 sd1: sdhci@56100000 {
613 compatible = "sirf,prima2-sdhc";
614 reg = <0x56100000 0x100000>;
618 sd2: sdhci@56200000 {
620 compatible = "sirf,prima2-sdhc";
621 reg = <0x56200000 0x100000>;
625 sd3: sdhci@56300000 {
627 compatible = "sirf,prima2-sdhc";
628 reg = <0x56300000 0x100000>;
632 sd4: sdhci@56400000 {
634 compatible = "sirf,prima2-sdhc";
635 reg = <0x56400000 0x100000>;
639 sd5: sdhci@56500000 {
641 compatible = "sirf,prima2-sdhc";
642 reg = <0x56500000 0x100000>;
647 compatible = "sirf,prima2-pcicp";
648 reg = <0x57900000 0x100000>;
652 rom-interface@57a00000 {
653 compatible = "sirf,prima2-romif";
654 reg = <0x57a00000 0x100000>;
660 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
661 #address-cells = <1>;
663 reg = <0x80030000 0x10000>;
666 compatible = "sirf,prima2-gpsrtc";
667 reg = <0x1000 0x1000>;
668 interrupts = <55 56 57>;
672 compatible = "sirf,prima2-sysrtc";
673 reg = <0x2000 0x1000>;
674 interrupts = <52 53 54>;
678 compatible = "sirf,prima2-pwrc";
679 reg = <0x3000 0x1000>;
685 compatible = "simple-bus";
686 #address-cells = <1>;
688 ranges = <0xb8000000 0xb8000000 0x40000>;
691 compatible = "chipidea,ci13611a-prima2";
692 reg = <0xb8000000 0x10000>;
698 compatible = "chipidea,ci13611a-prima2";
699 reg = <0xb8010000 0x10000>;
705 compatible = "synopsys,dwc-ahsata";
706 reg = <0xb8020000 0x10000>;
711 compatible = "sirf,prima2-security";
712 reg = <0xb8030000 0x10000>;