arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 smem_region: smem@80000000 {
  20                         reg = <0x80000000 0x200000>;
  21                         no-map;
  22                 };
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc0>;
  36                         qcom,saw = <&saw0>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc1>;
  47                         qcom,saw = <&saw1>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 cpu@3 {
  63                         compatible = "qcom,krait";
  64                         enable-method = "qcom,kpss-acc-v1";
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2>;
  68                         qcom,acc = <&acc3>;
  69                         qcom,saw = <&saw3>;
  70                         cpu-idle-states = <&CPU_SPC>;
  71                 };
  72
  73                 L2: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <900>;
  84                                 min-residency-us = <3000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 10 0x304>;
  92         };
  93
  94         clocks {
  95                 cxo_board {
  96                         compatible = "fixed-clock";
  97                         #clock-cells = <0>;
  98                         clock-frequency = <19200000>;
  99                 };
 100
 101                 pxo_board {
 102                         compatible = "fixed-clock";
 103                         #clock-cells = <0>;
 104                         clock-frequency = <27000000>;
 105                 };
 106
 107                 sleep_clk {
 108                         compatible = "fixed-clock";
 109                         #clock-cells = <0>;
 110                         clock-frequency = <32768>;
 111                 };
 112         };
 113
 114         sfpb_mutex: hwmutex {
 115                 compatible = "qcom,sfpb-mutex";
 116                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 117                 #hwlock-cells = <1>;
 118         };
 119
 120         smem {
 121                 compatible = "qcom,smem";
 122                 memory-region = <&smem_region>;
 123
 124                 hwlocks = <&sfpb_mutex 3>;
 125         };
 126
 127         smsm {
 128                 compatible = "qcom,smsm";
 129
 130                 #address-cells = <1>;
 131                 #size-cells = <0>;
 132
 133                 qcom,ipc-1 = <&l2cc 8 4>;
 134                 qcom,ipc-2 = <&l2cc 8 14>;
 135                 qcom,ipc-3 = <&l2cc 8 23>;
 136                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 137
 138                 apps_smsm: apps@0 {
 139                         reg = <0>;
 140                         #qcom,state-cells = <1>;
 141                 };
 142
 143                 modem_smsm: modem@1 {
 144                         reg = <1>;
 145                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 146
 147                         interrupt-controller;
 148                         #interrupt-cells = <2>;
 149                 };
 150
 151                 q6_smsm: q6@2 {
 152                         reg = <2>;
 153                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 154
 155                         interrupt-controller;
 156                         #interrupt-cells = <2>;
 157                 };
 158
 159                 wcnss_smsm: wcnss@3 {
 160                         reg = <3>;
 161                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 162
 163                         interrupt-controller;
 164                         #interrupt-cells = <2>;
 165                 };
 166
 167                 dsps_smsm: dsps@4 {
 168                         reg = <4>;
 169                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 170
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                 };
 174         };
 175
 176         soc: soc {
 177                 #address-cells = <1>;
 178                 #size-cells = <1>;
 179                 ranges;
 180                 compatible = "simple-bus";
 181
 182                 tlmm_pinmux: pinctrl@800000 {
 183                         compatible = "qcom,apq8064-pinctrl";
 184                         reg = <0x800000 0x4000>;
 185
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                         interrupt-controller;
 189                         #interrupt-cells = <2>;
 190                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 191
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&ps_hold>;
 194                 };
 195
 196                 sfpb_wrapper_mutex: syscon@1200000 {
 197                         compatible = "syscon";
 198                         reg = <0x01200000 0x8000>;
 199                 };
 200
 201                 intc: interrupt-controller@2000000 {
 202                         compatible = "qcom,msm-qgic2";
 203                         interrupt-controller;
 204                         #interrupt-cells = <3>;
 205                         reg = <0x02000000 0x1000>,
 206                               <0x02002000 0x1000>;
 207                 };
 208
 209                 timer@200a000 {
 210                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 211                         interrupts = <1 1 0x301>,
 212                                      <1 2 0x301>,
 213                                      <1 3 0x301>;
 214                         reg = <0x0200a000 0x100>;
 215                         clock-frequency = <27000000>,
 216                                           <32768>;
 217                         cpu-offset = <0x80000>;
 218                 };
 219
 220                 acc0: clock-controller@2088000 {
 221                         compatible = "qcom,kpss-acc-v1";
 222                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 223                 };
 224
 225                 acc1: clock-controller@2098000 {
 226                         compatible = "qcom,kpss-acc-v1";
 227                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 228                 };
 229
 230                 acc2: clock-controller@20a8000 {
 231                         compatible = "qcom,kpss-acc-v1";
 232                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 233                 };
 234
 235                 acc3: clock-controller@20b8000 {
 236                         compatible = "qcom,kpss-acc-v1";
 237                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 238                 };
 239
 240                 saw0: power-controller@2089000 {
 241                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 242                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 243                         regulator;
 244                 };
 245
 246                 saw1: power-controller@2099000 {
 247                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 248                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 249                         regulator;
 250                 };
 251
 252                 saw2: power-controller@20a9000 {
 253                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 254                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 255                         regulator;
 256                 };
 257
 258                 saw3: power-controller@20b9000 {
 259                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 260                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 261                         regulator;
 262                 };
 263
 264                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 265                         compatible      = "syscon";
 266                         reg             = <0x12100000 0x10000>;
 267                 };
 268
 269                 gsbi1: gsbi@12440000 {
 270                         status = "disabled";
 271                         compatible = "qcom,gsbi-v1.0.0";
 272                         cell-index = <1>;
 273                         reg = <0x12440000 0x100>;
 274                         clocks = <&gcc GSBI1_H_CLK>;
 275                         clock-names = "iface";
 276                         #address-cells = <1>;
 277                         #size-cells = <1>;
 278                         ranges;
 279
 280                         syscon-tcsr = <&tcsr>;
 281
 282                         gsbi1_i2c: i2c@12460000 {
 283                                 compatible = "qcom,i2c-qup-v1.1.1";
 284                                 pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
 285                                 pinctrl-names = "default", "sleep";
 286                                 reg = <0x12460000 0x1000>;
 287                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 288                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 289                                 clock-names = "core", "iface";
 290                                 #address-cells = <1>;
 291                                 #size-cells = <0>;
 292                         };
 293
 294                 };
 295
 296                 gsbi2: gsbi@12480000 {
 297                         status = "disabled";
 298                         compatible = "qcom,gsbi-v1.0.0";
 299                         cell-index = <2>;
 300                         reg = <0x12480000 0x100>;
 301                         clocks = <&gcc GSBI2_H_CLK>;
 302                         clock-names = "iface";
 303                         #address-cells = <1>;
 304                         #size-cells = <1>;
 305                         ranges;
 306
 307                         syscon-tcsr = <&tcsr>;
 308
 309                         gsbi2_i2c: i2c@124a0000 {
 310                                 compatible = "qcom,i2c-qup-v1.1.1";
 311                                 reg = <0x124a0000 0x1000>;
 312                                 pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
 313                                 pinctrl-names = "default", "sleep";
 314                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 315                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 316                                 clock-names = "core", "iface";
 317                                 #address-cells = <1>;
 318                                 #size-cells = <0>;
 319                         };
 320                 };
 321
 322                 gsbi3: gsbi@16200000 {
 323                         status = "disabled";
 324                         compatible = "qcom,gsbi-v1.0.0";
 325                         cell-index = <3>;
 326                         reg = <0x16200000 0x100>;
 327                         clocks = <&gcc GSBI3_H_CLK>;
 328                         clock-names = "iface";
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         ranges;
 332                         gsbi3_i2c: i2c@16280000 {
 333                                 compatible = "qcom,i2c-qup-v1.1.1";
 334                                 pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
 335                                 pinctrl-names = "default", "sleep";
 336                                 reg = <0x16280000 0x1000>;
 337                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 338                                 clocks = <&gcc GSBI3_QUP_CLK>,
 339                                          <&gcc GSBI3_H_CLK>;
 340                                 clock-names = "core", "iface";
 341                                 #address-cells = <1>;
 342                                 #size-cells = <0>;
 343                         };
 344                 };
 345
 346                 gsbi4: gsbi@16300000 {
 347                         status = "disabled";
 348                         compatible = "qcom,gsbi-v1.0.0";
 349                         cell-index = <4>;
 350                         reg = <0x16300000 0x03>;
 351                         clocks = <&gcc GSBI4_H_CLK>;
 352                         clock-names = "iface";
 353                         #address-cells = <1>;
 354                         #size-cells = <1>;
 355                         ranges;
 356
 357                         gsbi4_i2c: i2c@16380000 {
 358                                 compatible = "qcom,i2c-qup-v1.1.1";
 359                                 pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;
 360                                 pinctrl-names = "default", "sleep";
 361                                 reg = <0x16380000 0x1000>;
 362                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 363                                 clocks = <&gcc GSBI4_QUP_CLK>,
 364                                          <&gcc GSBI4_H_CLK>;
 365                                 clock-names = "core", "iface";
 366                         };
 367                 };
 368
 369                 gsbi5: gsbi@1a200000 {
 370                         status = "disabled";
 371                         compatible = "qcom,gsbi-v1.0.0";
 372                         cell-index = <5>;
 373                         reg = <0x1a200000 0x03>;
 374                         clocks = <&gcc GSBI5_H_CLK>;
 375                         clock-names = "iface";
 376                         #address-cells = <1>;
 377                         #size-cells = <1>;
 378                         ranges;
 379
 380                         gsbi5_serial: serial@1a240000 {
 381                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 382                                 reg = <0x1a240000 0x100>,
 383                                       <0x1a200000 0x03>;
 384                                 interrupts = <0 154 0x0>;
 385                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 386                                 clock-names = "core", "iface";
 387                                 status = "disabled";
 388                         };
 389
 390                         gsbi5_spi: spi@1a280000 {
 391                                 compatible = "qcom,spi-qup-v1.1.1";
 392                                 reg = <0x1a280000 0x1000>;
 393                                 interrupts = <0 155 0>;
 394                                 pinctrl-0 = <&spi5_default &spi5_sleep>;
 395                                 pinctrl-names = "default", "sleep";
 396                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 397                                 clock-names = "core", "iface";
 398                                 status = "disabled";
 399                                 #address-cells = <1>;
 400                                 #size-cells = <0>;
 401                         };
 402                 };
 403
 404                 gsbi6: gsbi@16500000 {
 405                         status = "disabled";
 406                         compatible = "qcom,gsbi-v1.0.0";
 407                         cell-index = <6>;
 408                         reg = <0x16500000 0x03>;
 409                         clocks = <&gcc GSBI6_H_CLK>;
 410                         clock-names = "iface";
 411                         #address-cells = <1>;
 412                         #size-cells = <1>;
 413                         ranges;
 414
 415                         gsbi6_serial: serial@16540000 {
 416                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 417                                 reg = <0x16540000 0x100>,
 418                                       <0x16500000 0x03>;
 419                                 interrupts = <0 156 0x0>;
 420                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 421                                 clock-names = "core", "iface";
 422                                 status = "disabled";
 423                         };
 424
 425                         gsbi6_i2c: i2c@16580000 {
 426                                 compatible = "qcom,i2c-qup-v1.1.1";
 427                                 pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>;
 428                                 pinctrl-names = "default", "sleep";
 429                                 reg = <0x16580000 0x1000>;
 430                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 431                                 clocks = <&gcc GSBI6_QUP_CLK>,
 432                                          <&gcc GSBI6_H_CLK>;
 433                                 clock-names = "core", "iface";
 434                         };
 435                 };
 436
 437                 gsbi7: gsbi@16600000 {
 438                         status = "disabled";
 439                         compatible = "qcom,gsbi-v1.0.0";
 440                         cell-index = <7>;
 441                         reg = <0x16600000 0x100>;
 442                         clocks = <&gcc GSBI7_H_CLK>;
 443                         clock-names = "iface";
 444                         #address-cells = <1>;
 445                         #size-cells = <1>;
 446                         ranges;
 447                         syscon-tcsr = <&tcsr>;
 448
 449                         gsbi7_serial: serial@16640000 {
 450                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 451                                 reg = <0x16640000 0x1000>,
 452                                       <0x16600000 0x1000>;
 453                                 interrupts = <0 158 0x0>;
 454                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 455                                 clock-names = "core", "iface";
 456                                 status = "disabled";
 457                         };
 458                 };
 459
 460                 rng@1a500000 {
 461                         compatible = "qcom,prng";
 462                         reg = <0x1a500000 0x200>;
 463                         clocks = <&gcc PRNG_CLK>;
 464                         clock-names = "core";
 465                 };
 466
 467                 qcom,ssbi@500000 {
 468                         compatible = "qcom,ssbi";
 469                         reg = <0x00500000 0x1000>;
 470                         qcom,controller-type = "pmic-arbiter";
 471
 472                         pmicintc: pmic@0 {
 473                                 compatible = "qcom,pm8921";
 474                                 interrupt-parent = <&tlmm_pinmux>;
 475                                 interrupts = <74 8>;
 476                                 #interrupt-cells = <2>;
 477                                 interrupt-controller;
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480
 481                                 pm8921_gpio: gpio@150 {
 482
 483                                         compatible = "qcom,pm8921-gpio",
 484                                                      "qcom,ssbi-gpio";
 485                                         reg = <0x150>;
 486                                         interrupts = <192 1>, <193 1>, <194 1>,
 487                                                      <195 1>, <196 1>, <197 1>,
 488                                                      <198 1>, <199 1>, <200 1>,
 489                                                      <201 1>, <202 1>, <203 1>,
 490                                                      <204 1>, <205 1>, <206 1>,
 491                                                      <207 1>, <208 1>, <209 1>,
 492                                                      <210 1>, <211 1>, <212 1>,
 493                                                      <213 1>, <214 1>, <215 1>,
 494                                                      <216 1>, <217 1>, <218 1>,
 495                                                      <219 1>, <220 1>, <221 1>,
 496                                                      <222 1>, <223 1>, <224 1>,
 497                                                      <225 1>, <226 1>, <227 1>,
 498                                                      <228 1>, <229 1>, <230 1>,
 499                                                      <231 1>, <232 1>, <233 1>,
 500                                                      <234 1>, <235 1>;
 501
 502                                         gpio-controller;
 503                                         #gpio-cells = <2>;
 504
 505                                 };
 506
 507                                 pm8921_mpps: mpps@50 {
 508                                         compatible = "qcom,pm8921-mpp",
 509                                                      "qcom,ssbi-mpp";
 510                                         reg = <0x50>;
 511                                         gpio-controller;
 512                                         #gpio-cells = <2>;
 513                                         interrupts =
 514                                         <128 1>, <129 1>, <130 1>, <131 1>,
 515                                         <132 1>, <133 1>, <134 1>, <135 1>,
 516                                         <136 1>, <137 1>, <138 1>, <139 1>;
 517                                 };
 518
 519                                 rtc@11d {
 520                                         compatible = "qcom,pm8921-rtc";
 521                                         interrupt-parent = <&pmicintc>;
 522                                         interrupts = <39 1>;
 523                                         reg = <0x11d>;
 524                                         allow-set-time;
 525                                 };
 526
 527                                 pwrkey@1c {
 528                                         compatible = "qcom,pm8921-pwrkey";
 529                                         reg = <0x1c>;
 530                                         interrupt-parent = <&pmicintc>;
 531                                         interrupts = <50 1>, <51 1>;
 532                                         debounce = <15625>;
 533                                         pull-up;
 534                                 };
 535                         };
 536                 };
 537
 538                 gcc: clock-controller@900000 {
 539                         compatible = "qcom,gcc-apq8064";
 540                         reg = <0x00900000 0x4000>;
 541                         #clock-cells = <1>;
 542                         #reset-cells = <1>;
 543                 };
 544
 545                 lcc: clock-controller@28000000 {
 546                         compatible = "qcom,lcc-apq8064";
 547                         reg = <0x28000000 0x1000>;
 548                         #clock-cells = <1>;
 549                         #reset-cells = <1>;
 550                 };
 551
 552                 mmcc: clock-controller@4000000 {
 553                         compatible = "qcom,mmcc-apq8064";
 554                         reg = <0x4000000 0x1000>;
 555                         #clock-cells = <1>;
 556                         #reset-cells = <1>;
 557                 };
 558
 559                 l2cc: clock-controller@2011000 {
 560                         compatible      = "syscon";
 561                         reg             = <0x2011000 0x1000>;
 562                 };
 563
 564                 rpm@108000 {
 565                         compatible      = "qcom,rpm-apq8064";
 566                         reg             = <0x108000 0x1000>;
 567                         qcom,ipc        = <&l2cc 0x8 2>;
 568
 569                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 570                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 571                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 572                         interrupt-names = "ack", "err", "wakeup";
 573
 574                         rpmcc: clock-controller {
 575                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 576                                 #clock-cells = <1>;
 577                         };
 578
 579                         regulators {
 580                                 compatible = "qcom,rpm-pm8921-regulators";
 581
 582                                 pm8921_s1: s1 {};
 583                                 pm8921_s2: s2 {};
 584                                 pm8921_s3: s3 {};
 585                                 pm8921_s4: s4 {};
 586                                 pm8921_s7: s7 {};
 587                                 pm8921_s8: s8 {};
 588
 589                                 pm8921_l1: l1 {};
 590                                 pm8921_l2: l2 {};
 591                                 pm8921_l3: l3 {};
 592                                 pm8921_l4: l4 {};
 593                                 pm8921_l5: l5 {};
 594                                 pm8921_l6: l6 {};
 595                                 pm8921_l7: l7 {};
 596                                 pm8921_l8: l8 {};
 597                                 pm8921_l9: l9 {};
 598                                 pm8921_l10: l10 {};
 599                                 pm8921_l11: l11 {};
 600                                 pm8921_l12: l12 {};
 601                                 pm8921_l14: l14 {};
 602                                 pm8921_l15: l15 {};
 603                                 pm8921_l16: l16 {};
 604                                 pm8921_l17: l17 {};
 605                                 pm8921_l18: l18 {};
 606                                 pm8921_l21: l21 {};
 607                                 pm8921_l22: l22 {};
 608                                 pm8921_l23: l23 {};
 609                                 pm8921_l24: l24 {};
 610                                 pm8921_l25: l25 {};
 611                                 pm8921_l26: l26 {};
 612                                 pm8921_l27: l27 {};
 613                                 pm8921_l28: l28 {};
 614                                 pm8921_l29: l29 {};
 615
 616                                 pm8921_lvs1: lvs1 {};
 617                                 pm8921_lvs2: lvs2 {};
 618                                 pm8921_lvs3: lvs3 {};
 619                                 pm8921_lvs4: lvs4 {};
 620                                 pm8921_lvs5: lvs5 {};
 621                                 pm8921_lvs6: lvs6 {};
 622                                 pm8921_lvs7: lvs7 {};
 623
 624                                 pm8921_usb_switch: usb-switch {};
 625
 626                                 pm8921_hdmi_switch: hdmi-switch {
 627                                         bias-pull-down;
 628                                 };
 629
 630                                 pm8921_ncp: ncp {};
 631                         };
 632                 };
 633
 634                 usb1_phy: phy@12500000 {
 635                         compatible      = "qcom,usb-otg-ci";
 636                         reg             = <0x12500000 0x400>;
 637                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 638                         status          = "disabled";
 639                         dr_mode         = "host";
 640
 641                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 642                                           <&gcc USB_HS1_H_CLK>;
 643                         clock-names     = "core", "iface";
 644
 645                         resets          = <&gcc USB_HS1_RESET>;
 646                         reset-names     = "link";
 647                 };
 648
 649                 usb3_phy: phy@12520000 {
 650                         compatible      = "qcom,usb-otg-ci";
 651                         reg             = <0x12520000 0x400>;
 652                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 653                         status          = "disabled";
 654                         dr_mode         = "host";
 655
 656                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 657                                           <&gcc USB_HS3_H_CLK>;
 658                         clock-names     = "core", "iface";
 659
 660                         resets          = <&gcc USB_HS3_RESET>;
 661                         reset-names     = "link";
 662                 };
 663
 664                 usb4_phy: phy@12530000 {
 665                         compatible      = "qcom,usb-otg-ci";
 666                         reg             = <0x12530000 0x400>;
 667                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 668                         status          = "disabled";
 669                         dr_mode         = "host";
 670
 671                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 672                                           <&gcc USB_HS4_H_CLK>;
 673                         clock-names     = "core", "iface";
 674
 675                         resets          = <&gcc USB_HS4_RESET>;
 676                         reset-names     = "link";
 677                 };
 678
 679                 gadget1: gadget@12500000 {
 680                         compatible      = "qcom,ci-hdrc";
 681                         reg             = <0x12500000 0x400>;
 682                         status          = "disabled";
 683                         dr_mode         = "peripheral";
 684                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 685                         usb-phy         = <&usb1_phy>;
 686                 };
 687
 688                 usb1: usb@12500000 {
 689                         compatible      = "qcom,ehci-host";
 690                         reg             = <0x12500000 0x400>;
 691                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 692                         status          = "disabled";
 693                         usb-phy         = <&usb1_phy>;
 694                 };
 695
 696                 usb3: usb@12520000 {
 697                         compatible      = "qcom,ehci-host";
 698                         reg             = <0x12520000 0x400>;
 699                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 700                         status          = "disabled";
 701                         usb-phy         = <&usb3_phy>;
 702                 };
 703
 704                 usb4: usb@12530000 {
 705                         compatible      = "qcom,ehci-host";
 706                         reg             = <0x12530000 0x400>;
 707                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 708                         status          = "disabled";
 709                         usb-phy         = <&usb4_phy>;
 710                 };
 711
 712                 sata_phy0: phy@1b400000 {
 713                         compatible      = "qcom,apq8064-sata-phy";
 714                         status          = "disabled";
 715                         reg             = <0x1b400000 0x200>;
 716                         reg-names       = "phy_mem";
 717                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 718                         clock-names     = "cfg";
 719                         #phy-cells      = <0>;
 720                 };
 721
 722                 sata0: sata@29000000 {
 723                         compatible              = "generic-ahci";
 724                         status                  = "disabled";
 725                         reg                     = <0x29000000 0x180>;
 726                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 727
 728                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 729                                                 <&gcc SATA_H_CLK>,
 730                                                 <&gcc SATA_A_CLK>,
 731                                                 <&gcc SATA_RXOOB_CLK>,
 732                                                 <&gcc SATA_PMALIVE_CLK>;
 733                         clock-names             = "slave_iface",
 734                                                 "iface",
 735                                                 "bus",
 736                                                 "rxoob",
 737                                                 "core_pmalive";
 738
 739                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 740                                                 <&gcc SATA_PMALIVE_CLK>;
 741                         assigned-clock-rates    = <100000000>, <100000000>;
 742
 743                         phys                    = <&sata_phy0>;
 744                         phy-names               = "sata-phy";
 745                 };
 746
 747                 /* Temporary fixed regulator */
 748                 sdcc1bam:dma@12402000{
 749                         compatible = "qcom,bam-v1.3.0";
 750                         reg = <0x12402000 0x8000>;
 751                         interrupts = <0 98 0>;
 752                         clocks = <&gcc SDC1_H_CLK>;
 753                         clock-names = "bam_clk";
 754                         #dma-cells = <1>;
 755                         qcom,ee = <0>;
 756                 };
 757
 758                 sdcc3bam:dma@12182000{
 759                         compatible = "qcom,bam-v1.3.0";
 760                         reg = <0x12182000 0x8000>;
 761                         interrupts = <0 96 0>;
 762                         clocks = <&gcc SDC3_H_CLK>;
 763                         clock-names = "bam_clk";
 764                         #dma-cells = <1>;
 765                         qcom,ee = <0>;
 766                 };
 767
 768                 sdcc4bam:dma@121c2000{
 769                         compatible = "qcom,bam-v1.3.0";
 770                         reg = <0x121c2000 0x8000>;
 771                         interrupts = <0 95 0>;
 772                         clocks = <&gcc SDC4_H_CLK>;
 773                         clock-names = "bam_clk";
 774                         #dma-cells = <1>;
 775                         qcom,ee = <0>;
 776                 };
 777
 778                 amba {
 779                         compatible = "simple-bus";
 780                         #address-cells = <1>;
 781                         #size-cells = <1>;
 782                         ranges;
 783                         sdcc1: sdcc@12400000 {
 784                                 status          = "disabled";
 785                                 compatible      = "arm,pl18x", "arm,primecell";
 786                                 arm,primecell-periphid = <0x00051180>;
 787                                 reg             = <0x12400000 0x2000>;
 788                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 789                                 interrupt-names = "cmd_irq";
 790                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 791                                 clock-names     = "mclk", "apb_pclk";
 792                                 bus-width       = <8>;
 793                                 max-frequency   = <96000000>;
 794                                 non-removable;
 795                                 cap-sd-highspeed;
 796                                 cap-mmc-highspeed;
 797                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 798                                 dma-names = "tx", "rx";
 799                         };
 800
 801                         sdcc3: sdcc@12180000 {
 802                                 compatible      = "arm,pl18x", "arm,primecell";
 803                                 arm,primecell-periphid = <0x00051180>;
 804                                 status          = "disabled";
 805                                 reg             = <0x12180000 0x2000>;
 806                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 807                                 interrupt-names = "cmd_irq";
 808                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 809                                 clock-names     = "mclk", "apb_pclk";
 810                                 bus-width       = <4>;
 811                                 cap-sd-highspeed;
 812                                 cap-mmc-highspeed;
 813                                 max-frequency   = <192000000>;
 814                                 no-1-8-v;
 815                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 816                                 dma-names = "tx", "rx";
 817                         };
 818
 819                         sdcc4: sdcc@121c0000 {
 820                                 compatible      = "arm,pl18x", "arm,primecell";
 821                                 arm,primecell-periphid = <0x00051180>;
 822                                 status          = "disabled";
 823                                 reg             = <0x121c0000 0x2000>;
 824                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 825                                 interrupt-names = "cmd_irq";
 826                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 827                                 clock-names     = "mclk", "apb_pclk";
 828                                 bus-width       = <4>;
 829                                 cap-sd-highspeed;
 830                                 cap-mmc-highspeed;
 831                                 max-frequency   = <48000000>;
 832                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 833                                 dma-names = "tx", "rx";
 834                                 pinctrl-names = "default";
 835                                 pinctrl-0 = <&sdc4_gpios>;
 836                         };
 837                 };
 838
 839                 tcsr: syscon@1a400000 {
 840                         compatible = "qcom,tcsr-apq8064", "syscon";
 841                         reg = <0x1a400000 0x100>;
 842                 };
 843
 844                 pcie: pci@1b500000 {
 845                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 846                         reg = <0x1b500000 0x1000
 847                                0x1b502000 0x80
 848                                0x1b600000 0x100
 849                                0x0ff00000 0x100000>;
 850                         reg-names = "dbi", "elbi", "parf", "config";
 851                         device_type = "pci";
 852                         linux,pci-domain = <0>;
 853                         bus-range = <0x00 0xff>;
 854                         num-lanes = <1>;
 855                         #address-cells = <3>;
 856                         #size-cells = <2>;
 857                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 858                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 859                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 860                         interrupt-names = "msi";
 861                         #interrupt-cells = <1>;
 862                         interrupt-map-mask = <0 0 0 0x7>;
 863                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 864                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 865                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 866                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 867                         clocks = <&gcc PCIE_A_CLK>,
 868                                  <&gcc PCIE_H_CLK>,
 869                                  <&gcc PCIE_PHY_REF_CLK>;
 870                         clock-names = "core", "iface", "phy";
 871                         resets = <&gcc PCIE_ACLK_RESET>,
 872                                  <&gcc PCIE_HCLK_RESET>,
 873                                  <&gcc PCIE_POR_RESET>,
 874                                  <&gcc PCIE_PCI_RESET>,
 875                                  <&gcc PCIE_PHY_RESET>;
 876                         reset-names = "axi", "ahb", "por", "pci", "phy";
 877                         status = "disabled";
 878                 };
 879         };
 880 };
 881 #include "qcom-apq8064-pins.dtsi"