3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 model = "Qualcomm APQ8064";
13 compatible = "qcom,apq8064";
14 interrupt-parent = <&intc>;
21 smem_region: smem@80000000 {
22 reg = <0x80000000 0x200000>;
32 compatible = "qcom,krait";
33 enable-method = "qcom,kpss-acc-v1";
36 next-level-cache = <&L2>;
39 cpu-idle-states = <&CPU_SPC>;
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
47 next-level-cache = <&L2>;
50 cpu-idle-states = <&CPU_SPC>;
54 compatible = "qcom,krait";
55 enable-method = "qcom,kpss-acc-v1";
58 next-level-cache = <&L2>;
61 cpu-idle-states = <&CPU_SPC>;
65 compatible = "qcom,krait";
66 enable-method = "qcom,kpss-acc-v1";
69 next-level-cache = <&L2>;
72 cpu-idle-states = <&CPU_SPC>;
82 compatible = "qcom,idle-state-spc",
84 entry-latency-us = <400>;
85 exit-latency-us = <900>;
86 min-residency-us = <3000>;
93 polling-delay-passive = <250>;
94 polling-delay = <1000>;
96 thermal-sensors = <&gcc 7>;
97 coefficients = <1199 0>;
101 temperature = <75000>;
106 temperature = <110000>;
114 polling-delay-passive = <250>;
115 polling-delay = <1000>;
117 thermal-sensors = <&gcc 8>;
118 coefficients = <1132 0>;
122 temperature = <75000>;
127 temperature = <110000>;
135 polling-delay-passive = <250>;
136 polling-delay = <1000>;
138 thermal-sensors = <&gcc 9>;
139 coefficients = <1199 0>;
143 temperature = <75000>;
148 temperature = <110000>;
156 polling-delay-passive = <250>;
157 polling-delay = <1000>;
159 thermal-sensors = <&gcc 10>;
160 coefficients = <1132 0>;
164 temperature = <75000>;
169 temperature = <110000>;
178 compatible = "qcom,krait-pmu";
179 interrupts = <1 10 0x304>;
184 compatible = "fixed-clock";
186 clock-frequency = <19200000>;
190 compatible = "fixed-clock";
192 clock-frequency = <27000000>;
196 compatible = "fixed-clock";
198 clock-frequency = <32768>;
202 sfpb_mutex: hwmutex {
203 compatible = "qcom,sfpb-mutex";
204 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
209 compatible = "qcom,smem";
210 memory-region = <&smem_region>;
212 hwlocks = <&sfpb_mutex 3>;
216 compatible = "qcom,smd";
219 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
221 qcom,ipc = <&l2cc 8 3>;
228 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
230 qcom,ipc = <&l2cc 8 15>;
237 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
239 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
246 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
248 qcom,ipc = <&l2cc 8 25>;
256 compatible = "qcom,smsm";
258 #address-cells = <1>;
261 qcom,ipc-1 = <&l2cc 8 4>;
262 qcom,ipc-2 = <&l2cc 8 14>;
263 qcom,ipc-3 = <&l2cc 8 23>;
264 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
268 #qcom,smem-state-cells = <1>;
271 modem_smsm: modem@1 {
273 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
281 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
287 wcnss_smsm: wcnss@3 {
289 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
297 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
306 compatible = "qcom,scm-apq8064";
308 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
309 clock-names = "core";
314 #address-cells = <1>;
317 compatible = "simple-bus";
319 tlmm_pinmux: pinctrl@800000 {
320 compatible = "qcom,apq8064-pinctrl";
321 reg = <0x800000 0x4000>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&ps_hold>;
333 sfpb_wrapper_mutex: syscon@1200000 {
334 compatible = "syscon";
335 reg = <0x01200000 0x8000>;
338 intc: interrupt-controller@2000000 {
339 compatible = "qcom,msm-qgic2";
340 interrupt-controller;
341 #interrupt-cells = <3>;
342 reg = <0x02000000 0x1000>,
347 compatible = "qcom,kpss-timer",
348 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
349 interrupts = <1 1 0x301>,
352 reg = <0x0200a000 0x100>;
353 clock-frequency = <27000000>,
355 cpu-offset = <0x80000>;
358 acc0: clock-controller@2088000 {
359 compatible = "qcom,kpss-acc-v1";
360 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
363 acc1: clock-controller@2098000 {
364 compatible = "qcom,kpss-acc-v1";
365 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
368 acc2: clock-controller@20a8000 {
369 compatible = "qcom,kpss-acc-v1";
370 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
373 acc3: clock-controller@20b8000 {
374 compatible = "qcom,kpss-acc-v1";
375 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
378 saw0: power-controller@2089000 {
379 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
380 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
384 saw1: power-controller@2099000 {
385 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
386 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
390 saw2: power-controller@20a9000 {
391 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
392 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
396 saw3: power-controller@20b9000 {
397 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
398 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
402 sps_sic_non_secure: sps-sic-non-secure@12100000 {
403 compatible = "syscon";
404 reg = <0x12100000 0x10000>;
407 gsbi1: gsbi@12440000 {
409 compatible = "qcom,gsbi-v1.0.0";
411 reg = <0x12440000 0x100>;
412 clocks = <&gcc GSBI1_H_CLK>;
413 clock-names = "iface";
414 #address-cells = <1>;
418 syscon-tcsr = <&tcsr>;
420 gsbi1_serial: serial@12450000 {
421 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
422 reg = <0x12450000 0x100>,
424 interrupts = <0 193 0x0>;
425 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
426 clock-names = "core", "iface";
430 gsbi1_i2c: i2c@12460000 {
431 compatible = "qcom,i2c-qup-v1.1.1";
432 pinctrl-0 = <&i2c1_pins>;
433 pinctrl-1 = <&i2c1_pins_sleep>;
434 pinctrl-names = "default", "sleep";
435 reg = <0x12460000 0x1000>;
436 interrupts = <0 194 IRQ_TYPE_NONE>;
437 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
438 clock-names = "core", "iface";
439 #address-cells = <1>;
445 gsbi2: gsbi@12480000 {
447 compatible = "qcom,gsbi-v1.0.0";
449 reg = <0x12480000 0x100>;
450 clocks = <&gcc GSBI2_H_CLK>;
451 clock-names = "iface";
452 #address-cells = <1>;
456 syscon-tcsr = <&tcsr>;
458 gsbi2_i2c: i2c@124a0000 {
459 compatible = "qcom,i2c-qup-v1.1.1";
460 reg = <0x124a0000 0x1000>;
461 pinctrl-0 = <&i2c2_pins>;
462 pinctrl-1 = <&i2c2_pins_sleep>;
463 pinctrl-names = "default", "sleep";
464 interrupts = <0 196 IRQ_TYPE_NONE>;
465 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
466 clock-names = "core", "iface";
467 #address-cells = <1>;
472 gsbi3: gsbi@16200000 {
474 compatible = "qcom,gsbi-v1.0.0";
476 reg = <0x16200000 0x100>;
477 clocks = <&gcc GSBI3_H_CLK>;
478 clock-names = "iface";
479 #address-cells = <1>;
482 gsbi3_i2c: i2c@16280000 {
483 compatible = "qcom,i2c-qup-v1.1.1";
484 pinctrl-0 = <&i2c3_pins>;
485 pinctrl-1 = <&i2c3_pins_sleep>;
486 pinctrl-names = "default", "sleep";
487 reg = <0x16280000 0x1000>;
488 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
489 clocks = <&gcc GSBI3_QUP_CLK>,
491 clock-names = "core", "iface";
492 #address-cells = <1>;
497 gsbi4: gsbi@16300000 {
499 compatible = "qcom,gsbi-v1.0.0";
501 reg = <0x16300000 0x03>;
502 clocks = <&gcc GSBI4_H_CLK>;
503 clock-names = "iface";
504 #address-cells = <1>;
508 gsbi4_i2c: i2c@16380000 {
509 compatible = "qcom,i2c-qup-v1.1.1";
510 pinctrl-0 = <&i2c4_pins>;
511 pinctrl-1 = <&i2c4_pins_sleep>;
512 pinctrl-names = "default", "sleep";
513 reg = <0x16380000 0x1000>;
514 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
515 clocks = <&gcc GSBI4_QUP_CLK>,
517 clock-names = "core", "iface";
521 gsbi5: gsbi@1a200000 {
523 compatible = "qcom,gsbi-v1.0.0";
525 reg = <0x1a200000 0x03>;
526 clocks = <&gcc GSBI5_H_CLK>;
527 clock-names = "iface";
528 #address-cells = <1>;
532 gsbi5_serial: serial@1a240000 {
533 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
534 reg = <0x1a240000 0x100>,
536 interrupts = <0 154 0x0>;
537 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
538 clock-names = "core", "iface";
542 gsbi5_spi: spi@1a280000 {
543 compatible = "qcom,spi-qup-v1.1.1";
544 reg = <0x1a280000 0x1000>;
545 interrupts = <0 155 0>;
546 pinctrl-0 = <&spi5_default>;
547 pinctrl-1 = <&spi5_sleep>;
548 pinctrl-names = "default", "sleep";
549 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
550 clock-names = "core", "iface";
552 #address-cells = <1>;
557 gsbi6: gsbi@16500000 {
559 compatible = "qcom,gsbi-v1.0.0";
561 reg = <0x16500000 0x03>;
562 clocks = <&gcc GSBI6_H_CLK>;
563 clock-names = "iface";
564 #address-cells = <1>;
568 gsbi6_serial: serial@16540000 {
569 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
570 reg = <0x16540000 0x100>,
572 interrupts = <0 156 0x0>;
573 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
574 clock-names = "core", "iface";
578 gsbi6_i2c: i2c@16580000 {
579 compatible = "qcom,i2c-qup-v1.1.1";
580 pinctrl-0 = <&i2c6_pins>;
581 pinctrl-1 = <&i2c6_pins_sleep>;
582 pinctrl-names = "default", "sleep";
583 reg = <0x16580000 0x1000>;
584 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
585 clocks = <&gcc GSBI6_QUP_CLK>,
587 clock-names = "core", "iface";
591 gsbi7: gsbi@16600000 {
593 compatible = "qcom,gsbi-v1.0.0";
595 reg = <0x16600000 0x100>;
596 clocks = <&gcc GSBI7_H_CLK>;
597 clock-names = "iface";
598 #address-cells = <1>;
601 syscon-tcsr = <&tcsr>;
603 gsbi7_serial: serial@16640000 {
604 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
605 reg = <0x16640000 0x1000>,
607 interrupts = <0 158 0x0>;
608 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
609 clock-names = "core", "iface";
613 gsbi7_i2c: i2c@16680000 {
614 compatible = "qcom,i2c-qup-v1.1.1";
615 pinctrl-0 = <&i2c7_pins>;
616 pinctrl-1 = <&i2c7_pins_sleep>;
617 pinctrl-names = "default", "sleep";
618 reg = <0x16680000 0x1000>;
619 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
620 clocks = <&gcc GSBI7_QUP_CLK>,
622 clock-names = "core", "iface";
628 compatible = "qcom,prng";
629 reg = <0x1a500000 0x200>;
630 clocks = <&gcc PRNG_CLK>;
631 clock-names = "core";
635 compatible = "qcom,ssbi";
636 reg = <0x00500000 0x1000>;
637 qcom,controller-type = "pmic-arbiter";
640 compatible = "qcom,pm8921";
641 interrupt-parent = <&tlmm_pinmux>;
643 #interrupt-cells = <2>;
644 interrupt-controller;
645 #address-cells = <1>;
648 pm8921_gpio: gpio@150 {
650 compatible = "qcom,pm8921-gpio",
653 interrupts = <192 IRQ_TYPE_NONE>,
702 pm8921_mpps: mpps@50 {
703 compatible = "qcom,pm8921-mpp",
724 compatible = "qcom,pm8921-rtc";
725 interrupt-parent = <&pmicintc>;
732 compatible = "qcom,pm8921-pwrkey";
734 interrupt-parent = <&pmicintc>;
735 interrupts = <50 1>, <51 1>;
742 qfprom: qfprom@700000 {
743 compatible = "qcom,qfprom";
744 reg = <0x00700000 0x1000>;
745 #address-cells = <1>;
751 tsens_backup: backup_calib {
756 gcc: clock-controller@900000 {
757 compatible = "qcom,gcc-apq8064";
758 reg = <0x00900000 0x4000>;
759 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
760 nvmem-cell-names = "calib", "calib_backup";
763 #thermal-sensor-cells = <1>;
766 lcc: clock-controller@28000000 {
767 compatible = "qcom,lcc-apq8064";
768 reg = <0x28000000 0x1000>;
773 mmcc: clock-controller@4000000 {
774 compatible = "qcom,mmcc-apq8064";
775 reg = <0x4000000 0x1000>;
780 l2cc: clock-controller@2011000 {
781 compatible = "syscon";
782 reg = <0x2011000 0x1000>;
786 compatible = "qcom,rpm-apq8064";
787 reg = <0x108000 0x1000>;
788 qcom,ipc = <&l2cc 0x8 2>;
790 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
791 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
792 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
793 interrupt-names = "ack", "err", "wakeup";
795 rpmcc: clock-controller {
796 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
801 compatible = "qcom,rpm-pm8921-regulators";
837 pm8921_lvs1: lvs1 {};
838 pm8921_lvs2: lvs2 {};
839 pm8921_lvs3: lvs3 {};
840 pm8921_lvs4: lvs4 {};
841 pm8921_lvs5: lvs5 {};
842 pm8921_lvs6: lvs6 {};
843 pm8921_lvs7: lvs7 {};
845 pm8921_usb_switch: usb-switch {};
847 pm8921_hdmi_switch: hdmi-switch {
855 usb1_phy: phy@12500000 {
856 compatible = "qcom,usb-otg-ci";
857 reg = <0x12500000 0x400>;
858 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
861 clocks = <&gcc USB_HS1_XCVR_CLK>,
862 <&gcc USB_HS1_H_CLK>;
863 clock-names = "core", "iface";
865 resets = <&gcc USB_HS1_RESET>;
866 reset-names = "link";
869 usb3_phy: phy@12520000 {
870 compatible = "qcom,usb-otg-ci";
871 reg = <0x12520000 0x400>;
872 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
876 clocks = <&gcc USB_HS3_XCVR_CLK>,
877 <&gcc USB_HS3_H_CLK>;
878 clock-names = "core", "iface";
880 resets = <&gcc USB_HS3_RESET>;
881 reset-names = "link";
884 usb4_phy: phy@12530000 {
885 compatible = "qcom,usb-otg-ci";
886 reg = <0x12530000 0x400>;
887 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
891 clocks = <&gcc USB_HS4_XCVR_CLK>,
892 <&gcc USB_HS4_H_CLK>;
893 clock-names = "core", "iface";
895 resets = <&gcc USB_HS4_RESET>;
896 reset-names = "link";
899 gadget1: gadget@12500000 {
900 compatible = "qcom,ci-hdrc";
901 reg = <0x12500000 0x400>;
903 dr_mode = "peripheral";
904 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
905 usb-phy = <&usb1_phy>;
909 compatible = "qcom,ehci-host";
910 reg = <0x12500000 0x400>;
911 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
913 usb-phy = <&usb1_phy>;
917 compatible = "qcom,ehci-host";
918 reg = <0x12520000 0x400>;
919 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
921 usb-phy = <&usb3_phy>;
925 compatible = "qcom,ehci-host";
926 reg = <0x12530000 0x400>;
927 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
929 usb-phy = <&usb4_phy>;
932 sata_phy0: phy@1b400000 {
933 compatible = "qcom,apq8064-sata-phy";
935 reg = <0x1b400000 0x200>;
936 reg-names = "phy_mem";
937 clocks = <&gcc SATA_PHY_CFG_CLK>;
942 sata0: sata@29000000 {
943 compatible = "qcom,apq8064-ahci", "generic-ahci";
945 reg = <0x29000000 0x180>;
946 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
948 clocks = <&gcc SFAB_SATA_S_H_CLK>,
951 <&gcc SATA_RXOOB_CLK>,
952 <&gcc SATA_PMALIVE_CLK>;
953 clock-names = "slave_iface",
959 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
960 <&gcc SATA_PMALIVE_CLK>;
961 assigned-clock-rates = <100000000>, <100000000>;
964 phy-names = "sata-phy";
965 ports-implemented = <0x1>;
968 /* Temporary fixed regulator */
969 sdcc1bam:dma@12402000{
970 compatible = "qcom,bam-v1.3.0";
971 reg = <0x12402000 0x8000>;
972 interrupts = <0 98 0>;
973 clocks = <&gcc SDC1_H_CLK>;
974 clock-names = "bam_clk";
979 sdcc3bam:dma@12182000{
980 compatible = "qcom,bam-v1.3.0";
981 reg = <0x12182000 0x8000>;
982 interrupts = <0 96 0>;
983 clocks = <&gcc SDC3_H_CLK>;
984 clock-names = "bam_clk";
989 sdcc4bam:dma@121c2000{
990 compatible = "qcom,bam-v1.3.0";
991 reg = <0x121c2000 0x8000>;
992 interrupts = <0 95 0>;
993 clocks = <&gcc SDC4_H_CLK>;
994 clock-names = "bam_clk";
1000 compatible = "simple-bus";
1001 #address-cells = <1>;
1004 sdcc1: sdcc@12400000 {
1005 status = "disabled";
1006 compatible = "arm,pl18x", "arm,primecell";
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&sdcc1_pins>;
1009 arm,primecell-periphid = <0x00051180>;
1010 reg = <0x12400000 0x2000>;
1011 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-names = "cmd_irq";
1013 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1014 clock-names = "mclk", "apb_pclk";
1016 max-frequency = <96000000>;
1020 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1021 dma-names = "tx", "rx";
1024 sdcc3: sdcc@12180000 {
1025 compatible = "arm,pl18x", "arm,primecell";
1026 arm,primecell-periphid = <0x00051180>;
1027 status = "disabled";
1028 reg = <0x12180000 0x2000>;
1029 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1030 interrupt-names = "cmd_irq";
1031 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1032 clock-names = "mclk", "apb_pclk";
1036 max-frequency = <192000000>;
1038 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1039 dma-names = "tx", "rx";
1042 sdcc4: sdcc@121c0000 {
1043 compatible = "arm,pl18x", "arm,primecell";
1044 arm,primecell-periphid = <0x00051180>;
1045 status = "disabled";
1046 reg = <0x121c0000 0x2000>;
1047 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "cmd_irq";
1049 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1050 clock-names = "mclk", "apb_pclk";
1054 max-frequency = <48000000>;
1055 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1056 dma-names = "tx", "rx";
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&sdc4_gpios>;
1062 tcsr: syscon@1a400000 {
1063 compatible = "qcom,tcsr-apq8064", "syscon";
1064 reg = <0x1a400000 0x100>;
1067 gpu: adreno-3xx@4300000 {
1068 compatible = "qcom,adreno-3xx";
1069 reg = <0x04300000 0x20000>;
1070 reg-names = "kgsl_3d0_reg_memory";
1071 interrupts = <GIC_SPI 80 0>;
1072 interrupt-names = "kgsl_3d0_irq";
1080 <&mmcc GFX3D_AHB_CLK>,
1081 <&mmcc GFX3D_AXI_CLK>,
1082 <&mmcc MMSS_IMEM_AHB_CLK>;
1083 qcom,chipid = <0x03020002>;
1150 qcom,gpu-pwrlevels {
1151 compatible = "qcom,gpu-pwrlevels";
1152 qcom,gpu-pwrlevel@0 {
1153 qcom,gpu-freq = <450000000>;
1155 qcom,gpu-pwrlevel@1 {
1156 qcom,gpu-freq = <27000000>;
1161 mmss_sfpb: syscon@5700000 {
1162 compatible = "syscon";
1163 reg = <0x5700000 0x70>;
1166 dsi0: mdss_dsi@4700000 {
1167 compatible = "qcom,mdss-dsi-ctrl";
1168 label = "MDSS DSI CTRL->0";
1169 #address-cells = <1>;
1171 interrupts = <GIC_SPI 82 0>;
1172 reg = <0x04700000 0x200>;
1173 reg-names = "dsi_ctrl";
1175 clocks = <&mmcc DSI_M_AHB_CLK>,
1176 <&mmcc DSI_S_AHB_CLK>,
1177 <&mmcc AMP_AHB_CLK>,
1179 <&mmcc DSI1_BYTE_CLK>,
1180 <&mmcc DSI_PIXEL_CLK>,
1181 <&mmcc DSI1_ESC_CLK>;
1182 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1183 "src_clk", "byte_clk", "pixel_clk",
1186 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1187 <&mmcc DSI1_ESC_SRC>,
1189 <&mmcc DSI_PIXEL_SRC>;
1190 assigned-clock-parents = <&dsi0_phy 0>,
1194 syscon-sfpb = <&mmss_sfpb>;
1197 #address-cells = <1>;
1208 dsi0_out: endpoint {
1215 dsi0_phy: dsi-phy@4700200 {
1216 compatible = "qcom,dsi-phy-28nm-8960";
1219 reg = <0x04700200 0x100>,
1222 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1223 clock-names = "iface_clk";
1224 clocks = <&mmcc DSI_M_AHB_CLK>;
1228 mdp_port0: iommu@7500000 {
1229 compatible = "qcom,apq8064-iommu";
1235 <&mmcc SMMU_AHB_CLK>,
1236 <&mmcc MDP_AXI_CLK>;
1237 reg = <0x07500000 0x100000>;
1244 mdp_port1: iommu@7600000 {
1245 compatible = "qcom,apq8064-iommu";
1251 <&mmcc SMMU_AHB_CLK>,
1252 <&mmcc MDP_AXI_CLK>;
1253 reg = <0x07600000 0x100000>;
1260 gfx3d: iommu@7c00000 {
1261 compatible = "qcom,apq8064-iommu";
1267 <&mmcc SMMU_AHB_CLK>,
1268 <&mmcc GFX3D_AXI_CLK>;
1269 reg = <0x07c00000 0x100000>;
1276 gfx3d1: iommu@7d00000 {
1277 compatible = "qcom,apq8064-iommu";
1283 <&mmcc SMMU_AHB_CLK>,
1284 <&mmcc GFX3D_AXI_CLK>;
1285 reg = <0x07d00000 0x100000>;
1292 pcie: pci@1b500000 {
1293 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1294 reg = <0x1b500000 0x1000
1297 0x0ff00000 0x100000>;
1298 reg-names = "dbi", "elbi", "parf", "config";
1299 device_type = "pci";
1300 linux,pci-domain = <0>;
1301 bus-range = <0x00 0xff>;
1303 #address-cells = <3>;
1305 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1306 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1307 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1308 interrupt-names = "msi";
1309 #interrupt-cells = <1>;
1310 interrupt-map-mask = <0 0 0 0x7>;
1311 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1312 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1313 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1314 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1315 clocks = <&gcc PCIE_A_CLK>,
1317 <&gcc PCIE_PHY_REF_CLK>;
1318 clock-names = "core", "iface", "phy";
1319 resets = <&gcc PCIE_ACLK_RESET>,
1320 <&gcc PCIE_HCLK_RESET>,
1321 <&gcc PCIE_POR_RESET>,
1322 <&gcc PCIE_PCI_RESET>,
1323 <&gcc PCIE_PHY_RESET>;
1324 reset-names = "axi", "ahb", "por", "pci", "phy";
1325 status = "disabled";
1328 hdmi: hdmi-tx@4a00000 {
1329 compatible = "qcom,hdmi-tx-8960";
1330 reg = <0x04a00000 0x2f0>;
1331 reg-names = "core_physical";
1332 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1333 clocks = <&mmcc HDMI_APP_CLK>,
1334 <&mmcc HDMI_M_AHB_CLK>,
1335 <&mmcc HDMI_S_AHB_CLK>;
1336 clock-names = "core_clk",
1341 phy-names = "hdmi-phy";
1344 #address-cells = <1>;
1355 hdmi_out: endpoint {
1361 hdmi_phy: hdmi-phy@4a00400 {
1362 compatible = "qcom,hdmi-phy-8960";
1363 reg = <0x4a00400 0x60>,
1365 reg-names = "hdmi_phy",
1368 clocks = <&mmcc HDMI_S_AHB_CLK>;
1369 clock-names = "slave_iface_clk";
1373 compatible = "qcom,mdp4";
1374 reg = <0x05100000 0xf0000>;
1375 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1376 clocks = <&mmcc MDP_CLK>,
1377 <&mmcc MDP_AHB_CLK>,
1378 <&mmcc MDP_AXI_CLK>,
1379 <&mmcc MDP_LUT_CLK>,
1380 <&mmcc HDMI_TV_CLK>,
1382 clock-names = "core_clk",
1389 iommus = <&mdp_port0 0
1395 #address-cells = <1>;
1400 mdp_lvds_out: endpoint {
1406 mdp_dsi1_out: endpoint {
1412 mdp_dsi2_out: endpoint {
1418 mdp_dtv_out: endpoint {
1425 #include "qcom-apq8064-pins.dtsi"