arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 / {
  11         model = "Qualcomm APQ8064";
  12         compatible = "qcom,apq8064";
  13         interrupt-parent = <&intc>;
  14
  15         reserved-memory {
  16                 #address-cells = <1>;
  17                 #size-cells = <1>;
  18                 ranges;
  19
  20                 smem_region: smem@80000000 {
  21                         reg = <0x80000000 0x200000>;
  22                         no-map;
  23                 };
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 CPU0: cpu@0 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <0>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc0>;
  37                         qcom,saw = <&saw0>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                         clocks = <&kraitcc 0>;
  40                         clock-names = "cpu";
  41                         clock-latency = <100000>;
  42                 };
  43
  44                 CPU1: cpu@1 {
  45                         compatible = "qcom,krait";
  46                         enable-method = "qcom,kpss-acc-v1";
  47                         device_type = "cpu";
  48                         reg = <1>;
  49                         next-level-cache = <&L2>;
  50                         qcom,acc = <&acc1>;
  51                         qcom,saw = <&saw1>;
  52                         cpu-idle-states = <&CPU_SPC>;
  53                         clocks = <&kraitcc 1>;
  54                         clock-names = "cpu";
  55                         clock-latency = <100000>;
  56                 };
  57
  58                 CPU2: cpu@2 {
  59                         compatible = "qcom,krait";
  60                         enable-method = "qcom,kpss-acc-v1";
  61                         device_type = "cpu";
  62                         reg = <2>;
  63                         next-level-cache = <&L2>;
  64                         qcom,acc = <&acc2>;
  65                         qcom,saw = <&saw2>;
  66                         cpu-idle-states = <&CPU_SPC>;
  67                         clocks = <&kraitcc 2>;
  68                         clock-names = "cpu";
  69                         clock-latency = <100000>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         compatible = "qcom,krait";
  74                         enable-method = "qcom,kpss-acc-v1";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                         qcom,acc = <&acc3>;
  79                         qcom,saw = <&saw3>;
  80                         cpu-idle-states = <&CPU_SPC>;
  81                         clocks = <&kraitcc 3>;
  82                         clock-names = "cpu";
  83                         clock-latency = <100000>;
  84                 };
  85
  86                 L2: l2-cache {
  87                         compatible = "cache";
  88                         cache-level = <2>;
  89                 };
  90
  91                 idle-states {
  92                         CPU_SPC: spc {
  93                                 compatible = "qcom,idle-state-spc",
  94                                                 "arm,idle-state";
  95                                 entry-latency-us = <400>;
  96                                 exit-latency-us = <900>;
  97                                 min-residency-us = <3000>;
  98                         };
  99                 };
 100         };
 101
 102         cpu-pmu {
 103                 compatible = "qcom,krait-pmu";
 104                 interrupts = <1 10 0x304>;
 105         };
 106
 107         clocks {
 108                 cxo_board {
 109                         compatible = "fixed-clock";
 110                         #clock-cells = <0>;
 111                         clock-frequency = <19200000>;
 112                 };
 113
 114                 pxo_board {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <27000000>;
 118                 };
 119
 120                 sleep_clk {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <32768>;
 124                 };
 125         };
 126
 127         sfpb_mutex: hwmutex {
 128                 compatible = "qcom,sfpb-mutex";
 129                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 130                 #hwlock-cells = <1>;
 131         };
 132
 133         smem {
 134                 compatible = "qcom,smem";
 135                 memory-region = <&smem_region>;
 136
 137                 hwlocks = <&sfpb_mutex 3>;
 138         };
 139
 140         qcom,pvs {
 141                 qcom,pvs-format-a;
 142                 qcom,speed0-pvs0-bin-v0 =
 143                         < 384000000 950000  >,
 144                         < 486000000 975000  >,
 145                         < 594000000 1000000  >,
 146                         < 702000000 1025000  >,
 147                         < 810000000 1075000  >,
 148                         < 918000000 1100000  >,
 149                         < 1026000000 1125000 >,
 150                         < 1080000000 1175000 >,
 151                         < 1134000000 1175000 >,
 152                         < 1188000000 1200000 >,
 153                         < 1242000000 1200000 >,
 154                         < 1296000000 1225000 >,
 155                         < 1350000000 1225000 >,
 156                         < 1404000000 1237500 >,
 157                         < 1458000000 1237500 >,
 158                         < 1512000000 1250000 >;
 159
 160                 qcom,speed0-pvs1-bin-v0 =
 161                         < 384000000 900000  >,
 162                         < 486000000 925000  >,
 163                         < 594000000 950000  >,
 164                         < 702000000 975000  >,
 165                         < 810000000 1025000  >,
 166                         < 918000000 1050000  >,
 167                         < 1026000000 1075000 >,
 168                         < 1080000000 1125000 >,
 169                         < 1134000000 1125000 >,
 170                         < 1188000000 1150000 >,
 171                         < 1242000000 1150000 >,
 172                         < 1296000000 1175000 >,
 173                         < 1350000000 1175000 >,
 174                         < 1404000000 1187500 >,
 175                         < 1458000000 1187500 >,
 176                         < 1512000000 1200000 >;
 177
 178                 qcom,speed0-pvs3-bin-v0 =
 179                         < 384000000 850000  >,
 180                         < 486000000 875000  >,
 181                         < 594000000 900000  >,
 182                         < 702000000 925000  >,
 183                         < 810000000 975000  >,
 184                         < 918000000 1000000  >,
 185                         < 1026000000 1025000 >,
 186                         < 1080000000 1075000 >,
 187                         < 1134000000 1075000 >,
 188                         < 1188000000 1100000 >,
 189                         < 1242000000 1100000 >,
 190                         < 1296000000 1125000 >,
 191                         < 1350000000 1125000 >,
 192                         < 1404000000 1137500 >,
 193                         < 1458000000 1137500 >,
 194                         < 1512000000 1150000 >;
 195
 196                 qcom,speed0-pvs4-bin-v0 =
 197                         < 384000000 850000  >,
 198                         < 486000000 875000  >,
 199                         < 594000000 900000  >,
 200                         < 702000000 925000  >,
 201                         < 810000000 962500  >,
 202                         < 918000000 975000  >,
 203                         < 1026000000 1000000 >,
 204                         < 1080000000 1050000 >,
 205                         < 1134000000 1050000 >,
 206                         < 1188000000 1075000 >,
 207                         < 1242000000 1075000 >,
 208                         < 1296000000 1100000 >,
 209                         < 1350000000 1100000 >,
 210                         < 1404000000 1112500 >,
 211                         < 1458000000 1112500 >,
 212                         < 1512000000 1125000 >;
 213
 214                 qcom,speed1-pvs0-bin-v0 =
 215                         < 384000000 950000  >,
 216                         < 486000000 950000  >,
 217                         < 594000000 950000  >,
 218                         < 702000000 962500  >,
 219                         < 810000000 1000000  >,
 220                         < 918000000 1025000  >,
 221                         < 1026000000 1037500 >,
 222                         < 1134000000 1075000 >,
 223                         < 1242000000 1087500 >,
 224                         < 1350000000 1125000 >,
 225                         < 1458000000 1150000 >,
 226                         < 1566000000 1175000 >,
 227                         < 1674000000 1225000 >,
 228                         < 1728000000 1250000 >;
 229
 230                 qcom,speed1-pvs1-bin-v0 =
 231                         < 384000000 950000  >,
 232                         < 486000000 950000  >,
 233                         < 594000000 950000  >,
 234                         < 702000000 962500  >,
 235                         < 810000000 975000  >,
 236                         < 918000000 1000000 >,
 237                         < 1026000000 1012500 >,
 238                         < 1134000000 1037500 >,
 239                         < 1242000000 1050000 >,
 240                         < 1350000000 1087500 >,
 241                         < 1458000000 1112500 >,
 242                         < 1566000000 1150000 >,
 243                         < 1674000000 1187500 >,
 244                         < 1728000000 1200000 >;
 245
 246                 qcom,speed1-pvs2-bin-v0 =
 247                         < 384000000 925000  >,
 248                         < 486000000 925000  >,
 249                         < 594000000 925000  >,
 250                         < 702000000 925000  >,
 251                         < 810000000 937500  >,
 252                         < 918000000 950000  >,
 253                         < 1026000000 975000 >,
 254                         < 1134000000 1000000 >,
 255                         < 1242000000 1012500 >,
 256                         < 1350000000 1037500 >,
 257                         < 1458000000 1075000 >,
 258                         < 1566000000 1100000 >,
 259                         < 1674000000 1137500 >,
 260                         < 1728000000 1162500 >;
 261
 262                 qcom,speed1-pvs3-bin-v0 =
 263                         < 384000000 900000  >,
 264                         < 486000000 900000  >,
 265                         < 594000000 900000  >,
 266                         < 702000000 900000  >,
 267                         < 810000000 900000  >,
 268                         < 918000000 925000  >,
 269                         < 1026000000 950000 >,
 270                         < 1134000000 975000 >,
 271                         < 1242000000 987500 >,
 272                         < 1350000000 1000000 >,
 273                         < 1458000000 1037500 >,
 274                         < 1566000000 1062500 >,
 275                         < 1674000000 1100000 >,
 276                         < 1728000000 1125000 >;
 277
 278                 qcom,speed1-pvs4-bin-v0 =
 279                         < 384000000 875000  >,
 280                         < 486000000 875000  >,
 281                         < 594000000 875000  >,
 282                         < 702000000 875000  >,
 283                         < 810000000 887500  >,
 284                         < 918000000 900000  >,
 285                         < 1026000000 925000 >,
 286                         < 1134000000 950000 >,
 287                         < 1242000000 962500 >,
 288                         < 1350000000 975000 >,
 289                         < 1458000000 1000000 >,
 290                         < 1566000000 1037500 >,
 291                         < 1674000000 1075000 >,
 292                         < 1728000000 1100000 >;
 293
 294                 qcom,speed1-pvs5-bin-v0 =
 295                         < 384000000 875000  >,
 296                         < 486000000 875000  >,
 297                         < 594000000 875000  >,
 298                         < 702000000 875000  >,
 299                         < 810000000 887500  >,
 300                         < 918000000 900000  >,
 301                         < 1026000000 925000 >,
 302                         < 1134000000 937500 >,
 303                         < 1242000000 950000 >,
 304                         < 1350000000 962500 >,
 305                         < 1458000000 987500 >,
 306                         < 1566000000 1012500 >,
 307                         < 1674000000 1050000 >,
 308                         < 1728000000 1075000 >;
 309
 310                 qcom,speed1-pvs6-bin-v0 =
 311                         < 384000000 875000  >,
 312                         < 486000000 875000  >,
 313                         < 594000000 875000  >,
 314                         < 702000000 875000  >,
 315                         < 810000000 887500  >,
 316                         < 918000000 900000  >,
 317                         < 1026000000 925000 >,
 318                         < 1134000000 937500 >,
 319                         < 1242000000 950000 >,
 320                         < 1350000000 962500 >,
 321                         < 1458000000 975000 >,
 322                         < 1566000000 1000000 >,
 323                         < 1674000000 1025000 >,
 324                         < 1728000000 1050000 >;
 325
 326                 qcom,speed2-pvs0-bin-v0 =
 327                         < 384000000 950000  >,
 328                         < 486000000 950000  >,
 329                         < 594000000 950000  >,
 330                         < 702000000 950000  >,
 331                         < 810000000 962500  >,
 332                         < 918000000 975000  >,
 333                         < 1026000000 1000000 >,
 334                         < 1134000000 1025000 >,
 335                         < 1242000000 1037500 >,
 336                         < 1350000000 1062500 >,
 337                         < 1458000000 1100000 >,
 338                         < 1566000000 1125000 >,
 339                         < 1674000000 1175000 >,
 340                         < 1782000000 1225000 >,
 341                         < 1890000000 1287500 >;
 342
 343                 qcom,speed2-pvs1-bin-v0 =
 344                         < 384000000 925000  >,
 345                         < 486000000 925000  >,
 346                         < 594000000 925000  >,
 347                         < 702000000 925000  >,
 348                         < 810000000 937500  >,
 349                         < 918000000 950000  >,
 350                         < 1026000000 975000 >,
 351                         < 1134000000 1000000 >,
 352                         < 1242000000 1012500 >,
 353                         < 1350000000 1037500 >,
 354                         < 1458000000 1075000 >,
 355                         < 1566000000 1100000 >,
 356                         < 1674000000 1137500 >,
 357                         < 1782000000 1187500 >,
 358                         < 1890000000 1250000 >;
 359
 360                 qcom,speed2-pvs2-bin-v0 =
 361                         < 384000000 900000  >,
 362                         < 486000000 900000  >,
 363                         < 594000000 900000  >,
 364                         < 702000000 900000  >,
 365                         < 810000000 912500  >,
 366                         < 918000000 925000  >,
 367                         < 1026000000 950000 >,
 368                         < 1134000000 975000 >,
 369                         < 1242000000 987500 >,
 370                         < 1350000000 1012500 >,
 371                         < 1458000000 1050000 >,
 372                         < 1566000000 1075000 >,
 373                         < 1674000000 1112500 >,
 374                         < 1782000000 1162500 >,
 375                         < 1890000000 1212500 >;
 376
 377                 qcom,speed2-pvs3-bin-v0 =
 378                         < 384000000 900000  >,
 379                         < 486000000 900000  >,
 380                         < 594000000 900000  >,
 381                         < 702000000 900000  >,
 382                         < 810000000 900000  >,
 383                         < 918000000 912500  >,
 384                         < 1026000000 937500 >,
 385                         < 1134000000 962500 >,
 386                         < 1242000000 975000 >,
 387                         < 1350000000 1000000 >,
 388                         < 1458000000 1025000 >,
 389                         < 1566000000 1050000 >,
 390                         < 1674000000 1087500 >,
 391                         < 1782000000 1137500 >,
 392                         < 1890000000 1175000 >;
 393
 394                 qcom,speed2-pvs4-bin-v0 =
 395                         < 384000000 875000  >,
 396                         < 486000000 875000  >,
 397                         < 594000000 875000  >,
 398                         < 702000000 875000  >,
 399                         < 810000000 887500  >,
 400                         < 918000000 900000  >,
 401                         < 1026000000 925000 >,
 402                         < 1134000000 950000 >,
 403                         < 1242000000 962500 >,
 404                         < 1350000000 975000 >,
 405                         < 1458000000 1000000 >,
 406                         < 1566000000 1037500 >,
 407                         < 1674000000 1075000 >,
 408                         < 1782000000 1112500 >,
 409                         < 1890000000 1150000 >;
 410
 411                 qcom,speed2-pvs5-bin-v0 =
 412                         < 384000000 875000  >,
 413                         < 486000000 875000  >,
 414                         < 594000000 875000  >,
 415                         < 702000000 875000  >,
 416                         < 810000000 887500  >,
 417                         < 918000000 900000  >,
 418                         < 1026000000 925000 >,
 419                         < 1134000000 937500 >,
 420                         < 1242000000 950000 >,
 421                         < 1350000000 962500 >,
 422                         < 1458000000 987500 >,
 423                         < 1566000000 1012500 >,
 424                         < 1674000000 1050000 >,
 425                         < 1782000000 1087500 >,
 426                         < 1890000000 1125000 >;
 427
 428                 qcom,speed2-pvs6-bin-v0 =
 429                         < 384000000 875000  >,
 430                         < 486000000 875000  >,
 431                         < 594000000 875000  >,
 432                         < 702000000 875000  >,
 433                         < 810000000 887500  >,
 434                         < 918000000 900000  >,
 435                         < 1026000000 925000 >,
 436                         < 1134000000 937500 >,
 437                         < 1242000000 950000 >,
 438                         < 1350000000 962500 >,
 439                         < 1458000000 975000 >,
 440                         < 1566000000 1000000 >,
 441                         < 1674000000 1025000 >,
 442                         < 1782000000 1062500 >,
 443                         < 1890000000 1100000 >;
 444
 445                 qcom,speed14-pvs0-bin-v0 =
 446                         < 384000000 950000 >,
 447                         < 486000000 950000 >,
 448                         < 594000000 950000 >,
 449                         < 702000000 962500 >,
 450                         < 810000000 1000000 >,
 451                         < 918000000 1025000 >,
 452                         < 1026000000 1037500 >,
 453                         < 1134000000 1075000 >,
 454                         < 1242000000 1087500 >,
 455                         < 1350000000 1125000 >,
 456                         < 1458000000 1150000 >,
 457                         < 1512000000 1162500 >;
 458
 459                 qcom,speed14-pvs1-bin-v0 =
 460                         < 384000000 950000 >,
 461                         < 486000000 950000 >,
 462                         < 594000000 950000 >,
 463                         < 702000000 962500 >,
 464                         < 810000000 975000 >,
 465                         < 918000000 1000000 >,
 466                         < 1026000000 1012500 >,
 467                         < 1134000000 1037500 >,
 468                         < 1242000000 1050000 >,
 469                         < 1350000000 1087500 >,
 470                         < 1458000000 1112500 >,
 471                         < 1512000000 1125000 >;
 472
 473                 qcom,speed14-pvs2-bin-v0 =
 474                         < 384000000 925000 >,
 475                         < 486000000 925000 >,
 476                         < 594000000 925000 >,
 477                         < 702000000 925000 >,
 478                         < 810000000 937500 >,
 479                         < 918000000 950000 >,
 480                         < 1026000000 975000 >,
 481                         < 1134000000 1000000 >,
 482                         < 1242000000 1012500 >,
 483                         < 1350000000 1037500 >,
 484                         < 1458000000 1075000 >,
 485                         < 1512000000 1087500 >;
 486
 487                 qcom,speed14-pvs3-bin-v0 =
 488                         < 384000000 900000 >,
 489                         < 486000000 900000 >,
 490                         < 594000000 900000 >,
 491                         < 702000000 900000 >,
 492                         < 810000000 900000 >,
 493                         < 918000000 925000 >,
 494                         < 1026000000 950000 >,
 495                         < 1134000000 975000 >,
 496                         < 1242000000 987500 >,
 497                         < 1350000000 1000000 >,
 498                         < 1458000000 1037500 >,
 499                         < 1512000000 1050000 >;
 500
 501                 qcom,speed14-pvs4-bin-v0 =
 502                         < 384000000 875000 >,
 503                         < 486000000 875000 >,
 504                         < 594000000 875000 >,
 505                         < 702000000 875000 >,
 506                         < 810000000 887500 >,
 507                         < 918000000 900000 >,
 508                         < 1026000000 925000 >,
 509                         < 1134000000 950000 >,
 510                         < 1242000000 962500 >,
 511                         < 1350000000 975000 >,
 512                         < 1458000000 1000000 >,
 513                         < 1512000000 1012500 >;
 514
 515                 qcom,speed14-pvs5-bin-v0 =
 516                         < 384000000 875000 >,
 517                         < 486000000 875000 >,
 518                         < 594000000 875000 >,
 519                         < 702000000 875000 >,
 520                         < 810000000 887500 >,
 521                         < 918000000 900000 >,
 522                         < 1026000000 925000 >,
 523                         < 1134000000 937500 >,
 524                         < 1242000000 950000 >,
 525                         < 1350000000 962500 >,
 526                         < 1458000000 987500 >,
 527                         < 1512000000 1000000 >;
 528
 529                 qcom,speed14-pvs6-bin-v0 =
 530                         < 384000000 875000 >,
 531                         < 486000000 875000 >,
 532                         < 594000000 875000 >,
 533                         < 702000000 875000 >,
 534                         < 810000000 887500 >,
 535                         < 918000000 900000 >,
 536                         < 1026000000 925000 >,
 537                         < 1134000000 937500 >,
 538                         < 1242000000 950000 >,
 539                         < 1350000000 962500 >,
 540                         < 1458000000 975000 >,
 541                         < 1512000000 987500 >;
 542         };
 543
 544         kraitcc: clock-controller {
 545                 compatible = "qcom,krait-cc-v1";
 546                 #clock-cells = <1>;
 547         };
 548
 549         clocks {
 550                 sleep_clk: sleep_clk {
 551                         compatible = "fixed-clock";
 552                         clock-frequency = <32768>;
 553                         #clock-cells = <0>;
 554                 };
 555         };
 556
 557         soc: soc {
 558                 #address-cells = <1>;
 559                 #size-cells = <1>;
 560                 ranges;
 561                 compatible = "simple-bus";
 562
 563                 tlmm_pinmux: pinctrl@800000 {
 564                         compatible = "qcom,apq8064-pinctrl";
 565                         reg = <0x800000 0x4000>;
 566
 567                         gpio-controller;
 568                         #gpio-cells = <2>;
 569                         interrupt-controller;
 570                         #interrupt-cells = <2>;
 571                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 572
 573                         pinctrl-names = "default";
 574                         pinctrl-0 = <&ps_hold>;
 575
 576                         sdc4_gpios: sdc4-gpios {
 577                                 pios {
 578                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 579                                         function = "sdc4";
 580                                 };
 581                         };
 582
 583                         hdmi_pinctrl: hdmi-pinctrl {
 584                                 mux1 {
 585                                         pins = "gpio69", "gpio70", "gpio71";
 586                                         function = "hdmi";
 587                                         bias-pull-up;
 588                                         drive-strength = <2>;
 589                                 };
 590                                 mux2 {
 591                                         pins = "gpio72";
 592                                         function = "hdmi";
 593                                         bias-pull-down;
 594                                         drive-strength = <16>;
 595                                 };
 596                         };
 597                         ps_hold: ps_hold {
 598                                 mux {
 599                                         pins = "gpio78";
 600                                         function = "ps_hold";
 601                                 };
 602                         };
 603
 604                         i2c1_pins: i2c1 {
 605                                 mux {
 606                                         pins = "gpio20", "gpio21";
 607                                         function = "gsbi1";
 608                                 };
 609                         };
 610
 611                         i2c3_pins: i2c3 {
 612                                 mux {
 613                                         pins = "gpio8", "gpio9";
 614                                         function = "gsbi3";
 615                                 };
 616                         };
 617
 618                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 619                                 mux {
 620                                         pins = "gpio14", "gpio15";
 621                                         function = "gsbi6";
 622                                 };
 623                         };
 624
 625                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 626                                 mux {
 627                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 628                                         function = "gsbi6";
 629                                 };
 630                         };
 631
 632                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 633                                 mux {
 634                                         pins = "gpio82", "gpio83";
 635                                         function = "gsbi7";
 636                                 };
 637                         };
 638
 639                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 640                                 mux {
 641                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 642                                         function = "gsbi7";
 643                                 };
 644                         };
 645                 };
 646
 647                 sfpb_wrapper_mutex: syscon@1200000 {
 648                         compatible = "syscon";
 649                         reg = <0x01200000 0x8000>;
 650                 };
 651
 652                 intc: interrupt-controller@2000000 {
 653                         compatible = "qcom,msm-qgic2";
 654                         interrupt-controller;
 655                         #interrupt-cells = <3>;
 656                         reg = <0x02000000 0x1000>,
 657                               <0x02002000 0x1000>;
 658                 };
 659
 660                 timer@200a000 {
 661                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 662                         interrupts = <1 1 0x301>,
 663                                      <1 2 0x301>,
 664                                      <1 3 0x301>;
 665                         reg = <0x0200a000 0x100>;
 666                         clock-frequency = <27000000>,
 667                                           <32768>;
 668                         cpu-offset = <0x80000>;
 669                 };
 670
 671                 watchdog@208a038 {
 672                         compatible = "qcom,kpss-wdt-apq8064";
 673                         reg = <0x0208a038 0x40>;
 674                         clocks = <&sleep_clk>;
 675                         timeout-sec = <10>;
 676                 };
 677
 678                 acc0: clock-controller@2088000 {
 679                         compatible = "qcom,kpss-acc-v1";
 680                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 681                         clock-output-names = "acpu0_aux";
 682                 };
 683
 684                 acc1: clock-controller@2098000 {
 685                         compatible = "qcom,kpss-acc-v1";
 686                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 687                         clock-output-names = "acpu1_aux";
 688                 };
 689
 690                 acc2: clock-controller@20a8000 {
 691                         compatible = "qcom,kpss-acc-v1";
 692                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 693                         clock-output-names = "acpu2_aux";
 694                 };
 695
 696                 acc3: clock-controller@20b8000 {
 697                         compatible = "qcom,kpss-acc-v1";
 698                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 699                         clock-output-names = "acpu3_aux";
 700                 };
 701
 702                 saw0: power-controller@2089000 {
 703                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 704                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 705                         regulator;
 706                 };
 707
 708                 saw1: power-controller@2099000 {
 709                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 710                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 711                         regulator;
 712                 };
 713
 714                 saw2: power-controller@20a9000 {
 715                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 716                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 717                         regulator;
 718                 };
 719
 720                 saw3: power-controller@20b9000 {
 721                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 722                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 723                         regulator;
 724                 };
 725
 726                 gsbi1: gsbi@12440000 {
 727                         status = "disabled";
 728                         compatible = "qcom,gsbi-v1.0.0";
 729                         cell-index = <1>;
 730                         reg = <0x12440000 0x100>;
 731                         clocks = <&gcc GSBI1_H_CLK>;
 732                         clock-names = "iface";
 733                         #address-cells = <1>;
 734                         #size-cells = <1>;
 735                         ranges;
 736
 737                         syscon-tcsr = <&tcsr>;
 738
 739                         i2c1: i2c@12460000 {
 740                                 compatible = "qcom,i2c-qup-v1.1.1";
 741                                 pinctrl-0 = <&i2c1_pins>;
 742                                 pinctrl-names = "default";
 743                                 reg = <0x12460000 0x1000>;
 744                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 745                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 746                                 clock-names = "core", "iface";
 747                                 #address-cells = <1>;
 748                                 #size-cells = <0>;
 749                         };
 750                 };
 751
 752                 gsbi2: gsbi@12480000 {
 753                         status = "disabled";
 754                         compatible = "qcom,gsbi-v1.0.0";
 755                         cell-index = <2>;
 756                         reg = <0x12480000 0x100>;
 757                         clocks = <&gcc GSBI2_H_CLK>;
 758                         clock-names = "iface";
 759                         #address-cells = <1>;
 760                         #size-cells = <1>;
 761                         ranges;
 762
 763                         syscon-tcsr = <&tcsr>;
 764
 765                         i2c2: i2c@124a0000 {
 766                                 compatible = "qcom,i2c-qup-v1.1.1";
 767                                 reg = <0x124a0000 0x1000>;
 768                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 769                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 770                                 clock-names = "core", "iface";
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773                         };
 774                 };
 775
 776                 gsbi3: gsbi@16200000 {
 777                         status = "disabled";
 778                         compatible = "qcom,gsbi-v1.0.0";
 779                         cell-index = <3>;
 780                         reg = <0x16200000 0x100>;
 781                         clocks = <&gcc GSBI3_H_CLK>;
 782                         clock-names = "iface";
 783                         #address-cells = <1>;
 784                         #size-cells = <1>;
 785                         ranges;
 786                         i2c3: i2c@16280000 {
 787                                 compatible = "qcom,i2c-qup-v1.1.1";
 788                                 pinctrl-0 = <&i2c3_pins>;
 789                                 pinctrl-names = "default";
 790                                 reg = <0x16280000 0x1000>;
 791                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 792                                 clocks = <&gcc GSBI3_QUP_CLK>,
 793                                          <&gcc GSBI3_H_CLK>;
 794                                 clock-names = "core", "iface";
 795                         };
 796                 };
 797
 798                 gsbi5: gsbi@1a200000 {
 799                         status = "disabled";
 800                         compatible = "qcom,gsbi-v1.0.0";
 801                         cell-index = <5>;
 802                         reg = <0x1a200000 0x03>;
 803                         clocks = <&gcc GSBI5_H_CLK>;
 804                         clock-names = "iface";
 805                         #address-cells = <1>;
 806                         #size-cells = <1>;
 807                         ranges;
 808
 809                         gsbi5_serial: serial@1a240000 {
 810                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 811                                 reg = <0x1a240000 0x100>,
 812                                       <0x1a200000 0x03>;
 813                                 interrupts = <0 154 0x0>;
 814                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 815                                 clock-names = "core", "iface";
 816                                 status = "disabled";
 817                         };
 818                 };
 819
 820                 gsbi6: gsbi@16500000 {
 821                         status = "disabled";
 822                         compatible = "qcom,gsbi-v1.0.0";
 823                         cell-index = <6>;
 824                         reg = <0x16500000 0x03>;
 825                         clocks = <&gcc GSBI6_H_CLK>;
 826                         clock-names = "iface";
 827                         #address-cells = <1>;
 828                         #size-cells = <1>;
 829                         ranges;
 830
 831                         gsbi6_serial: serial@16540000 {
 832                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 833                                 reg = <0x16540000 0x100>,
 834                                       <0x16500000 0x03>;
 835                                 interrupts = <0 156 0x0>;
 836                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 837                                 clock-names = "core", "iface";
 838                                 status = "disabled";
 839                         };
 840                 };
 841
 842                 gsbi7: gsbi@16600000 {
 843                         status = "disabled";
 844                         compatible = "qcom,gsbi-v1.0.0";
 845                         cell-index = <7>;
 846                         reg = <0x16600000 0x100>;
 847                         clocks = <&gcc GSBI7_H_CLK>;
 848                         clock-names = "iface";
 849                         #address-cells = <1>;
 850                         #size-cells = <1>;
 851                         ranges;
 852                         syscon-tcsr = <&tcsr>;
 853
 854                         gsbi7_serial: serial@16640000 {
 855                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 856                                 reg = <0x16640000 0x1000>,
 857                                       <0x16600000 0x1000>;
 858                                 interrupts = <0 158 0x0>;
 859                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 860                                 clock-names = "core", "iface";
 861                                 status = "disabled";
 862                         };
 863                 };
 864
 865                 rng@1a500000 {
 866                         compatible = "qcom,prng";
 867                         reg = <0x1a500000 0x200>;
 868                         clocks = <&gcc PRNG_CLK>;
 869                         clock-names = "core";
 870                 };
 871
 872                 qcom,ssbi@500000 {
 873                         compatible = "qcom,ssbi";
 874                         reg = <0x00500000 0x1000>;
 875                         qcom,controller-type = "pmic-arbiter";
 876
 877                         pmicintc: pmic@0 {
 878                                 compatible = "qcom,pm8921";
 879                                 interrupt-parent = <&tlmm_pinmux>;
 880                                 interrupts = <74 8>;
 881                                 #interrupt-cells = <2>;
 882                                 interrupt-controller;
 883                                 #address-cells = <1>;
 884                                 #size-cells = <0>;
 885
 886                                 pm8921_gpio: gpio@150 {
 887
 888                                         compatible = "qcom,pm8921-gpio",
 889                                                      "qcom,ssbi-gpio";
 890                                         reg = <0x150>;
 891                                         interrupts = <192 1>, <193 1>, <194 1>,
 892                                                      <195 1>, <196 1>, <197 1>,
 893                                                      <198 1>, <199 1>, <200 1>,
 894                                                      <201 1>, <202 1>, <203 1>,
 895                                                      <204 1>, <205 1>, <206 1>,
 896                                                      <207 1>, <208 1>, <209 1>,
 897                                                      <210 1>, <211 1>, <212 1>,
 898                                                      <213 1>, <214 1>, <215 1>,
 899                                                      <216 1>, <217 1>, <218 1>,
 900                                                      <219 1>, <220 1>, <221 1>,
 901                                                      <222 1>, <223 1>, <224 1>,
 902                                                      <225 1>, <226 1>, <227 1>,
 903                                                      <228 1>, <229 1>, <230 1>,
 904                                                      <231 1>, <232 1>, <233 1>,
 905                                                      <234 1>, <235 1>;
 906
 907                                         gpio-controller;
 908                                         #gpio-cells = <2>;
 909
 910                                 };
 911
 912                                 pm8921_mpps: mpps@50 {
 913                                         compatible = "qcom,pm8921-mpp",
 914                                                      "qcom,ssbi-mpp";
 915                                         reg = <0x50>;
 916                                         gpio-controller;
 917                                         #gpio-cells = <2>;
 918                                         interrupts =
 919                                         <128 1>, <129 1>, <130 1>, <131 1>,
 920                                         <132 1>, <133 1>, <134 1>, <135 1>,
 921                                         <136 1>, <137 1>, <138 1>, <139 1>;
 922                                 };
 923
 924                                 rtc@11d {
 925                                         compatible = "qcom,pm8921-rtc";
 926                                         interrupt-parent = <&pmicintc>;
 927                                         interrupts = <39 1>;
 928                                         reg = <0x11d>;
 929                                         allow-set-time;
 930                                 };
 931
 932                                 pwrkey@1c {
 933                                         compatible = "qcom,pm8921-pwrkey";
 934                                         reg = <0x1c>;
 935                                         interrupt-parent = <&pmicintc>;
 936                                         interrupts = <50 1>, <51 1>;
 937                                         debounce = <15625>;
 938                                         pull-up;
 939                                 };
 940                         };
 941                 };
 942
 943                 gcc: clock-controller@900000 {
 944                         compatible = "qcom,gcc-apq8064";
 945                         reg = <0x00900000 0x4000>;
 946                         #clock-cells = <1>;
 947                         #reset-cells = <1>;
 948                 };
 949
 950                 lcc: clock-controller@28000000 {
 951                         compatible = "qcom,lcc-apq8064";
 952                         reg = <0x28000000 0x1000>;
 953                         #clock-cells = <1>;
 954                         #reset-cells = <1>;
 955                 };
 956
 957                 mmcc: clock-controller@4000000 {
 958                         compatible = "qcom,mmcc-apq8064";
 959                         reg = <0x4000000 0x1000>;
 960                         #clock-cells = <1>;
 961                         #reset-cells = <1>;
 962                 };
 963
 964                 l2cc: clock-controller@2011000 {
 965                         compatible      = "syscon";
 966                         reg             = <0x2011000 0x1000>;
 967                 };
 968
 969                 rpm@108000 {
 970                         compatible      = "qcom,rpm-apq8064";
 971                         reg             = <0x108000 0x1000>;
 972                         qcom,ipc        = <&l2cc 0x8 2>;
 973
 974                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 975                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 976                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 977                         interrupt-names = "ack", "err", "wakeup";
 978
 979                         regulators {
 980                                 compatible = "qcom,rpm-pm8921-regulators";
 981
 982                                 pm8921_s1: s1 {};
 983                                 pm8921_s2: s2 {};
 984                                 pm8921_s3: s3 {};
 985                                 pm8921_s4: s4 {};
 986                                 pm8921_s7: s7 {};
 987                                 pm8921_s8: s8 {};
 988
 989                                 pm8921_l1: l1 {};
 990                                 pm8921_l2: l2 {};
 991                                 pm8921_l3: l3 {};
 992                                 pm8921_l4: l4 {};
 993                                 pm8921_l5: l5 {};
 994                                 pm8921_l6: l6 {};
 995                                 pm8921_l7: l7 {};
 996                                 pm8921_l8: l8 {};
 997                                 pm8921_l9: l9 {};
 998                                 pm8921_l10: l10 {};
 999                                 pm8921_l11: l11 {};
1000                                 pm8921_l12: l12 {};
1001                                 pm8921_l14: l14 {};
1002                                 pm8921_l15: l15 {};
1003                                 pm8921_l16: l16 {};
1004                                 pm8921_l17: l17 {};
1005                                 pm8921_l18: l18 {};
1006                                 pm8921_l21: l21 {};
1007                                 pm8921_l22: l22 {};
1008                                 pm8921_l23: l23 {};
1009                                 pm8921_l24: l24 {};
1010                                 pm8921_l25: l25 {};
1011                                 pm8921_l26: l26 {};
1012                                 pm8921_l27: l27 {};
1013                                 pm8921_l28: l28 {};
1014                                 pm8921_l29: l29 {};
1015
1016                                 pm8921_lvs1: lvs1 {};
1017                                 pm8921_lvs2: lvs2 {};
1018                                 pm8921_lvs3: lvs3 {};
1019                                 pm8921_lvs4: lvs4 {};
1020                                 pm8921_lvs5: lvs5 {};
1021                                 pm8921_lvs6: lvs6 {};
1022                                 pm8921_lvs7: lvs7 {};
1023
1024                                 pm8921_usb_switch: usb-switch {};
1025
1026                                 pm8921_hdmi_switch: hdmi-switch {
1027                                         bias-pull-down;
1028                                 };
1029
1030                                 pm8921_ncp: ncp {};
1031                         };
1032                 };
1033
1034                 usb1_phy: phy@12500000 {
1035                         compatible      = "qcom,usb-otg-ci";
1036                         reg             = <0x12500000 0x400>;
1037                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1038                         status          = "disabled";
1039                         dr_mode         = "host";
1040
1041                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
1042                                           <&gcc USB_HS1_H_CLK>;
1043                         clock-names     = "core", "iface";
1044
1045                         resets          = <&gcc USB_HS1_RESET>;
1046                         reset-names     = "link";
1047                 };
1048
1049                 usb3_phy: phy@12520000 {
1050                         compatible      = "qcom,usb-otg-ci";
1051                         reg             = <0x12520000 0x400>;
1052                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1053                         status          = "disabled";
1054                         dr_mode         = "host";
1055
1056                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
1057                                           <&gcc USB_HS3_H_CLK>;
1058                         clock-names     = "core", "iface";
1059
1060                         resets          = <&gcc USB_HS3_RESET>;
1061                         reset-names     = "link";
1062                 };
1063
1064                 usb4_phy: phy@12530000 {
1065                         compatible      = "qcom,usb-otg-ci";
1066                         reg             = <0x12530000 0x400>;
1067                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1068                         status          = "disabled";
1069                         dr_mode         = "host";
1070
1071                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
1072                                           <&gcc USB_HS4_H_CLK>;
1073                         clock-names     = "core", "iface";
1074
1075                         resets          = <&gcc USB_HS4_RESET>;
1076                         reset-names     = "link";
1077                 };
1078
1079                 gadget1: gadget@12500000 {
1080                         compatible      = "qcom,ci-hdrc";
1081                         reg             = <0x12500000 0x400>;
1082                         status          = "disabled";
1083                         dr_mode         = "peripheral";
1084                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1085                         usb-phy         = <&usb1_phy>;
1086                 };
1087
1088                 usb1: usb@12500000 {
1089                         compatible      = "qcom,ehci-host";
1090                         reg             = <0x12500000 0x400>;
1091                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1092                         status          = "disabled";
1093                         usb-phy         = <&usb1_phy>;
1094                 };
1095
1096                 usb3: usb@12520000 {
1097                         compatible      = "qcom,ehci-host";
1098                         reg             = <0x12520000 0x400>;
1099                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1100                         status          = "disabled";
1101                         usb-phy         = <&usb3_phy>;
1102                 };
1103
1104                 usb4: usb@12530000 {
1105                         compatible      = "qcom,ehci-host";
1106                         reg             = <0x12530000 0x400>;
1107                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1108                         status          = "disabled";
1109                         usb-phy         = <&usb4_phy>;
1110                 };
1111
1112                 sata_phy0: phy@1b400000 {
1113                         compatible      = "qcom,apq8064-sata-phy";
1114                         status          = "disabled";
1115                         reg             = <0x1b400000 0x200>;
1116                         reg-names       = "phy_mem";
1117                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
1118                         clock-names     = "cfg";
1119                         #phy-cells      = <0>;
1120                 };
1121
1122                 sata0: sata@29000000 {
1123                         compatible              = "generic-ahci";
1124                         status                  = "disabled";
1125                         reg                     = <0x29000000 0x180>;
1126                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
1127
1128                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
1129                                                 <&gcc SATA_H_CLK>,
1130                                                 <&gcc SATA_A_CLK>,
1131                                                 <&gcc SATA_RXOOB_CLK>,
1132                                                 <&gcc SATA_PMALIVE_CLK>;
1133                         clock-names             = "slave_iface",
1134                                                 "iface",
1135                                                 "bus",
1136                                                 "rxoob",
1137                                                 "core_pmalive";
1138
1139                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
1140                                                 <&gcc SATA_PMALIVE_CLK>;
1141                         assigned-clock-rates    = <100000000>, <100000000>;
1142
1143                         phys                    = <&sata_phy0>;
1144                         phy-names               = "sata-phy";
1145                 };
1146
1147                 /* Temporary fixed regulator */
1148                 sdcc1bam:dma@12402000{
1149                         compatible = "qcom,bam-v1.3.0";
1150                         reg = <0x12402000 0x8000>;
1151                         interrupts = <0 98 0>;
1152                         clocks = <&gcc SDC1_H_CLK>;
1153                         clock-names = "bam_clk";
1154                         #dma-cells = <1>;
1155                         qcom,ee = <0>;
1156                 };
1157
1158                 sdcc3bam:dma@12182000{
1159                         compatible = "qcom,bam-v1.3.0";
1160                         reg = <0x12182000 0x8000>;
1161                         interrupts = <0 96 0>;
1162                         clocks = <&gcc SDC3_H_CLK>;
1163                         clock-names = "bam_clk";
1164                         #dma-cells = <1>;
1165                         qcom,ee = <0>;
1166                 };
1167
1168                 sdcc4bam:dma@121c2000{
1169                         compatible = "qcom,bam-v1.3.0";
1170                         reg = <0x121c2000 0x8000>;
1171                         interrupts = <0 95 0>;
1172                         clocks = <&gcc SDC4_H_CLK>;
1173                         clock-names = "bam_clk";
1174                         #dma-cells = <1>;
1175                         qcom,ee = <0>;
1176                 };
1177
1178                 amba {
1179                         compatible = "arm,amba-bus";
1180                         #address-cells = <1>;
1181                         #size-cells = <1>;
1182                         ranges;
1183                         sdcc1: sdcc@12400000 {
1184                                 status          = "disabled";
1185                                 compatible      = "arm,pl18x", "arm,primecell";
1186                                 arm,primecell-periphid = <0x00051180>;
1187                                 reg             = <0x12400000 0x2000>;
1188                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1189                                 interrupt-names = "cmd_irq";
1190                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1191                                 clock-names     = "mclk", "apb_pclk";
1192                                 bus-width       = <8>;
1193                                 max-frequency   = <96000000>;
1194                                 non-removable;
1195                                 cap-sd-highspeed;
1196                                 cap-mmc-highspeed;
1197                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1198                                 dma-names = "tx", "rx";
1199                         };
1200
1201                         sdcc3: sdcc@12180000 {
1202                                 compatible      = "arm,pl18x", "arm,primecell";
1203                                 arm,primecell-periphid = <0x00051180>;
1204                                 status          = "disabled";
1205                                 reg             = <0x12180000 0x2000>;
1206                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1207                                 interrupt-names = "cmd_irq";
1208                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1209                                 clock-names     = "mclk", "apb_pclk";
1210                                 bus-width       = <4>;
1211                                 cap-sd-highspeed;
1212                                 cap-mmc-highspeed;
1213                                 max-frequency   = <192000000>;
1214                                 no-1-8-v;
1215                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1216                                 dma-names = "tx", "rx";
1217                         };
1218
1219                         sdcc4: sdcc@121c0000 {
1220                                 compatible      = "arm,pl18x", "arm,primecell";
1221                                 arm,primecell-periphid = <0x00051180>;
1222                                 status          = "disabled";
1223                                 reg             = <0x121c0000 0x2000>;
1224                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1225                                 interrupt-names = "cmd_irq";
1226                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1227                                 clock-names     = "mclk", "apb_pclk";
1228                                 bus-width       = <4>;
1229                                 cap-sd-highspeed;
1230                                 cap-mmc-highspeed;
1231                                 max-frequency   = <48000000>;
1232                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1233                                 dma-names = "tx", "rx";
1234                                 pinctrl-names = "default";
1235                                 pinctrl-0 = <&sdc4_gpios>;
1236                         };
1237                 };
1238
1239                 tcsr: syscon@1a400000 {
1240                         compatible = "qcom,tcsr-apq8064", "syscon";
1241                         reg = <0x1a400000 0x100>;
1242                 };
1243
1244                 pcie: pci@1b500000 {
1245                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1246                         reg = <0x1b500000 0x1000
1247                                0x1b502000 0x80
1248                                0x1b600000 0x100
1249                                0x0ff00000 0x100000>;
1250                         reg-names = "dbi", "elbi", "parf", "config";
1251                         device_type = "pci";
1252                         linux,pci-domain = <0>;
1253                         bus-range = <0x00 0xff>;
1254                         num-lanes = <1>;
1255                         #address-cells = <3>;
1256                         #size-cells = <2>;
1257                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1258                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1259                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1260                         interrupt-names = "msi";
1261                         #interrupt-cells = <1>;
1262                         interrupt-map-mask = <0 0 0 0x7>;
1263                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1264                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1265                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1266                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1267                         clocks = <&gcc PCIE_A_CLK>,
1268                                  <&gcc PCIE_H_CLK>,
1269                                  <&gcc PCIE_PHY_REF_CLK>;
1270                         clock-names = "core", "iface", "phy";
1271                         resets = <&gcc PCIE_ACLK_RESET>,
1272                                  <&gcc PCIE_HCLK_RESET>,
1273                                  <&gcc PCIE_POR_RESET>,
1274                                  <&gcc PCIE_PCI_RESET>,
1275                                  <&gcc PCIE_PHY_RESET>;
1276                         reset-names = "axi", "ahb", "por", "pci", "phy";
1277                         status = "disabled";
1278                 };
1279
1280                 hdmi: qcom,hdmi-tx@4a00000 {
1281                         compatible = "qcom,hdmi-tx-8960";
1282                         reg-names = "core_physical";
1283                         reg = <0x04a00000 0x1000>;
1284                         interrupts = <GIC_SPI 79 0>;
1285                         clock-names =
1286                             "core_clk",
1287                             "master_iface_clk",
1288                             "slave_iface_clk";
1289                         clocks =
1290                             <&mmcc HDMI_APP_CLK>,
1291                             <&mmcc HDMI_M_AHB_CLK>,
1292                             <&mmcc HDMI_S_AHB_CLK>;
1293                         qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1294                         qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1295                         qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1296                         pinctrl-names = "default";
1297                         pinctrl-0 = <&hdmi_pinctrl>;
1298                 };
1299
1300                 gpu: qcom,adreno-3xx@4300000 {
1301                         compatible = "qcom,adreno-3xx";
1302                         reg = <0x04300000 0x20000>;
1303                         reg-names = "kgsl_3d0_reg_memory";
1304                         interrupts = <GIC_SPI 80 0>;
1305                         interrupt-names = "kgsl_3d0_irq";
1306                         clock-names =
1307                             "core_clk",
1308                             "iface_clk",
1309                             "mem_clk",
1310                             "mem_iface_clk";
1311                         clocks =
1312                             <&mmcc GFX3D_CLK>,
1313                             <&mmcc GFX3D_AHB_CLK>,
1314                             <&mmcc GFX3D_AXI_CLK>,
1315                             <&mmcc MMSS_IMEM_AHB_CLK>;
1316                         qcom,chipid = <0x03020002>;
1317
1318                          iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1319                                    &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1320                                    &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1321                                    &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1322
1323                         qcom,gpu-pwrlevels {
1324                                 compatible = "qcom,gpu-pwrlevels";
1325                                 qcom,gpu-pwrlevel@0 {
1326                                         qcom,gpu-freq = <450000000>;
1327                                 };
1328                                 qcom,gpu-pwrlevel@1 {
1329                                         qcom,gpu-freq = <27000000>;
1330                                 };
1331                         };
1332                 };
1333
1334                 mdp: qcom,mdp@5100000 {
1335                         compatible = "qcom,mdp";
1336                         reg = <0x05100000 0xf0000>;
1337                         interrupts = <GIC_SPI 75 0>;
1338                         connectors = <&hdmi>;
1339                         gpus = <&gpu>;
1340                         clock-names =
1341                             "core_clk",
1342                             "iface_clk",
1343                             "lut_clk",
1344                             "src_clk",
1345                             "hdmi_clk",
1346                             "mdp_clk",
1347                             "mdp_axi_clk";
1348                         clocks =
1349                             <&mmcc MDP_CLK>,
1350                             <&mmcc MDP_AHB_CLK>,
1351                             <&mmcc MDP_LUT_CLK>,
1352                             <&mmcc TV_SRC>,
1353                             <&mmcc HDMI_TV_CLK>,
1354                             <&mmcc MDP_TV_CLK>,
1355                             <&mmcc MDP_AXI_CLK>;
1356
1357                         iommus = <&mdp_port0 0 2
1358                                   &mdp_port1 0 2>;
1359                 };
1360
1361                 mdp_port0: qcom,iommu@7500000 {
1362                         compatible = "qcom,iommu-v0";
1363                         #iommu-cells = <2>;
1364                         clock-names =
1365                             "smmu_pclk",
1366                             "iommu_clk";
1367                         clocks =
1368                             <&mmcc SMMU_AHB_CLK>,
1369                             <&mmcc MDP_AXI_CLK>;
1370                         reg = <0x07500000 0x100000>;
1371                         interrupts =
1372                             <GIC_SPI 63 0>,
1373                             <GIC_SPI 64 0>;
1374                         ncb = <2>;
1375                 };
1376
1377                 mdp_port1: qcom,iommu@7600000 {
1378                         compatible = "qcom,iommu";
1379                         #iommu-cells = <2>;
1380                         clock-names =
1381                             "smmu_pclk",
1382                             "iommu_clk";
1383                         clocks =
1384                             <&mmcc SMMU_AHB_CLK>,
1385                             <&mmcc MDP_AXI_CLK>;
1386                         reg = <0x07600000 0x100000>;
1387                         interrupts =
1388                             <GIC_SPI 61 0>,
1389                             <GIC_SPI 62 0>;
1390                         ncb = <2>;
1391                 };
1392
1393                 gfx3d: qcom,iommu@7c00000 {
1394                         compatible = "qcom,iommu-v0";
1395                         #iommu-cells = <16>;
1396                         clock-names =
1397                             "smmu_pclk",
1398                             "iommu_clk";
1399                         clocks =
1400                             <&mmcc SMMU_AHB_CLK>,
1401                             <&mmcc GFX3D_AXI_CLK>;
1402                         reg = <0x07c00000 0x100000>;
1403                         interrupts =
1404                             <GIC_SPI 69 0>,
1405                             <GIC_SPI 70 0>;
1406                         ncb = <3>;
1407                 };
1408
1409                 gfx3d1: qcom,iommu@7d00000 {
1410                         compatible = "qcom,iommu-v0";
1411                         #iommu-cells = <16>;
1412                         clock-names =
1413                             "smmu_pclk",
1414                             "iommu_clk";
1415                         clocks =
1416                             <&mmcc SMMU_AHB_CLK>,
1417                             <&mmcc GFX3D_AXI_CLK>;
1418                         reg = <0x07d00000 0x100000>;
1419                         interrupts =
1420                             <GIC_SPI 210 0>,
1421                             <GIC_SPI 211 0>;
1422                         ncb = <3>;
1423                 };
1424         };
1425 };