arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 / {
  11         model = "Qualcomm APQ8064";
  12         compatible = "qcom,apq8064";
  13         interrupt-parent = <&intc>;
  14
  15         reserved-memory {
  16                 #address-cells = <1>;
  17                 #size-cells = <1>;
  18                 ranges;
  19
  20                 smem_region: smem@80000000 {
  21                         reg = <0x80000000 0x200000>;
  22                         no-map;
  23                 };
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         compatible = "qcom,krait";
  32                         enable-method = "qcom,kpss-acc-v1";
  33                         device_type = "cpu";
  34                         reg = <0>;
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc0>;
  37                         qcom,saw = <&saw0>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         cpu-idle-states = <&CPU_SPC>;
  50                 };
  51
  52                 cpu@2 {
  53                         compatible = "qcom,krait";
  54                         enable-method = "qcom,kpss-acc-v1";
  55                         device_type = "cpu";
  56                         reg = <2>;
  57                         next-level-cache = <&L2>;
  58                         qcom,acc = <&acc2>;
  59                         qcom,saw = <&saw2>;
  60                         cpu-idle-states = <&CPU_SPC>;
  61                 };
  62
  63                 cpu@3 {
  64                         compatible = "qcom,krait";
  65                         enable-method = "qcom,kpss-acc-v1";
  66                         device_type = "cpu";
  67                         reg = <3>;
  68                         next-level-cache = <&L2>;
  69                         qcom,acc = <&acc3>;
  70                         qcom,saw = <&saw3>;
  71                         cpu-idle-states = <&CPU_SPC>;
  72                 };
  73
  74                 L2: l2-cache {
  75                         compatible = "cache";
  76                         cache-level = <2>;
  77                 };
  78
  79                 idle-states {
  80                         CPU_SPC: spc {
  81                                 compatible = "qcom,idle-state-spc",
  82                                                 "arm,idle-state";
  83                                 entry-latency-us = <400>;
  84                                 exit-latency-us = <900>;
  85                                 min-residency-us = <3000>;
  86                         };
  87                 };
  88         };
  89
  90         cpu-pmu {
  91                 compatible = "qcom,krait-pmu";
  92                 interrupts = <1 10 0x304>;
  93         };
  94
  95         clocks {
  96                 cxo_board {
  97                         compatible = "fixed-clock";
  98                         #clock-cells = <0>;
  99                         clock-frequency = <19200000>;
 100                 };
 101
 102                 pxo_board {
 103                         compatible = "fixed-clock";
 104                         #clock-cells = <0>;
 105                         clock-frequency = <27000000>;
 106                 };
 107
 108                 sleep_clk {
 109                         compatible = "fixed-clock";
 110                         #clock-cells = <0>;
 111                         clock-frequency = <32768>;
 112                 };
 113         };
 114
 115         sfpb_mutex: hwmutex {
 116                 compatible = "qcom,sfpb-mutex";
 117                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 118                 #hwlock-cells = <1>;
 119         };
 120
 121         smem {
 122                 compatible = "qcom,smem";
 123                 memory-region = <&smem_region>;
 124
 125                 hwlocks = <&sfpb_mutex 3>;
 126         };
 127
 128         soc: soc {
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132                 compatible = "simple-bus";
 133
 134                 tlmm_pinmux: pinctrl@800000 {
 135                         compatible = "qcom,apq8064-pinctrl";
 136                         reg = <0x800000 0x4000>;
 137
 138                         gpio-controller;
 139                         #gpio-cells = <2>;
 140                         interrupt-controller;
 141                         #interrupt-cells = <2>;
 142                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 143
 144                         pinctrl-names = "default";
 145                         pinctrl-0 = <&ps_hold>;
 146
 147                         sdc4_gpios: sdc4-gpios {
 148                                 pios {
 149                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 150                                         function = "sdc4";
 151                                 };
 152                         };
 153
 154                         hdmi_pinctrl: hdmi-pinctrl {
 155                                 mux1 {
 156                                         pins = "gpio69", "gpio70", "gpio71";
 157                                         function = "hdmi";
 158                                         bias-pull-up;
 159                                         drive-strength = <2>;
 160                                 };
 161                                 mux2 {
 162                                         pins = "gpio72";
 163                                         function = "hdmi";
 164                                         bias-pull-down;
 165                                         drive-strength = <16>;
 166                                 };
 167                         };
 168                         ps_hold: ps_hold {
 169                                 mux {
 170                                         pins = "gpio78";
 171                                         function = "ps_hold";
 172                                 };
 173                         };
 174
 175                         i2c1_pins: i2c1 {
 176                                 mux {
 177                                         pins = "gpio20", "gpio21";
 178                                         function = "gsbi1";
 179                                 };
 180                         };
 181
 182                         i2c3_pins: i2c3 {
 183                                 mux {
 184                                         pins = "gpio8", "gpio9";
 185                                         function = "gsbi3";
 186                                 };
 187                         };
 188
 189                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 190                                 mux {
 191                                         pins = "gpio14", "gpio15";
 192                                         function = "gsbi6";
 193                                 };
 194                         };
 195
 196                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 197                                 mux {
 198                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 199                                         function = "gsbi6";
 200                                 };
 201                         };
 202
 203                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 204                                 mux {
 205                                         pins = "gpio82", "gpio83";
 206                                         function = "gsbi7";
 207                                 };
 208                         };
 209
 210                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 211                                 mux {
 212                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 213                                         function = "gsbi7";
 214                                 };
 215                         };
 216                 };
 217
 218                 sfpb_wrapper_mutex: syscon@1200000 {
 219                         compatible = "syscon";
 220                         reg = <0x01200000 0x8000>;
 221                 };
 222
 223                 intc: interrupt-controller@2000000 {
 224                         compatible = "qcom,msm-qgic2";
 225                         interrupt-controller;
 226                         #interrupt-cells = <3>;
 227                         reg = <0x02000000 0x1000>,
 228                               <0x02002000 0x1000>;
 229                 };
 230
 231                 timer@200a000 {
 232                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 233                         interrupts = <1 1 0x301>,
 234                                      <1 2 0x301>,
 235                                      <1 3 0x301>;
 236                         reg = <0x0200a000 0x100>;
 237                         clock-frequency = <27000000>,
 238                                           <32768>;
 239                         cpu-offset = <0x80000>;
 240                 };
 241
 242                 acc0: clock-controller@2088000 {
 243                         compatible = "qcom,kpss-acc-v1";
 244                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 245                 };
 246
 247                 acc1: clock-controller@2098000 {
 248                         compatible = "qcom,kpss-acc-v1";
 249                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 250                 };
 251
 252                 acc2: clock-controller@20a8000 {
 253                         compatible = "qcom,kpss-acc-v1";
 254                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 255                 };
 256
 257                 acc3: clock-controller@20b8000 {
 258                         compatible = "qcom,kpss-acc-v1";
 259                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 260                 };
 261
 262                 saw0: power-controller@2089000 {
 263                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 264                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 265                         regulator;
 266                 };
 267
 268                 saw1: power-controller@2099000 {
 269                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 270                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 271                         regulator;
 272                 };
 273
 274                 saw2: power-controller@20a9000 {
 275                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 276                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 277                         regulator;
 278                 };
 279
 280                 saw3: power-controller@20b9000 {
 281                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 282                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 283                         regulator;
 284                 };
 285
 286                 gsbi1: gsbi@12440000 {
 287                         status = "disabled";
 288                         compatible = "qcom,gsbi-v1.0.0";
 289                         cell-index = <1>;
 290                         reg = <0x12440000 0x100>;
 291                         clocks = <&gcc GSBI1_H_CLK>;
 292                         clock-names = "iface";
 293                         #address-cells = <1>;
 294                         #size-cells = <1>;
 295                         ranges;
 296
 297                         syscon-tcsr = <&tcsr>;
 298
 299                         i2c1: i2c@12460000 {
 300                                 compatible = "qcom,i2c-qup-v1.1.1";
 301                                 pinctrl-0 = <&i2c1_pins>;
 302                                 pinctrl-names = "default";
 303                                 reg = <0x12460000 0x1000>;
 304                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 305                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 306                                 clock-names = "core", "iface";
 307                                 #address-cells = <1>;
 308                                 #size-cells = <0>;
 309                         };
 310                 };
 311
 312                 gsbi2: gsbi@12480000 {
 313                         status = "disabled";
 314                         compatible = "qcom,gsbi-v1.0.0";
 315                         cell-index = <2>;
 316                         reg = <0x12480000 0x100>;
 317                         clocks = <&gcc GSBI2_H_CLK>;
 318                         clock-names = "iface";
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         ranges;
 322
 323                         syscon-tcsr = <&tcsr>;
 324
 325                         i2c2: i2c@124a0000 {
 326                                 compatible = "qcom,i2c-qup-v1.1.1";
 327                                 reg = <0x124a0000 0x1000>;
 328                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 329                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 330                                 clock-names = "core", "iface";
 331                                 #address-cells = <1>;
 332                                 #size-cells = <0>;
 333                         };
 334                 };
 335
 336                 gsbi3: gsbi@16200000 {
 337                         status = "disabled";
 338                         compatible = "qcom,gsbi-v1.0.0";
 339                         cell-index = <3>;
 340                         reg = <0x16200000 0x100>;
 341                         clocks = <&gcc GSBI3_H_CLK>;
 342                         clock-names = "iface";
 343                         #address-cells = <1>;
 344                         #size-cells = <1>;
 345                         ranges;
 346                         i2c3: i2c@16280000 {
 347                                 compatible = "qcom,i2c-qup-v1.1.1";
 348                                 pinctrl-0 = <&i2c3_pins>;
 349                                 pinctrl-names = "default";
 350                                 reg = <0x16280000 0x1000>;
 351                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 352                                 clocks = <&gcc GSBI3_QUP_CLK>,
 353                                          <&gcc GSBI3_H_CLK>;
 354                                 clock-names = "core", "iface";
 355                         };
 356                 };
 357
 358                 gsbi5: gsbi@1a200000 {
 359                         status = "disabled";
 360                         compatible = "qcom,gsbi-v1.0.0";
 361                         cell-index = <5>;
 362                         reg = <0x1a200000 0x03>;
 363                         clocks = <&gcc GSBI5_H_CLK>;
 364                         clock-names = "iface";
 365                         #address-cells = <1>;
 366                         #size-cells = <1>;
 367                         ranges;
 368
 369                         gsbi5_serial: serial@1a240000 {
 370                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 371                                 reg = <0x1a240000 0x100>,
 372                                       <0x1a200000 0x03>;
 373                                 interrupts = <0 154 0x0>;
 374                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 375                                 clock-names = "core", "iface";
 376                                 status = "disabled";
 377                         };
 378                 };
 379
 380                 gsbi6: gsbi@16500000 {
 381                         status = "disabled";
 382                         compatible = "qcom,gsbi-v1.0.0";
 383                         cell-index = <6>;
 384                         reg = <0x16500000 0x03>;
 385                         clocks = <&gcc GSBI6_H_CLK>;
 386                         clock-names = "iface";
 387                         #address-cells = <1>;
 388                         #size-cells = <1>;
 389                         ranges;
 390
 391                         gsbi6_serial: serial@16540000 {
 392                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 393                                 reg = <0x16540000 0x100>,
 394                                       <0x16500000 0x03>;
 395                                 interrupts = <0 156 0x0>;
 396                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 397                                 clock-names = "core", "iface";
 398                                 status = "disabled";
 399                         };
 400                 };
 401
 402                 gsbi7: gsbi@16600000 {
 403                         status = "disabled";
 404                         compatible = "qcom,gsbi-v1.0.0";
 405                         cell-index = <7>;
 406                         reg = <0x16600000 0x100>;
 407                         clocks = <&gcc GSBI7_H_CLK>;
 408                         clock-names = "iface";
 409                         #address-cells = <1>;
 410                         #size-cells = <1>;
 411                         ranges;
 412                         syscon-tcsr = <&tcsr>;
 413
 414                         gsbi7_serial: serial@16640000 {
 415                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 416                                 reg = <0x16640000 0x1000>,
 417                                       <0x16600000 0x1000>;
 418                                 interrupts = <0 158 0x0>;
 419                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 420                                 clock-names = "core", "iface";
 421                                 status = "disabled";
 422                         };
 423                 };
 424
 425                 rng@1a500000 {
 426                         compatible = "qcom,prng";
 427                         reg = <0x1a500000 0x200>;
 428                         clocks = <&gcc PRNG_CLK>;
 429                         clock-names = "core";
 430                 };
 431
 432                 qcom,ssbi@500000 {
 433                         compatible = "qcom,ssbi";
 434                         reg = <0x00500000 0x1000>;
 435                         qcom,controller-type = "pmic-arbiter";
 436
 437                         pmicintc: pmic@0 {
 438                                 compatible = "qcom,pm8921";
 439                                 interrupt-parent = <&tlmm_pinmux>;
 440                                 interrupts = <74 8>;
 441                                 #interrupt-cells = <2>;
 442                                 interrupt-controller;
 443                                 #address-cells = <1>;
 444                                 #size-cells = <0>;
 445
 446                                 pm8921_gpio: gpio@150 {
 447
 448                                         compatible = "qcom,pm8921-gpio",
 449                                                      "qcom,ssbi-gpio";
 450                                         reg = <0x150>;
 451                                         interrupts = <192 1>, <193 1>, <194 1>,
 452                                                      <195 1>, <196 1>, <197 1>,
 453                                                      <198 1>, <199 1>, <200 1>,
 454                                                      <201 1>, <202 1>, <203 1>,
 455                                                      <204 1>, <205 1>, <206 1>,
 456                                                      <207 1>, <208 1>, <209 1>,
 457                                                      <210 1>, <211 1>, <212 1>,
 458                                                      <213 1>, <214 1>, <215 1>,
 459                                                      <216 1>, <217 1>, <218 1>,
 460                                                      <219 1>, <220 1>, <221 1>,
 461                                                      <222 1>, <223 1>, <224 1>,
 462                                                      <225 1>, <226 1>, <227 1>,
 463                                                      <228 1>, <229 1>, <230 1>,
 464                                                      <231 1>, <232 1>, <233 1>,
 465                                                      <234 1>, <235 1>;
 466
 467                                         gpio-controller;
 468                                         #gpio-cells = <2>;
 469
 470                                 };
 471
 472                                 pm8921_mpps: mpps@50 {
 473                                         compatible = "qcom,pm8921-mpp",
 474                                                      "qcom,ssbi-mpp";
 475                                         reg = <0x50>;
 476                                         gpio-controller;
 477                                         #gpio-cells = <2>;
 478                                         interrupts =
 479                                         <128 1>, <129 1>, <130 1>, <131 1>,
 480                                         <132 1>, <133 1>, <134 1>, <135 1>,
 481                                         <136 1>, <137 1>, <138 1>, <139 1>;
 482                                 };
 483
 484                                 rtc@11d {
 485                                         compatible = "qcom,pm8921-rtc";
 486                                         interrupt-parent = <&pmicintc>;
 487                                         interrupts = <39 1>;
 488                                         reg = <0x11d>;
 489                                         allow-set-time;
 490                                 };
 491
 492                                 pwrkey@1c {
 493                                         compatible = "qcom,pm8921-pwrkey";
 494                                         reg = <0x1c>;
 495                                         interrupt-parent = <&pmicintc>;
 496                                         interrupts = <50 1>, <51 1>;
 497                                         debounce = <15625>;
 498                                         pull-up;
 499                                 };
 500                         };
 501                 };
 502
 503                 gcc: clock-controller@900000 {
 504                         compatible = "qcom,gcc-apq8064";
 505                         reg = <0x00900000 0x4000>;
 506                         #clock-cells = <1>;
 507                         #reset-cells = <1>;
 508                 };
 509
 510                 lcc: clock-controller@28000000 {
 511                         compatible = "qcom,lcc-apq8064";
 512                         reg = <0x28000000 0x1000>;
 513                         #clock-cells = <1>;
 514                         #reset-cells = <1>;
 515                 };
 516
 517                 mmcc: clock-controller@4000000 {
 518                         compatible = "qcom,mmcc-apq8064";
 519                         reg = <0x4000000 0x1000>;
 520                         #clock-cells = <1>;
 521                         #reset-cells = <1>;
 522                 };
 523
 524                 l2cc: clock-controller@2011000 {
 525                         compatible      = "syscon";
 526                         reg             = <0x2011000 0x1000>;
 527                 };
 528
 529                 rpm@108000 {
 530                         compatible      = "qcom,rpm-apq8064";
 531                         reg             = <0x108000 0x1000>;
 532                         qcom,ipc        = <&l2cc 0x8 2>;
 533
 534                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 535                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 536                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 537                         interrupt-names = "ack", "err", "wakeup";
 538
 539                         regulators {
 540                                 compatible = "qcom,rpm-pm8921-regulators";
 541
 542                                 pm8921_s1: s1 {};
 543                                 pm8921_s2: s2 {};
 544                                 pm8921_s3: s3 {};
 545                                 pm8921_s4: s4 {};
 546                                 pm8921_s7: s7 {};
 547                                 pm8921_s8: s8 {};
 548
 549                                 pm8921_l1: l1 {};
 550                                 pm8921_l2: l2 {};
 551                                 pm8921_l3: l3 {};
 552                                 pm8921_l4: l4 {};
 553                                 pm8921_l5: l5 {};
 554                                 pm8921_l6: l6 {};
 555                                 pm8921_l7: l7 {};
 556                                 pm8921_l8: l8 {};
 557                                 pm8921_l9: l9 {};
 558                                 pm8921_l10: l10 {};
 559                                 pm8921_l11: l11 {};
 560                                 pm8921_l12: l12 {};
 561                                 pm8921_l14: l14 {};
 562                                 pm8921_l15: l15 {};
 563                                 pm8921_l16: l16 {};
 564                                 pm8921_l17: l17 {};
 565                                 pm8921_l18: l18 {};
 566                                 pm8921_l21: l21 {};
 567                                 pm8921_l22: l22 {};
 568                                 pm8921_l23: l23 {};
 569                                 pm8921_l24: l24 {};
 570                                 pm8921_l25: l25 {};
 571                                 pm8921_l26: l26 {};
 572                                 pm8921_l27: l27 {};
 573                                 pm8921_l28: l28 {};
 574                                 pm8921_l29: l29 {};
 575
 576                                 pm8921_lvs1: lvs1 {};
 577                                 pm8921_lvs2: lvs2 {};
 578                                 pm8921_lvs3: lvs3 {};
 579                                 pm8921_lvs4: lvs4 {};
 580                                 pm8921_lvs5: lvs5 {};
 581                                 pm8921_lvs6: lvs6 {};
 582                                 pm8921_lvs7: lvs7 {};
 583
 584                                 pm8921_usb_switch: usb-switch {};
 585
 586                                 pm8921_hdmi_switch: hdmi-switch {
 587                                         bias-pull-down;
 588                                 };
 589
 590                                 pm8921_ncp: ncp {};
 591                         };
 592                 };
 593
 594                 usb1_phy: phy@12500000 {
 595                         compatible      = "qcom,usb-otg-ci";
 596                         reg             = <0x12500000 0x400>;
 597                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 598                         status          = "disabled";
 599                         dr_mode         = "host";
 600
 601                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 602                                           <&gcc USB_HS1_H_CLK>;
 603                         clock-names     = "core", "iface";
 604
 605                         resets          = <&gcc USB_HS1_RESET>;
 606                         reset-names     = "link";
 607                 };
 608
 609                 usb3_phy: phy@12520000 {
 610                         compatible      = "qcom,usb-otg-ci";
 611                         reg             = <0x12520000 0x400>;
 612                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 613                         status          = "disabled";
 614                         dr_mode         = "host";
 615
 616                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 617                                           <&gcc USB_HS3_H_CLK>;
 618                         clock-names     = "core", "iface";
 619
 620                         resets          = <&gcc USB_HS3_RESET>;
 621                         reset-names     = "link";
 622                 };
 623
 624                 usb4_phy: phy@12530000 {
 625                         compatible      = "qcom,usb-otg-ci";
 626                         reg             = <0x12530000 0x400>;
 627                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 628                         status          = "disabled";
 629                         dr_mode         = "host";
 630
 631                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 632                                           <&gcc USB_HS4_H_CLK>;
 633                         clock-names     = "core", "iface";
 634
 635                         resets          = <&gcc USB_HS4_RESET>;
 636                         reset-names     = "link";
 637                 };
 638
 639                 gadget1: gadget@12500000 {
 640                         compatible      = "qcom,ci-hdrc";
 641                         reg             = <0x12500000 0x400>;
 642                         status          = "disabled";
 643                         dr_mode         = "peripheral";
 644                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 645                         usb-phy         = <&usb1_phy>;
 646                 };
 647
 648                 usb1: usb@12500000 {
 649                         compatible      = "qcom,ehci-host";
 650                         reg             = <0x12500000 0x400>;
 651                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 652                         status          = "disabled";
 653                         usb-phy         = <&usb1_phy>;
 654                 };
 655
 656                 usb3: usb@12520000 {
 657                         compatible      = "qcom,ehci-host";
 658                         reg             = <0x12520000 0x400>;
 659                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 660                         status          = "disabled";
 661                         usb-phy         = <&usb3_phy>;
 662                 };
 663
 664                 usb4: usb@12530000 {
 665                         compatible      = "qcom,ehci-host";
 666                         reg             = <0x12530000 0x400>;
 667                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 668                         status          = "disabled";
 669                         usb-phy         = <&usb4_phy>;
 670                 };
 671
 672                 sata_phy0: phy@1b400000 {
 673                         compatible      = "qcom,apq8064-sata-phy";
 674                         status          = "disabled";
 675                         reg             = <0x1b400000 0x200>;
 676                         reg-names       = "phy_mem";
 677                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 678                         clock-names     = "cfg";
 679                         #phy-cells      = <0>;
 680                 };
 681
 682                 sata0: sata@29000000 {
 683                         compatible              = "generic-ahci";
 684                         status                  = "disabled";
 685                         reg                     = <0x29000000 0x180>;
 686                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 687
 688                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 689                                                 <&gcc SATA_H_CLK>,
 690                                                 <&gcc SATA_A_CLK>,
 691                                                 <&gcc SATA_RXOOB_CLK>,
 692                                                 <&gcc SATA_PMALIVE_CLK>;
 693                         clock-names             = "slave_iface",
 694                                                 "iface",
 695                                                 "bus",
 696                                                 "rxoob",
 697                                                 "core_pmalive";
 698
 699                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 700                                                 <&gcc SATA_PMALIVE_CLK>;
 701                         assigned-clock-rates    = <100000000>, <100000000>;
 702
 703                         phys                    = <&sata_phy0>;
 704                         phy-names               = "sata-phy";
 705                 };
 706
 707                 /* Temporary fixed regulator */
 708                 sdcc1bam:dma@12402000{
 709                         compatible = "qcom,bam-v1.3.0";
 710                         reg = <0x12402000 0x8000>;
 711                         interrupts = <0 98 0>;
 712                         clocks = <&gcc SDC1_H_CLK>;
 713                         clock-names = "bam_clk";
 714                         #dma-cells = <1>;
 715                         qcom,ee = <0>;
 716                 };
 717
 718                 sdcc3bam:dma@12182000{
 719                         compatible = "qcom,bam-v1.3.0";
 720                         reg = <0x12182000 0x8000>;
 721                         interrupts = <0 96 0>;
 722                         clocks = <&gcc SDC3_H_CLK>;
 723                         clock-names = "bam_clk";
 724                         #dma-cells = <1>;
 725                         qcom,ee = <0>;
 726                 };
 727
 728                 sdcc4bam:dma@121c2000{
 729                         compatible = "qcom,bam-v1.3.0";
 730                         reg = <0x121c2000 0x8000>;
 731                         interrupts = <0 95 0>;
 732                         clocks = <&gcc SDC4_H_CLK>;
 733                         clock-names = "bam_clk";
 734                         #dma-cells = <1>;
 735                         qcom,ee = <0>;
 736                 };
 737
 738                 amba {
 739                         compatible = "arm,amba-bus";
 740                         #address-cells = <1>;
 741                         #size-cells = <1>;
 742                         ranges;
 743                         sdcc1: sdcc@12400000 {
 744                                 status          = "disabled";
 745                                 compatible      = "arm,pl18x", "arm,primecell";
 746                                 arm,primecell-periphid = <0x00051180>;
 747                                 reg             = <0x12400000 0x2000>;
 748                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 749                                 interrupt-names = "cmd_irq";
 750                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 751                                 clock-names     = "mclk", "apb_pclk";
 752                                 bus-width       = <8>;
 753                                 max-frequency   = <96000000>;
 754                                 non-removable;
 755                                 cap-sd-highspeed;
 756                                 cap-mmc-highspeed;
 757                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 758                                 dma-names = "tx", "rx";
 759                         };
 760
 761                         sdcc3: sdcc@12180000 {
 762                                 compatible      = "arm,pl18x", "arm,primecell";
 763                                 arm,primecell-periphid = <0x00051180>;
 764                                 status          = "disabled";
 765                                 reg             = <0x12180000 0x2000>;
 766                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 767                                 interrupt-names = "cmd_irq";
 768                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 769                                 clock-names     = "mclk", "apb_pclk";
 770                                 bus-width       = <4>;
 771                                 cap-sd-highspeed;
 772                                 cap-mmc-highspeed;
 773                                 max-frequency   = <192000000>;
 774                                 no-1-8-v;
 775                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 776                                 dma-names = "tx", "rx";
 777                         };
 778
 779                         sdcc4: sdcc@121c0000 {
 780                                 compatible      = "arm,pl18x", "arm,primecell";
 781                                 arm,primecell-periphid = <0x00051180>;
 782                                 status          = "disabled";
 783                                 reg             = <0x121c0000 0x2000>;
 784                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 785                                 interrupt-names = "cmd_irq";
 786                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 787                                 clock-names     = "mclk", "apb_pclk";
 788                                 bus-width       = <4>;
 789                                 cap-sd-highspeed;
 790                                 cap-mmc-highspeed;
 791                                 max-frequency   = <48000000>;
 792                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 793                                 dma-names = "tx", "rx";
 794                                 pinctrl-names = "default";
 795                                 pinctrl-0 = <&sdc4_gpios>;
 796                         };
 797                 };
 798
 799                 tcsr: syscon@1a400000 {
 800                         compatible = "qcom,tcsr-apq8064", "syscon";
 801                         reg = <0x1a400000 0x100>;
 802                 };
 803
 804                 pcie: pci@1b500000 {
 805                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 806                         reg = <0x1b500000 0x1000
 807                                0x1b502000 0x80
 808                                0x1b600000 0x100
 809                                0x0ff00000 0x100000>;
 810                         reg-names = "dbi", "elbi", "parf", "config";
 811                         device_type = "pci";
 812                         linux,pci-domain = <0>;
 813                         bus-range = <0x00 0xff>;
 814                         num-lanes = <1>;
 815                         #address-cells = <3>;
 816                         #size-cells = <2>;
 817                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 818                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 819                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 820                         interrupt-names = "msi";
 821                         #interrupt-cells = <1>;
 822                         interrupt-map-mask = <0 0 0 0x7>;
 823                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 824                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 825                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 826                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 827                         clocks = <&gcc PCIE_A_CLK>,
 828                                  <&gcc PCIE_H_CLK>,
 829                                  <&gcc PCIE_PHY_REF_CLK>;
 830                         clock-names = "core", "iface", "phy";
 831                         resets = <&gcc PCIE_ACLK_RESET>,
 832                                  <&gcc PCIE_HCLK_RESET>,
 833                                  <&gcc PCIE_POR_RESET>,
 834                                  <&gcc PCIE_PCI_RESET>,
 835                                  <&gcc PCIE_PHY_RESET>;
 836                         reset-names = "axi", "ahb", "por", "pci", "phy";
 837                         status = "disabled";
 838                 };
 839
 840                 hdmi: qcom,hdmi-tx@4a00000 {
 841                         compatible = "qcom,hdmi-tx-8960";
 842                         reg-names = "core_physical";
 843                         reg = <0x04a00000 0x1000>;
 844                         interrupts = <GIC_SPI 79 0>;
 845                         clock-names =
 846                             "core_clk",
 847                             "master_iface_clk",
 848                             "slave_iface_clk";
 849                         clocks =
 850                             <&mmcc HDMI_APP_CLK>,
 851                             <&mmcc HDMI_M_AHB_CLK>,
 852                             <&mmcc HDMI_S_AHB_CLK>;
 853                         qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
 854                         qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
 855                         qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
 856                         pinctrl-names = "default";
 857                         pinctrl-0 = <&hdmi_pinctrl>;
 858                 };
 859
 860                 gpu: qcom,adreno-3xx@4300000 {
 861                         compatible = "qcom,adreno-3xx";
 862                         reg = <0x04300000 0x20000>;
 863                         reg-names = "kgsl_3d0_reg_memory";
 864                         interrupts = <GIC_SPI 80 0>;
 865                         interrupt-names = "kgsl_3d0_irq";
 866                         clock-names =
 867                             "core_clk",
 868                             "iface_clk",
 869                             "mem_clk",
 870                             "mem_iface_clk";
 871                         clocks =
 872                             <&mmcc GFX3D_CLK>,
 873                             <&mmcc GFX3D_AHB_CLK>,
 874                             <&mmcc GFX3D_AXI_CLK>,
 875                             <&mmcc MMSS_IMEM_AHB_CLK>;
 876                         qcom,chipid = <0x03020002>;
 877                         qcom,gpu-pwrlevels {
 878                                 compatible = "qcom,gpu-pwrlevels";
 879                                 qcom,gpu-pwrlevel@0 {
 880                                         qcom,gpu-freq = <450000000>;
 881                                 };
 882                                 qcom,gpu-pwrlevel@1 {
 883                                         qcom,gpu-freq = <27000000>;
 884                                 };
 885                         };
 886                 };
 887
 888                 mdp: qcom,mdp@5100000 {
 889                         compatible = "qcom,mdp";
 890                         reg = <0x05100000 0xf0000>;
 891                         interrupts = <GIC_SPI 75 0>;
 892                         connectors = <&hdmi>;
 893                         gpus = <&gpu>;
 894                         clock-names =
 895                             "core_clk",
 896                             "iface_clk",
 897                             "lut_clk",
 898                             "src_clk",
 899                             "hdmi_clk",
 900                             "mdp_clk",
 901                             "mdp_axi_clk";
 902                         clocks =
 903                             <&mmcc MDP_CLK>,
 904                             <&mmcc MDP_AHB_CLK>,
 905                             <&mmcc MDP_LUT_CLK>,
 906                             <&mmcc TV_SRC>,
 907                             <&mmcc HDMI_TV_CLK>,
 908                             <&mmcc MDP_TV_CLK>,
 909                             <&mmcc MDP_AXI_CLK>;
 910                 };
 911         };
 912 };