3 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm APQ 8084";
10 compatible = "qcom,apq8084";
11 interrupt-parent = <&intc>;
18 smem_mem: smem_region@fa00000 {
19 reg = <0xfa00000 0x200000>;
30 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v2";
33 next-level-cache = <&L2>;
36 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v2";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v2";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
63 compatible = "qcom,krait";
65 enable-method = "qcom,kpss-acc-v2";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
73 compatible = "qcom,arch-cache";
80 compatible = "qcom,idle-state-spc",
82 entry-latency-us = <150>;
83 exit-latency-us = <200>;
84 min-residency-us = <2000>;
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 7 0xf04>;
95 compatible = "arm,armv7-timer";
96 interrupts = <1 2 0xf08>,
100 clock-frequency = <19200000>;
104 compatible = "qcom,smem";
106 qcom,rpm-msg-ram = <&rpm_msg_ram>;
107 memory-region = <&smem_mem>;
109 hwlocks = <&tcsr_mutex 3>;
113 #address-cells = <1>;
116 compatible = "simple-bus";
118 intc: interrupt-controller@f9000000 {
119 compatible = "qcom,msm-qgic2";
120 interrupt-controller;
121 #interrupt-cells = <3>;
122 reg = <0xf9000000 0x1000>,
126 apcs: syscon@f9011000 {
127 compatible = "syscon";
128 reg = <0xf9011000 0x1000>;
132 #address-cells = <1>;
135 compatible = "arm,armv7-timer-mem";
136 reg = <0xf9020000 0x1000>;
137 clock-frequency = <19200000>;
141 interrupts = <0 8 0x4>,
143 reg = <0xf9021000 0x1000>,
149 interrupts = <0 9 0x4>;
150 reg = <0xf9023000 0x1000>;
156 interrupts = <0 10 0x4>;
157 reg = <0xf9024000 0x1000>;
163 interrupts = <0 11 0x4>;
164 reg = <0xf9025000 0x1000>;
170 interrupts = <0 12 0x4>;
171 reg = <0xf9026000 0x1000>;
177 interrupts = <0 13 0x4>;
178 reg = <0xf9027000 0x1000>;
184 interrupts = <0 14 0x4>;
185 reg = <0xf9028000 0x1000>;
190 saw0: power-controller@f9089000 {
191 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
192 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
195 saw1: power-controller@f9099000 {
196 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
197 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
200 saw2: power-controller@f90a9000 {
201 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
202 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
205 saw3: power-controller@f90b9000 {
206 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
207 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
210 saw_l2: power-controller@f9012000 {
211 compatible = "qcom,saw2";
212 reg = <0xf9012000 0x1000>;
216 acc0: clock-controller@f9088000 {
217 compatible = "qcom,kpss-acc-v2";
218 reg = <0xf9088000 0x1000>,
222 acc1: clock-controller@f9098000 {
223 compatible = "qcom,kpss-acc-v2";
224 reg = <0xf9098000 0x1000>,
228 acc2: clock-controller@f90a8000 {
229 compatible = "qcom,kpss-acc-v2";
230 reg = <0xf90a8000 0x1000>,
234 acc3: clock-controller@f90b8000 {
235 compatible = "qcom,kpss-acc-v2";
236 reg = <0xf90b8000 0x1000>,
241 compatible = "qcom,pshold";
242 reg = <0xfc4ab000 0x4>;
245 gcc: clock-controller@fc400000 {
246 compatible = "qcom,gcc-apq8084";
249 #power-domain-cells = <1>;
250 reg = <0xfc400000 0x4000>;
253 tcsr_mutex_regs: syscon@fd484000 {
254 compatible = "syscon";
255 reg = <0xfd484000 0x2000>;
259 compatible = "qcom,tcsr-mutex";
260 syscon = <&tcsr_mutex_regs 0 0x80>;
264 rpm_msg_ram: memory@fc428000 {
265 compatible = "qcom,rpm-msg-ram";
266 reg = <0xfc428000 0x4000>;
269 tlmm: pinctrl@fd510000 {
270 compatible = "qcom,apq8084-pinctrl";
271 reg = <0xfd510000 0x4000>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 interrupts = <0 208 0>;
279 blsp2_uart2: serial@f995e000 {
280 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
281 reg = <0xf995e000 0x1000>;
282 interrupts = <0 114 0x0>;
283 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
284 clock-names = "core", "iface";
289 compatible = "qcom,sdhci-msm-v4";
290 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
291 reg-names = "hc_mem", "core_mem";
292 interrupts = <0 123 0>, <0 138 0>;
293 interrupt-names = "hc_irq", "pwr_irq";
294 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
295 clock-names = "core", "iface";
300 compatible = "qcom,sdhci-msm-v4";
301 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
302 reg-names = "hc_mem", "core_mem";
303 interrupts = <0 125 0>, <0 221 0>;
304 interrupt-names = "hc_irq", "pwr_irq";
305 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
306 clock-names = "core", "iface";
310 spmi_bus: spmi@fc4cf000 {
311 compatible = "qcom,spmi-pmic-arb";
312 reg-names = "core", "intr", "cnfg";
313 reg = <0xfc4cf000 0x1000>,
316 interrupt-names = "periph_irq";
317 interrupts = <0 190 0>;
320 #address-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <4>;
328 compatible = "qcom,smd";
331 interrupts = <0 168 1>;
332 qcom,ipc = <&apcs 8 0>;
333 qcom,smd-edge = <15>;
336 compatible = "qcom,rpm-apq8084";
337 qcom,smd-channels = "rpm_requests";
340 compatible = "qcom,rpm-pma8084-regulators";
383 pma8084_lvs1: lvs1 {};
384 pma8084_lvs2: lvs2 {};
385 pma8084_lvs3: lvs3 {};
386 pma8084_lvs4: lvs4 {};
388 pma8084_5vs1: 5vs1 {};