3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
11 model = "Qualcomm MSM8660";
12 compatible = "qcom,msm8660";
13 interrupt-parent = <&intc>;
20 compatible = "qcom,scorpion";
21 enable-method = "qcom,gcc-msm8660";
24 next-level-cache = <&L2>;
28 compatible = "qcom,scorpion";
29 enable-method = "qcom,gcc-msm8660";
32 next-level-cache = <&L2>;
42 compatible = "qcom,scorpion-mp-pmu";
43 interrupts = <1 9 0x304>;
48 compatible = "fixed-clock";
50 clock-frequency = <19200000>;
54 compatible = "fixed-clock";
56 clock-frequency = <27000000>;
60 compatible = "fixed-clock";
62 clock-frequency = <32768>;
67 * These channels from the ADC are simply hardware monitors.
68 * That is why the ADC is referred to as "HKADC" - HouseKeeping
72 compatible = "iio-hwmon";
73 io-channels = <&xoadc 0x00 0x01>, /* Battery */
74 <&xoadc 0x00 0x02>, /* DC in (charger) */
75 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
76 <&xoadc 0x00 0x0b>, /* Die temperature */
77 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
78 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
79 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
86 compatible = "simple-bus";
88 intc: interrupt-controller@2080000 {
89 compatible = "qcom,msm-8660-qgic";
91 #interrupt-cells = <3>;
92 reg = < 0x02080000 0x1000 >,
93 < 0x02081000 0x1000 >;
97 compatible = "qcom,scss-timer", "qcom,msm-timer";
98 interrupts = <1 0 0x301>,
101 reg = <0x02000000 0x100>;
102 clock-frequency = <27000000>,
104 cpu-offset = <0x40000>;
107 tlmm: pinctrl@800000 {
108 compatible = "qcom,msm8660-pinctrl";
109 reg = <0x800000 0x4000>;
113 interrupts = <0 16 0x4>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
119 gcc: clock-controller@900000 {
120 compatible = "qcom,gcc-msm8660";
123 reg = <0x900000 0x4000>;
127 gsbi8: gsbi@19800000 {
128 compatible = "qcom,gsbi-v1.0.0";
130 reg = <0x19800000 0x100>;
131 clocks = <&gcc GSBI8_H_CLK>;
132 clock-names = "iface";
133 #address-cells = <1>;
137 syscon-tcsr = <&tcsr>;
139 gsbi8_i2c: i2c@19880000 {
140 compatible = "qcom,i2c-qup-v1.1.1";
141 reg = <0x19880000 0x1000>;
142 interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
143 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
144 clock-names = "core", "iface";
145 #address-cells = <1>;
151 gsbi12: gsbi@19c00000 {
152 compatible = "qcom,gsbi-v1.0.0";
154 reg = <0x19c00000 0x100>;
155 clocks = <&gcc GSBI12_H_CLK>;
156 clock-names = "iface";
157 #address-cells = <1>;
161 syscon-tcsr = <&tcsr>;
163 gsbi12_serial: serial@19c40000 {
164 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
165 reg = <0x19c40000 0x1000>,
167 interrupts = <0 195 IRQ_TYPE_NONE>;
168 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
169 clock-names = "core", "iface";
173 gsbi12_i2c: i2c@19c80000 {
174 compatible = "qcom,i2c-qup-v1.1.1";
175 reg = <0x19c80000 0x1000>;
176 interrupts = <0 196 IRQ_TYPE_NONE>;
177 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
178 clock-names = "core", "iface";
179 #address-cells = <1>;
185 external-bus@1a100000 {
186 compatible = "qcom,msm8660-ebi2";
187 #address-cells = <2>;
189 ranges = <0 0x0 0x1a800000 0x00800000>,
190 <1 0x0 0x1b000000 0x00800000>,
191 <2 0x0 0x1b800000 0x00800000>,
192 <3 0x0 0x1d000000 0x08000000>,
193 <4 0x0 0x1c800000 0x00800000>,
194 <5 0x0 0x1c000000 0x00800000>;
195 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
196 reg-names = "ebi2", "xmem";
197 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
198 clock-names = "ebi2x", "ebi2";
203 compatible = "qcom,ssbi";
204 reg = <0x500000 0x1000>;
205 qcom,controller-type = "pmic-arbiter";
208 compatible = "qcom,pm8058";
209 interrupt-parent = <&tlmm>;
211 #interrupt-cells = <2>;
212 interrupt-controller;
213 #address-cells = <1>;
216 pm8058_gpio: gpio@150 {
217 compatible = "qcom,pm8058-gpio",
220 interrupt-parent = <&pm8058>;
221 interrupts = <192 IRQ_TYPE_NONE>,
270 pm8058_mpps: mpps@50 {
271 compatible = "qcom,pm8058-mpp",
276 interrupt-parent = <&pm8058>;
293 compatible = "qcom,pm8058-pwrkey";
295 interrupt-parent = <&pm8058>;
296 interrupts = <50 1>, <51 1>;
302 compatible = "qcom,pm8058-keypad";
304 interrupt-parent = <&pm8058>;
305 interrupts = <74 1>, <75 1>;
312 compatible = "qcom,pm8058-adc";
314 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
315 #address-cells = <2>;
317 #io-channel-cells = <2>;
319 vcoin: adc-channel@00 {
322 vbat: adc-channel@01 {
325 dcin: adc-channel@02 {
328 ichg: adc-channel@03 {
331 vph_pwr: adc-channel@04 {
334 usb_vbus: adc-channel@0a {
337 die_temp: adc-channel@0b {
340 ref_625mv: adc-channel@0c {
343 ref_1250mv: adc-channel@0d {
346 ref_325mv: adc-channel@0e {
349 ref_muxoff: adc-channel@0f {
355 compatible = "qcom,pm8058-rtc";
357 interrupt-parent = <&pm8058>;
363 compatible = "qcom,pm8058-vib";
369 l2cc: clock-controller@2082000 {
370 compatible = "syscon";
371 reg = <0x02082000 0x1000>;
375 compatible = "qcom,rpm-msm8660";
376 reg = <0x00104000 0x1000>;
377 qcom,ipc = <&l2cc 0x8 2>;
379 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
380 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
381 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
382 interrupt-names = "ack", "err", "wakeup";
383 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
386 rpmcc: clock-controller {
387 compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
392 compatible = "qcom,rpm-pm8901-regulators";
402 /* S0 and S1 Handled as SAW regulators by SPM */
407 pm8901_lvs0: lvs0 {};
408 pm8901_lvs1: lvs1 {};
409 pm8901_lvs2: lvs2 {};
410 pm8901_lvs3: lvs3 {};
416 compatible = "qcom,rpm-pm8058-regulators";
451 pm8058_lvs0: lvs0 {};
452 pm8058_lvs1: lvs1 {};
459 compatible = "simple-bus";
460 #address-cells = <1>;
463 sdcc1: sdcc@12400000 {
465 compatible = "arm,pl18x", "arm,primecell";
466 arm,primecell-periphid = <0x00051180>;
467 reg = <0x12400000 0x8000>;
468 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "cmd_irq";
470 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
471 clock-names = "mclk", "apb_pclk";
473 max-frequency = <48000000>;
479 sdcc2: sdcc@12140000 {
481 compatible = "arm,pl18x", "arm,primecell";
482 arm,primecell-periphid = <0x00051180>;
483 reg = <0x12140000 0x8000>;
484 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "cmd_irq";
486 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
487 clock-names = "mclk", "apb_pclk";
489 max-frequency = <48000000>;
494 sdcc3: sdcc@12180000 {
495 compatible = "arm,pl18x", "arm,primecell";
496 arm,primecell-periphid = <0x00051180>;
498 reg = <0x12180000 0x8000>;
499 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
500 interrupt-names = "cmd_irq";
501 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
502 clock-names = "mclk", "apb_pclk";
506 max-frequency = <48000000>;
510 sdcc4: sdcc@121c0000 {
511 compatible = "arm,pl18x", "arm,primecell";
512 arm,primecell-periphid = <0x00051180>;
514 reg = <0x121c0000 0x8000>;
515 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "cmd_irq";
517 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
518 clock-names = "mclk", "apb_pclk";
520 max-frequency = <48000000>;
525 sdcc5: sdcc@12200000 {
526 compatible = "arm,pl18x", "arm,primecell";
527 arm,primecell-periphid = <0x00051180>;
529 reg = <0x12200000 0x8000>;
530 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
531 interrupt-names = "cmd_irq";
532 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
533 clock-names = "mclk", "apb_pclk";
537 max-frequency = <48000000>;
541 tcsr: syscon@1a400000 {
542 compatible = "qcom,tcsr-msm8660", "syscon";
543 reg = <0x1a400000 0x100>;