3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
7 #include <dt-bindings/mfd/qcom-rpm.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
11 model = "Qualcomm MSM8960";
12 compatible = "qcom,msm8960";
13 interrupt-parent = <&intc>;
18 interrupts = <1 14 0x304>;
21 compatible = "qcom,krait";
22 enable-method = "qcom,kpss-acc-v1";
25 next-level-cache = <&L2>;
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
35 next-level-cache = <&L2>;
47 compatible = "qcom,krait-pmu";
48 interrupts = <1 10 0x304>;
54 compatible = "fixed-clock";
56 clock-frequency = <19200000>;
57 clock-output-names = "cxo_board";
61 compatible = "fixed-clock";
63 clock-frequency = <27000000>;
64 clock-output-names = "pxo_board";
68 compatible = "fixed-clock";
70 clock-frequency = <32768>;
71 clock-output-names = "sleep_clk";
79 compatible = "simple-bus";
81 intc: interrupt-controller@2000000 {
82 compatible = "qcom,msm-qgic2";
84 #interrupt-cells = <3>;
85 reg = <0x02000000 0x1000>,
90 compatible = "qcom,kpss-timer", "qcom,msm-timer";
91 interrupts = <1 1 0x301>,
94 reg = <0x0200a000 0x100>;
95 clock-frequency = <27000000>,
97 cpu-offset = <0x80000>;
100 msmgpio: pinctrl@800000 {
101 compatible = "qcom,msm8960-pinctrl";
104 interrupts = <0 16 0x4>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 reg = <0x800000 0x4000>;
110 gcc: clock-controller@900000 {
111 compatible = "qcom,gcc-msm8960";
114 reg = <0x900000 0x4000>;
117 lcc: clock-controller@28000000 {
118 compatible = "qcom,lcc-msm8960";
119 reg = <0x28000000 0x1000>;
124 clock-controller@4000000 {
125 compatible = "qcom,mmcc-msm8960";
126 reg = <0x4000000 0x1000>;
131 l2cc: clock-controller@2011000 {
132 compatible = "syscon";
133 reg = <0x2011000 0x1000>;
137 compatible = "qcom,rpm-msm8960";
138 reg = <0x108000 0x1000>;
139 qcom,ipc = <&l2cc 0x8 2>;
141 interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
142 interrupt-names = "ack", "err", "wakeup";
145 compatible = "qcom,rpm-pm8921-regulators";
149 acc0: clock-controller@2088000 {
150 compatible = "qcom,kpss-acc-v1";
151 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
154 acc1: clock-controller@2098000 {
155 compatible = "qcom,kpss-acc-v1";
156 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
159 saw0: regulator@2089000 {
160 compatible = "qcom,saw2";
161 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
165 saw1: regulator@2099000 {
166 compatible = "qcom,saw2";
167 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
171 gsbi5: gsbi@16400000 {
172 compatible = "qcom,gsbi-v1.0.0";
174 reg = <0x16400000 0x100>;
175 clocks = <&gcc GSBI5_H_CLK>;
176 clock-names = "iface";
177 #address-cells = <1>;
181 syscon-tcsr = <&tcsr>;
183 gsbi5_serial: serial@16440000 {
184 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
185 reg = <0x16440000 0x1000>,
187 interrupts = <0 154 0x0>;
188 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
189 clock-names = "core", "iface";
195 compatible = "qcom,ssbi";
196 reg = <0x500000 0x1000>;
197 qcom,controller-type = "pmic-arbiter";
200 compatible = "qcom,pm8921";
201 interrupt-parent = <&msmgpio>;
202 interrupts = <104 8>;
203 #interrupt-cells = <2>;
204 interrupt-controller;
205 #address-cells = <1>;
209 compatible = "qcom,pm8921-pwrkey";
211 interrupt-parent = <&pmicintc>;
212 interrupts = <50 1>, <51 1>;
218 compatible = "qcom,pm8921-keypad";
220 interrupt-parent = <&pmicintc>;
221 interrupts = <74 1>, <75 1>;
228 compatible = "qcom,pm8921-rtc";
229 interrupt-parent = <&pmicintc>;
238 compatible = "qcom,prng";
239 reg = <0x1a500000 0x200>;
240 clocks = <&gcc PRNG_CLK>;
241 clock-names = "core";
244 /* Temporary fixed regulator */
245 vsdcc_fixed: vsdcc-regulator {
246 compatible = "regulator-fixed";
247 regulator-name = "SDCC Power";
248 regulator-min-microvolt = <2700000>;
249 regulator-max-microvolt = <2700000>;
254 compatible = "simple-bus";
255 #address-cells = <1>;
258 sdcc1: sdcc@12400000 {
260 compatible = "arm,pl18x", "arm,primecell";
261 arm,primecell-periphid = <0x00051180>;
262 reg = <0x12400000 0x8000>;
263 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
264 interrupt-names = "cmd_irq";
265 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
266 clock-names = "mclk", "apb_pclk";
268 max-frequency = <96000000>;
272 vmmc-supply = <&vsdcc_fixed>;
275 sdcc3: sdcc@12180000 {
276 compatible = "arm,pl18x", "arm,primecell";
277 arm,primecell-periphid = <0x00051180>;
279 reg = <0x12180000 0x8000>;
280 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "cmd_irq";
282 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
283 clock-names = "mclk", "apb_pclk";
287 max-frequency = <192000000>;
289 vmmc-supply = <&vsdcc_fixed>;
293 tcsr: syscon@1a400000 {
294 compatible = "qcom,tcsr-msm8960", "syscon";
295 reg = <0x1a400000 0x100>;
299 compatible = "qcom,gsbi-v1.0.0";
301 reg = <0x16000000 0x100>;
302 clocks = <&gcc GSBI1_H_CLK>;
303 clock-names = "iface";
304 #address-cells = <1>;
309 compatible = "qcom,spi-qup-v1.1.1";
310 #address-cells = <1>;
312 reg = <0x16080000 0x1000>;
313 interrupts = <0 147 0>;
314 spi-max-frequency = <24000000>;
315 cs-gpios = <&msmgpio 8 0>;
317 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
318 clock-names = "core", "iface";