arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include <dt-bindings/clock/qcom,rpmcc.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include "skeleton.dtsi"
   8
   9 / {
  10         model = "Qualcomm MSM8974";
  11         compatible = "qcom,msm8974";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 mpss@08000000 {
  20                         reg = <0x08000000 0x5100000>;
  21                         no-map;
  22                 };
  23
  24                 mba@00d100000 {
  25                         reg = <0x0d100000 0x100000>;
  26                         no-map;
  27                 };
  28
  29                 reserved@0d200000 {
  30                         reg = <0x0d200000 0xa00000>;
  31                         no-map;
  32                 };
  33
  34                 adsp_region: adsp@0dc00000 {
  35                         reg = <0x0dc00000 0x1900000>;
  36                         no-map;
  37                 };
  38
  39                 venus@0f500000 {
  40                         reg = <0x0f500000 0x500000>;
  41                         no-map;
  42                 };
  43
  44                 smem_region: smem@fa00000 {
  45                         reg = <0xfa00000 0x200000>;
  46                         no-map;
  47                 };
  48
  49                 tz@0fc00000 {
  50                         reg = <0x0fc00000 0x160000>;
  51                         no-map;
  52                 };
  53
  54                 rfsa@0fd60000 {
  55                         reg = <0x0fd60000 0x20000>;
  56                         no-map;
  57                 };
  58
  59                 rmtfs@0fd80000 {
  60                         reg = <0x0fd80000 0x180000>;
  61                         no-map;
  62                 };
  63         };
  64
  65         cpus {
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68                 interrupts = <1 9 0xf04>;
  69
  70                 CPU0: cpu@0 {
  71                         compatible = "qcom,krait";
  72                         enable-method = "qcom,kpss-acc-v2";
  73                         device_type = "cpu";
  74                         reg = <0>;
  75                         next-level-cache = <&L2>;
  76                         qcom,acc = <&acc0>;
  77                         qcom,saw = <&saw0>;
  78                         cpu-idle-states = <&CPU_SPC>;
  79                 };
  80
  81                 CPU1: cpu@1 {
  82                         compatible = "qcom,krait";
  83                         enable-method = "qcom,kpss-acc-v2";
  84                         device_type = "cpu";
  85                         reg = <1>;
  86                         next-level-cache = <&L2>;
  87                         qcom,acc = <&acc1>;
  88                         qcom,saw = <&saw1>;
  89                         cpu-idle-states = <&CPU_SPC>;
  90                 };
  91
  92                 CPU2: cpu@2 {
  93                         compatible = "qcom,krait";
  94                         enable-method = "qcom,kpss-acc-v2";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                         next-level-cache = <&L2>;
  98                         qcom,acc = <&acc2>;
  99                         qcom,saw = <&saw2>;
 100                         cpu-idle-states = <&CPU_SPC>;
 101                 };
 102
 103                 CPU3: cpu@3 {
 104                         compatible = "qcom,krait";
 105                         enable-method = "qcom,kpss-acc-v2";
 106                         device_type = "cpu";
 107                         reg = <3>;
 108                         next-level-cache = <&L2>;
 109                         qcom,acc = <&acc3>;
 110                         qcom,saw = <&saw3>;
 111                         cpu-idle-states = <&CPU_SPC>;
 112                 };
 113
 114                 L2: l2-cache {
 115                         compatible = "cache";
 116                         cache-level = <2>;
 117                         qcom,saw = <&saw_l2>;
 118                 };
 119
 120                 idle-states {
 121                         CPU_SPC: spc {
 122                                 compatible = "qcom,idle-state-spc",
 123                                                 "arm,idle-state";
 124                                 entry-latency-us = <150>;
 125                                 exit-latency-us = <200>;
 126                                 min-residency-us = <2000>;
 127                         };
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 cpu-thermal0 {
 133                         polling-delay-passive = <250>;
 134                         polling-delay = <1000>;
 135
 136                         thermal-sensors = <&tsens 5>;
 137
 138                         trips {
 139                                 cpu_alert0: trip0 {
 140                                         temperature = <75000>;
 141                                         hysteresis = <2000>;
 142                                         type = "passive";
 143                                 };
 144                                 cpu_crit0: trip1 {
 145                                         temperature = <110000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150                 };
 151
 152                 cpu-thermal1 {
 153                         polling-delay-passive = <250>;
 154                         polling-delay = <1000>;
 155
 156                         thermal-sensors = <&tsens 6>;
 157
 158                         trips {
 159                                 cpu_alert1: trip0 {
 160                                         temperature = <75000>;
 161                                         hysteresis = <2000>;
 162                                         type = "passive";
 163                                 };
 164                                 cpu_crit1: trip1 {
 165                                         temperature = <110000>;
 166                                         hysteresis = <2000>;
 167                                         type = "critical";
 168                                 };
 169                         };
 170                 };
 171
 172                 cpu-thermal2 {
 173                         polling-delay-passive = <250>;
 174                         polling-delay = <1000>;
 175
 176                         thermal-sensors = <&tsens 7>;
 177
 178                         trips {
 179                                 cpu_alert2: trip0 {
 180                                         temperature = <75000>;
 181                                         hysteresis = <2000>;
 182                                         type = "passive";
 183                                 };
 184                                 cpu_crit2: trip1 {
 185                                         temperature = <110000>;
 186                                         hysteresis = <2000>;
 187                                         type = "critical";
 188                                 };
 189                         };
 190                 };
 191
 192                 cpu-thermal3 {
 193                         polling-delay-passive = <250>;
 194                         polling-delay = <1000>;
 195
 196                         thermal-sensors = <&tsens 8>;
 197
 198                         trips {
 199                                 cpu_alert3: trip0 {
 200                                         temperature = <75000>;
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                                 cpu_crit3: trip1 {
 205                                         temperature = <110000>;
 206                                         hysteresis = <2000>;
 207                                         type = "critical";
 208                                 };
 209                         };
 210                 };
 211         };
 212
 213         cpu-pmu {
 214                 compatible = "qcom,krait-pmu";
 215                 interrupts = <1 7 0xf04>;
 216         };
 217
 218         clocks {
 219                 xo_board: xo_board {
 220                         compatible = "fixed-clock";
 221                         #clock-cells = <0>;
 222                         clock-frequency = <19200000>;
 223                 };
 224
 225                 sleep_clk: sleep_clk {
 226                         compatible = "fixed-clock";
 227                         #clock-cells = <0>;
 228                         clock-frequency = <32768>;
 229                 };
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv7-timer";
 234                 interrupts = <1 2 0xf08>,
 235                              <1 3 0xf08>,
 236                              <1 4 0xf08>,
 237                              <1 1 0xf08>;
 238                 clock-frequency = <19200000>;
 239         };
 240
 241         adsp-pil {
 242                 compatible = "qcom,msm8974-adsp-pil";
 243
 244                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
 245                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 246                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 247                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 248                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 249                 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 250
 251                 cx-supply = <&pm8841_s2>;
 252
 253                 clocks = <&xo_board>;
 254                 clock-names = "xo";
 255
 256                 memory-region = <&adsp_region>;
 257
 258                 qcom,smem-states = <&adsp_smp2p_out 0>;
 259                 qcom,smem-state-names = "stop";
 260         };
 261
 262         smem {
 263                 compatible = "qcom,smem";
 264
 265                 memory-region = <&smem_region>;
 266                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 267
 268                 hwlocks = <&tcsr_mutex 3>;
 269         };
 270
 271         smp2p-adsp {
 272                 compatible = "qcom,smp2p";
 273                 qcom,smem = <443>, <429>;
 274
 275                 interrupt-parent = <&intc>;
 276                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 277
 278                 qcom,ipc = <&apcs 8 10>;
 279
 280                 qcom,local-pid = <0>;
 281                 qcom,remote-pid = <2>;
 282
 283                 adsp_smp2p_out: master-kernel {
 284                         qcom,entry-name = "master-kernel";
 285                         #qcom,smem-state-cells = <1>;
 286                 };
 287
 288                 adsp_smp2p_in: slave-kernel {
 289                         qcom,entry-name = "slave-kernel";
 290
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                 };
 294         };
 295
 296         smp2p-modem {
 297                 compatible = "qcom,smp2p";
 298                 qcom,smem = <435>, <428>;
 299
 300                 interrupt-parent = <&intc>;
 301                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
 302
 303                 qcom,ipc = <&apcs 8 14>;
 304
 305                 qcom,local-pid = <0>;
 306                 qcom,remote-pid = <1>;
 307
 308                 modem_smp2p_out: master-kernel {
 309                         qcom,entry-name = "master-kernel";
 310                         #qcom,smem-state-cells = <1>;
 311                 };
 312
 313                 modem_smp2p_in: slave-kernel {
 314                         qcom,entry-name = "slave-kernel";
 315
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319         };
 320
 321         smp2p-wcnss {
 322                 compatible = "qcom,smp2p";
 323                 qcom,smem = <451>, <431>;
 324
 325                 interrupt-parent = <&intc>;
 326                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 327
 328                 qcom,ipc = <&apcs 8 18>;
 329
 330                 qcom,local-pid = <0>;
 331                 qcom,remote-pid = <4>;
 332
 333                 wcnss_smp2p_out: master-kernel {
 334                         qcom,entry-name = "master-kernel";
 335
 336                         #qcom,smem-state-cells = <1>;
 337                 };
 338
 339                 wcnss_smp2p_in: slave-kernel {
 340                         qcom,entry-name = "slave-kernel";
 341
 342                         interrupt-controller;
 343                         #interrupt-cells = <2>;
 344                 };
 345         };
 346
 347         smsm {
 348                 compatible = "qcom,smsm";
 349
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352
 353                 qcom,ipc-1 = <&apcs 8 13>;
 354                 qcom,ipc-2 = <&apcs 8 9>;
 355                 qcom,ipc-3 = <&apcs 8 19>;
 356
 357                 apps_smsm: apps@0 {
 358                         reg = <0>;
 359
 360                         #qcom,smem-state-cells = <1>;
 361                 };
 362
 363                 modem_smsm: modem@1 {
 364                         reg = <1>;
 365                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 366
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 adsp_smsm: adsp@2 {
 372                         reg = <2>;
 373                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 374
 375                         interrupt-controller;
 376                         #interrupt-cells = <2>;
 377                 };
 378
 379                 wcnss_smsm: wcnss@7 {
 380                         reg = <7>;
 381                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 382
 383                         interrupt-controller;
 384                         #interrupt-cells = <2>;
 385                 };
 386         };
 387
 388         firmware {
 389                 scm {
 390                         compatible = "qcom,scm";
 391                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 392                         clock-names = "core", "bus", "iface";
 393                 };
 394         };
 395
 396         soc: soc {
 397                 #address-cells = <1>;
 398                 #size-cells = <1>;
 399                 ranges;
 400                 compatible = "simple-bus";
 401
 402                 intc: interrupt-controller@f9000000 {
 403                         compatible = "qcom,msm-qgic2";
 404                         interrupt-controller;
 405                         #interrupt-cells = <3>;
 406                         reg = <0xf9000000 0x1000>,
 407                               <0xf9002000 0x1000>;
 408                 };
 409
 410                 apcs: syscon@f9011000 {
 411                         compatible = "syscon";
 412                         reg = <0xf9011000 0x1000>;
 413                 };
 414
 415                 qfprom: qfprom@fc4bc000 {
 416                         #address-cells = <1>;
 417                         #size-cells = <1>;
 418                         compatible = "qcom,qfprom";
 419                         reg = <0xfc4bc000 0x1000>;
 420                         tsens_calib: calib@d0 {
 421                                 reg = <0xd0 0x18>;
 422                         };
 423                         tsens_backup: backup@440 {
 424                                 reg = <0x440 0x10>;
 425                         };
 426                 };
 427
 428                 tsens: thermal-sensor@fc4a8000 {
 429                         compatible = "qcom,msm8974-tsens";
 430                         reg = <0xfc4a8000 0x2000>;
 431                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 432                         nvmem-cell-names = "calib", "calib_backup";
 433                         #thermal-sensor-cells = <1>;
 434                 };
 435
 436                 timer@f9020000 {
 437                         #address-cells = <1>;
 438                         #size-cells = <1>;
 439                         ranges;
 440                         compatible = "arm,armv7-timer-mem";
 441                         reg = <0xf9020000 0x1000>;
 442                         clock-frequency = <19200000>;
 443
 444                         frame@f9021000 {
 445                                 frame-number = <0>;
 446                                 interrupts = <0 8 0x4>,
 447                                              <0 7 0x4>;
 448                                 reg = <0xf9021000 0x1000>,
 449                                       <0xf9022000 0x1000>;
 450                         };
 451
 452                         frame@f9023000 {
 453                                 frame-number = <1>;
 454                                 interrupts = <0 9 0x4>;
 455                                 reg = <0xf9023000 0x1000>;
 456                                 status = "disabled";
 457                         };
 458
 459                         frame@f9024000 {
 460                                 frame-number = <2>;
 461                                 interrupts = <0 10 0x4>;
 462                                 reg = <0xf9024000 0x1000>;
 463                                 status = "disabled";
 464                         };
 465
 466                         frame@f9025000 {
 467                                 frame-number = <3>;
 468                                 interrupts = <0 11 0x4>;
 469                                 reg = <0xf9025000 0x1000>;
 470                                 status = "disabled";
 471                         };
 472
 473                         frame@f9026000 {
 474                                 frame-number = <4>;
 475                                 interrupts = <0 12 0x4>;
 476                                 reg = <0xf9026000 0x1000>;
 477                                 status = "disabled";
 478                         };
 479
 480                         frame@f9027000 {
 481                                 frame-number = <5>;
 482                                 interrupts = <0 13 0x4>;
 483                                 reg = <0xf9027000 0x1000>;
 484                                 status = "disabled";
 485                         };
 486
 487                         frame@f9028000 {
 488                                 frame-number = <6>;
 489                                 interrupts = <0 14 0x4>;
 490                                 reg = <0xf9028000 0x1000>;
 491                                 status = "disabled";
 492                         };
 493                 };
 494
 495                 saw0: power-controller@f9089000 {
 496                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 497                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 498                 };
 499
 500                 saw1: power-controller@f9099000 {
 501                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 502                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 503                 };
 504
 505                 saw2: power-controller@f90a9000 {
 506                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 507                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 508                 };
 509
 510                 saw3: power-controller@f90b9000 {
 511                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 512                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 513                 };
 514
 515                 saw_l2: power-controller@f9012000 {
 516                         compatible = "qcom,saw2";
 517                         reg = <0xf9012000 0x1000>;
 518                         regulator;
 519                 };
 520
 521                 acc0: clock-controller@f9088000 {
 522                         compatible = "qcom,kpss-acc-v2";
 523                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 524                 };
 525
 526                 acc1: clock-controller@f9098000 {
 527                         compatible = "qcom,kpss-acc-v2";
 528                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 529                 };
 530
 531                 acc2: clock-controller@f90a8000 {
 532                         compatible = "qcom,kpss-acc-v2";
 533                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 534                 };
 535
 536                 acc3: clock-controller@f90b8000 {
 537                         compatible = "qcom,kpss-acc-v2";
 538                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 539                 };
 540
 541                 restart@fc4ab000 {
 542                         compatible = "qcom,pshold";
 543                         reg = <0xfc4ab000 0x4>;
 544                 };
 545
 546                 gcc: clock-controller@fc400000 {
 547                         compatible = "qcom,gcc-msm8974";
 548                         #clock-cells = <1>;
 549                         #reset-cells = <1>;
 550                         #power-domain-cells = <1>;
 551                         reg = <0xfc400000 0x4000>;
 552                 };
 553
 554                 tcsr_mutex_block: syscon@fd484000 {
 555                         compatible = "syscon";
 556                         reg = <0xfd484000 0x2000>;
 557                 };
 558
 559                 mmcc: clock-controller@fd8c0000 {
 560                         compatible = "qcom,mmcc-msm8974";
 561                         #clock-cells = <1>;
 562                         #reset-cells = <1>;
 563                         #power-domain-cells = <1>;
 564                         reg = <0xfd8c0000 0x6000>;
 565                 };
 566
 567                 tcsr_mutex: tcsr-mutex {
 568                         compatible = "qcom,tcsr-mutex";
 569                         syscon = <&tcsr_mutex_block 0 0x80>;
 570
 571                         #hwlock-cells = <1>;
 572                 };
 573
 574                 rpm_msg_ram: memory@fc428000 {
 575                         compatible = "qcom,rpm-msg-ram";
 576                         reg = <0xfc428000 0x4000>;
 577                 };
 578
 579                 blsp1_uart1: serial@f991d000 {
 580                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 581                         reg = <0xf991d000 0x1000>;
 582                         interrupts = <0 107 0x0>;
 583                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 584                         clock-names = "core", "iface";
 585                         status = "disabled";
 586                 };
 587
 588                 blsp1_uart2: serial@f991e000 {
 589                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 590                         reg = <0xf991e000 0x1000>;
 591                         interrupts = <0 108 0x0>;
 592                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 593                         clock-names = "core", "iface";
 594                         status = "disabled";
 595                 };
 596
 597                 sdhci@f9824900 {
 598                         compatible = "qcom,sdhci-msm-v4";
 599                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 600                         reg-names = "hc_mem", "core_mem";
 601                         interrupts = <0 123 0>, <0 138 0>;
 602                         interrupt-names = "hc_irq", "pwr_irq";
 603                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 604                                  <&gcc GCC_SDCC1_AHB_CLK>,
 605                                  <&xo_board>;
 606                         clock-names = "core", "iface", "xo";
 607                         status = "disabled";
 608                 };
 609
 610                 sdhci@f98a4900 {
 611                         compatible = "qcom,sdhci-msm-v4";
 612                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 613                         reg-names = "hc_mem", "core_mem";
 614                         interrupts = <0 125 0>, <0 221 0>;
 615                         interrupt-names = "hc_irq", "pwr_irq";
 616                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 617                                  <&gcc GCC_SDCC2_AHB_CLK>,
 618                                  <&xo_board>;
 619                         clock-names = "core", "iface", "xo";
 620                         status = "disabled";
 621                 };
 622
 623                 rng@f9bff000 {
 624                         compatible = "qcom,prng";
 625                         reg = <0xf9bff000 0x200>;
 626                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 627                         clock-names = "core";
 628                 };
 629
 630                 msmgpio: pinctrl@fd510000 {
 631                         compatible = "qcom,msm8974-pinctrl";
 632                         reg = <0xfd510000 0x4000>;
 633                         gpio-controller;
 634                         #gpio-cells = <2>;
 635                         interrupt-controller;
 636                         #interrupt-cells = <2>;
 637                         interrupts = <0 208 0>;
 638                 };
 639
 640                 i2c@f9924000 {
 641                         status = "disabled";
 642                         compatible = "qcom,i2c-qup-v2.1.1";
 643                         reg = <0xf9924000 0x1000>;
 644                         interrupts = <0 96 IRQ_TYPE_NONE>;
 645                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 646                         clock-names = "core", "iface";
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649                 };
 650
 651                 blsp_i2c8: i2c@f9964000 {
 652                         status = "disabled";
 653                         compatible = "qcom,i2c-qup-v2.1.1";
 654                         reg = <0xf9964000 0x1000>;
 655                         interrupts = <0 102 IRQ_TYPE_NONE>;
 656                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 657                         clock-names = "core", "iface";
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                 };
 661
 662                 blsp_i2c11: i2c@f9967000 {
 663                         status = "disabled";
 664                         compatible = "qcom,i2c-qup-v2.1.1";
 665                         reg = <0xf9967000 0x1000>;
 666                         interrupts = <0 105 IRQ_TYPE_NONE>;
 667                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 668                         clock-names = "core", "iface";
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 672                         dma-names = "tx", "rx";
 673                 };
 674
 675                 spmi_bus: spmi@fc4cf000 {
 676                         compatible = "qcom,spmi-pmic-arb";
 677                         reg-names = "core", "intr", "cnfg";
 678                         reg = <0xfc4cf000 0x1000>,
 679                               <0xfc4cb000 0x1000>,
 680                               <0xfc4ca000 0x1000>;
 681                         interrupt-names = "periph_irq";
 682                         interrupts = <0 190 0>;
 683                         qcom,ee = <0>;
 684                         qcom,channel = <0>;
 685                         #address-cells = <2>;
 686                         #size-cells = <0>;
 687                         interrupt-controller;
 688                         #interrupt-cells = <4>;
 689                 };
 690
 691                 blsp2_dma: dma-controller@f9944000 {
 692                         compatible = "qcom,bam-v1.4.0";
 693                         reg = <0xf9944000 0x19000>;
 694                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 696                         clock-names = "bam_clk";
 697                         #dma-cells = <1>;
 698                         qcom,ee = <0>;
 699                 };
 700
 701                 etr@fc322000 {
 702                         compatible = "arm,coresight-tmc", "arm,primecell";
 703                         reg = <0xfc322000 0x1000>;
 704
 705                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 706                         clock-names = "apb_pclk", "atclk";
 707
 708                         port {
 709                                 etr_in: endpoint {
 710                                         slave-mode;
 711                                         remote-endpoint = <&replicator_out0>;
 712                                 };
 713                         };
 714                 };
 715
 716                 tpiu@fc318000 {
 717                         compatible = "arm,coresight-tpiu", "arm,primecell";
 718                         reg = <0xfc318000 0x1000>;
 719
 720                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 721                         clock-names = "apb_pclk", "atclk";
 722
 723                         port {
 724                                 tpiu_in: endpoint {
 725                                          slave-mode;
 726                                          remote-endpoint = <&replicator_out1>;
 727                                  };
 728                         };
 729                 };
 730
 731                 replicator@fc31c000 {
 732                         compatible = "qcom,coresight-replicator1x", "arm,primecell";
 733                         reg = <0xfc31c000 0x1000>;
 734
 735                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 736                         clock-names = "apb_pclk", "atclk";
 737
 738                         ports {
 739                                 #address-cells = <1>;
 740                                 #size-cells = <0>;
 741
 742                                 port@0 {
 743                                         reg = <0>;
 744                                         replicator_out0: endpoint {
 745                                                 remote-endpoint = <&etr_in>;
 746                                         };
 747                                 };
 748                                 port@1 {
 749                                         reg = <1>;
 750                                         replicator_out1: endpoint {
 751                                                 remote-endpoint = <&tpiu_in>;
 752                                         };
 753                                 };
 754                                 port@2 {
 755                                         reg = <0>;
 756                                         replicator_in: endpoint {
 757                                                 slave-mode;
 758                                                 remote-endpoint = <&etf_out>;
 759                                         };
 760                                 };
 761                         };
 762                 };
 763
 764                 etf@fc307000 {
 765                         compatible = "arm,coresight-tmc", "arm,primecell";
 766                         reg = <0xfc307000 0x1000>;
 767
 768                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 769                         clock-names = "apb_pclk", "atclk";
 770
 771                         ports {
 772                                 #address-cells = <1>;
 773                                 #size-cells = <0>;
 774
 775                                 port@0 {
 776                                         reg = <0>;
 777                                         etf_out: endpoint {
 778                                                 remote-endpoint = <&replicator_in>;
 779                                         };
 780                                 };
 781                                 port@1 {
 782                                         reg = <0>;
 783                                         etf_in: endpoint {
 784                                                 slave-mode;
 785                                                 remote-endpoint = <&merger_out>;
 786                                         };
 787                                 };
 788                         };
 789                 };
 790
 791                 funnel@fc31b000 {
 792                         compatible = "arm,coresight-funnel", "arm,primecell";
 793                         reg = <0xfc31b000 0x1000>;
 794
 795                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 796                         clock-names = "apb_pclk", "atclk";
 797
 798                         ports {
 799                                 #address-cells = <1>;
 800                                 #size-cells = <0>;
 801
 802                                 /*
 803                                  * Not described input ports:
 804                                  * 0 - connected trought funnel to Audio, Modem and
 805                                  *     Resource and Power Manager CPU's
 806                                  * 2...7 - not-connected
 807                                  */
 808                                 port@1 {
 809                                         reg = <1>;
 810                                         merger_in1: endpoint {
 811                                                 slave-mode;
 812                                                 remote-endpoint = <&funnel1_out>;
 813                                         };
 814                                 };
 815                                 port@8 {
 816                                         reg = <0>;
 817                                         merger_out: endpoint {
 818                                                 remote-endpoint = <&etf_in>;
 819                                         };
 820                                 };
 821                         };
 822                 };
 823
 824                 funnel@fc31a000 {
 825                         compatible = "arm,coresight-funnel", "arm,primecell";
 826                         reg = <0xfc31a000 0x1000>;
 827
 828                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 829                         clock-names = "apb_pclk", "atclk";
 830
 831                         ports {
 832                                 #address-cells = <1>;
 833                                 #size-cells = <0>;
 834
 835                                 /*
 836                                  * Not described input ports:
 837                                  * 0 - not-connected
 838                                  * 1 - connected trought funnel to Multimedia CPU
 839                                  * 2 - connected to Wireless CPU
 840                                  * 3 - not-connected
 841                                  * 4 - not-connected
 842                                  * 6 - not-connected
 843                                  * 7 - connected to STM
 844                                  */
 845                                 port@5 {
 846                                         reg = <5>;
 847                                         funnel1_in5: endpoint {
 848                                                 slave-mode;
 849                                                 remote-endpoint = <&kpss_out>;
 850                                         };
 851                                 };
 852                                 port@8 {
 853                                         reg = <0>;
 854                                         funnel1_out: endpoint {
 855                                                 remote-endpoint = <&merger_in1>;
 856                                         };
 857                                 };
 858                         };
 859                 };
 860
 861                 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
 862                         compatible = "arm,coresight-funnel", "arm,primecell";
 863                         reg = <0xfc345000 0x1000>;
 864
 865                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 866                         clock-names = "apb_pclk", "atclk";
 867
 868                         ports {
 869                                 #address-cells = <1>;
 870                                 #size-cells = <0>;
 871
 872                                 port@0 {
 873                                         reg = <0>;
 874                                         kpss_in0: endpoint {
 875                                                 slave-mode;
 876                                                 remote-endpoint = <&etm0_out>;
 877                                         };
 878                                 };
 879                                 port@1 {
 880                                         reg = <1>;
 881                                         kpss_in1: endpoint {
 882                                                 slave-mode;
 883                                                 remote-endpoint = <&etm1_out>;
 884                                         };
 885                                 };
 886                                 port@2 {
 887                                         reg = <2>;
 888                                         kpss_in2: endpoint {
 889                                                 slave-mode;
 890                                                 remote-endpoint = <&etm2_out>;
 891                                         };
 892                                 };
 893                                 port@3 {
 894                                         reg = <3>;
 895                                         kpss_in3: endpoint {
 896                                                 slave-mode;
 897                                                 remote-endpoint = <&etm3_out>;
 898                                         };
 899                                 };
 900                                 port@8 {
 901                                         reg = <0>;
 902                                         kpss_out: endpoint {
 903                                                 remote-endpoint = <&funnel1_in5>;
 904                                         };
 905                                 };
 906                         };
 907                 };
 908
 909                 etm@fc33c000 {
 910                         compatible = "arm,coresight-etm4x", "arm,primecell";
 911                         reg = <0xfc33c000 0x1000>;
 912
 913                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 914                         clock-names = "apb_pclk", "atclk";
 915
 916                         cpu = <&CPU0>;
 917
 918                         port {
 919                                 etm0_out: endpoint {
 920                                         remote-endpoint = <&kpss_in0>;
 921                                 };
 922                         };
 923                 };
 924
 925                 etm@fc33d000 {
 926                         compatible = "arm,coresight-etm4x", "arm,primecell";
 927                         reg = <0xfc33d000 0x1000>;
 928
 929                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 930                         clock-names = "apb_pclk", "atclk";
 931
 932                         cpu = <&CPU1>;
 933
 934                         port {
 935                                 etm1_out: endpoint {
 936                                         remote-endpoint = <&kpss_in1>;
 937                                 };
 938                         };
 939                 };
 940
 941                 etm@fc33e000 {
 942                         compatible = "arm,coresight-etm4x", "arm,primecell";
 943                         reg = <0xfc33e000 0x1000>;
 944
 945                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 946                         clock-names = "apb_pclk", "atclk";
 947
 948                         cpu = <&CPU2>;
 949
 950                         port {
 951                                 etm2_out: endpoint {
 952                                         remote-endpoint = <&kpss_in2>;
 953                                 };
 954                         };
 955                 };
 956
 957                 etm@fc33f000 {
 958                         compatible = "arm,coresight-etm4x", "arm,primecell";
 959                         reg = <0xfc33f000 0x1000>;
 960
 961                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 962                         clock-names = "apb_pclk", "atclk";
 963
 964                         cpu = <&CPU3>;
 965
 966                         port {
 967                                 etm3_out: endpoint {
 968                                         remote-endpoint = <&kpss_in3>;
 969                                 };
 970                         };
 971                 };
 972         };
 973
 974         smd {
 975                 compatible = "qcom,smd";
 976
 977                 adsp {
 978                         interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
 979
 980                         qcom,ipc = <&apcs 8 8>;
 981                         qcom,smd-edge = <1>;
 982                 };
 983
 984                 modem {
 985                         interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 986
 987                         qcom,ipc = <&apcs 8 12>;
 988                         qcom,smd-edge = <0>;
 989                 };
 990
 991                 rpm {
 992                         interrupts = <0 168 1>;
 993                         qcom,ipc = <&apcs 8 0>;
 994                         qcom,smd-edge = <15>;
 995
 996                         rpm_requests {
 997                                 compatible = "qcom,rpm-msm8974";
 998                                 qcom,smd-channels = "rpm_requests";
 999
1000                                 rpmcc: clock-controller {
1001                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1002                                         #clock-cells = <1>;
1003                                 };
1004
1005                                 pm8841-regulators {
1006                                         compatible = "qcom,rpm-pm8841-regulators";
1007
1008                                         pm8841_s1: s1 {};
1009                                         pm8841_s2: s2 {};
1010                                         pm8841_s3: s3 {};
1011                                         pm8841_s4: s4 {};
1012                                         pm8841_s5: s5 {};
1013                                         pm8841_s6: s6 {};
1014                                         pm8841_s7: s7 {};
1015                                         pm8841_s8: s8 {};
1016                                 };
1017
1018                                 pm8941-regulators {
1019                                         compatible = "qcom,rpm-pm8941-regulators";
1020
1021                                         pm8941_s1: s1 {};
1022                                         pm8941_s2: s2 {};
1023                                         pm8941_s3: s3 {};
1024                                         pm8941_5v: s4 {};
1025
1026                                         pm8941_l1: l1 {};
1027                                         pm8941_l2: l2 {};
1028                                         pm8941_l3: l3 {};
1029                                         pm8941_l4: l4 {};
1030                                         pm8941_l5: l5 {};
1031                                         pm8941_l6: l6 {};
1032                                         pm8941_l7: l7 {};
1033                                         pm8941_l8: l8 {};
1034                                         pm8941_l9: l9 {};
1035                                         pm8941_l10: l10 {};
1036                                         pm8941_l11: l11 {};
1037                                         pm8941_l12: l12 {};
1038                                         pm8941_l13: l13 {};
1039                                         pm8941_l14: l14 {};
1040                                         pm8941_l15: l15 {};
1041                                         pm8941_l16: l16 {};
1042                                         pm8941_l17: l17 {};
1043                                         pm8941_l18: l18 {};
1044                                         pm8941_l19: l19 {};
1045                                         pm8941_l20: l20 {};
1046                                         pm8941_l21: l21 {};
1047                                         pm8941_l22: l22 {};
1048                                         pm8941_l23: l23 {};
1049                                         pm8941_l24: l24 {};
1050
1051                                         pm8941_lvs1: lvs1 {};
1052                                         pm8941_lvs2: lvs2 {};
1053                                         pm8941_lvs3: lvs3 {};
1054
1055                                         pm8941_5vs1: 5vs1 {};
1056                                         pm8941_5vs2: 5vs2 {};
1057                                 };
1058                         };
1059                 };
1060         };
1061
1062         vreg_boost: vreg-boost {
1063                 compatible = "regulator-fixed";
1064
1065                 regulator-name = "vreg-boost";
1066                 regulator-min-microvolt = <3150000>;
1067                 regulator-max-microvolt = <3150000>;
1068
1069                 regulator-always-on;
1070                 regulator-boot-on;
1071
1072                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1073                 enable-active-high;
1074
1075                 pinctrl-names = "default";
1076                 pinctrl-0 = <&boost_bypass_n_pin>;
1077         };
1078         vreg_vph_pwr: vreg-vph-pwr {
1079                 compatible = "regulator-fixed";
1080                 regulator-name = "vph-pwr";
1081
1082                 regulator-min-microvolt = <3600000>;
1083                 regulator-max-microvolt = <3600000>;
1084
1085                 regulator-always-on;
1086         };
1087 };