arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 mpss@08000000 {
  18                         reg = <0x08000000 0x5100000>;
  19                         no-map;
  20                 };
  21
  22                 mba@00d100000 {
  23                         reg = <0x0d100000 0x100000>;
  24                         no-map;
  25                 };
  26
  27                 reserved@0d200000 {
  28                         reg = <0x0d200000 0xa00000>;
  29                         no-map;
  30                 };
  31
  32                 adsp@0dc00000 {
  33                         reg = <0x0dc00000 0x1900000>;
  34                         no-map;
  35                 };
  36
  37                 venus@0f500000 {
  38                         reg = <0x0f500000 0x500000>;
  39                         no-map;
  40                 };
  41
  42                 smem_region: smem@fa00000 {
  43                         reg = <0xfa00000 0x200000>;
  44                         no-map;
  45                 };
  46
  47                 tz@0fc00000 {
  48                         reg = <0x0fc00000 0x160000>;
  49                         no-map;
  50                 };
  51
  52                 efs@0fd600000 {
  53                         reg = <0x0fd60000 0x1a0000>;
  54                         no-map;
  55                 };
  56
  57                 unused@0ff00000 {
  58                         reg = <0x0ff00000 0x10100000>;
  59                         no-map;
  60                 };
  61         };
  62
  63         firmware {
  64                 compatible = "simple-bus";
  65
  66                 scm {
  67                         compatible = "qcom,scm";
  68                         clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>,
  69                                  <&gcc GCC_CE1_AHB_CLK>;
  70                         clock-names = "core", "bus", "iface";
  71                 };
  72         };
  73
  74         cpus {
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77                 interrupts = <1 9 0xf04>;
  78
  79                 cpu@0 {
  80                         compatible = "qcom,krait";
  81                         enable-method = "qcom,kpss-acc-v2";
  82                         device_type = "cpu";
  83                         reg = <0>;
  84                         next-level-cache = <&L2>;
  85                         qcom,acc = <&acc0>;
  86                         qcom,saw = <&saw0>;
  87                         cpu-idle-states = <&CPU_SPC>;
  88                 };
  89
  90                 cpu@1 {
  91                         compatible = "qcom,krait";
  92                         enable-method = "qcom,kpss-acc-v2";
  93                         device_type = "cpu";
  94                         reg = <1>;
  95                         next-level-cache = <&L2>;
  96                         qcom,acc = <&acc1>;
  97                         qcom,saw = <&saw1>;
  98                         cpu-idle-states = <&CPU_SPC>;
  99                 };
 100
 101                 cpu@2 {
 102                         compatible = "qcom,krait";
 103                         enable-method = "qcom,kpss-acc-v2";
 104                         device_type = "cpu";
 105                         reg = <2>;
 106                         next-level-cache = <&L2>;
 107                         qcom,acc = <&acc2>;
 108                         qcom,saw = <&saw2>;
 109                         cpu-idle-states = <&CPU_SPC>;
 110                 };
 111
 112                 cpu@3 {
 113                         compatible = "qcom,krait";
 114                         enable-method = "qcom,kpss-acc-v2";
 115                         device_type = "cpu";
 116                         reg = <3>;
 117                         next-level-cache = <&L2>;
 118                         qcom,acc = <&acc3>;
 119                         qcom,saw = <&saw3>;
 120                         cpu-idle-states = <&CPU_SPC>;
 121                 };
 122
 123                 L2: l2-cache {
 124                         compatible = "cache";
 125                         cache-level = <2>;
 126                         qcom,saw = <&saw_l2>;
 127                 };
 128
 129                 idle-states {
 130                         CPU_SPC: spc {
 131                                 compatible = "qcom,idle-state-spc",
 132                                                 "arm,idle-state";
 133                                 entry-latency-us = <150>;
 134                                 exit-latency-us = <200>;
 135                                 min-residency-us = <2000>;
 136                         };
 137                 };
 138         };
 139
 140         cpu-pmu {
 141                 compatible = "qcom,krait-pmu";
 142                 interrupts = <1 7 0xf04>;
 143         };
 144
 145         clocks {
 146                 xo_board {
 147                         compatible = "fixed-clock";
 148                         #clock-cells = <0>;
 149                         clock-frequency = <19200000>;
 150                 };
 151
 152                 sleep_clk {
 153                         compatible = "fixed-clock";
 154                         #clock-cells = <0>;
 155                         clock-frequency = <32768>;
 156                 };
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv7-timer";
 161                 interrupts = <1 2 0xf08>,
 162                              <1 3 0xf08>,
 163                              <1 4 0xf08>,
 164                              <1 1 0xf08>;
 165                 clock-frequency = <19200000>;
 166         };
 167
 168         smem {
 169                 compatible = "qcom,smem";
 170
 171                 memory-region = <&smem_region>;
 172                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 173
 174                 hwlocks = <&tcsr_mutex 3>;
 175         };
 176
 177         smp2p-wcnss {
 178                 compatible = "qcom,smp2p";
 179                 qcom,smem = <451>, <431>;
 180
 181                 interrupt-parent = <&intc>;
 182                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
 183
 184                 qcom,ipc = <&apcs 8 18>;
 185
 186                 qcom,local-pid = <0>;
 187                 qcom,remote-pid = <4>;
 188
 189                 wcnss_smp2p_out: master-kernel {
 190                         qcom,entry-name = "master-kernel";
 191
 192                         #qcom,state-cells = <1>;
 193                 };
 194
 195                 wcnss_smp2p_in: slave-kernel {
 196                         qcom,entry-name = "slave-kernel";
 197
 198                         interrupt-controller;
 199                         #interrupt-cells = <2>;
 200                 };
 201         };
 202
 203         smsm {
 204                 compatible = "qcom,smsm";
 205
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208
 209                 qcom,ipc-1 = <&apcs 8 13>;
 210                 qcom,ipc-2 = <&apcs 8 9>;
 211                 qcom,ipc-3 = <&apcs 8 19>;
 212
 213                 apps_smsm: apps@0 {
 214                         reg = <0>;
 215
 216                         #qcom,state-cells = <1>;
 217                 };
 218
 219                 modem_smsm: modem@1 {
 220                         reg = <1>;
 221                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
 222
 223                         interrupt-controller;
 224                         #interrupt-cells = <2>;
 225                 };
 226
 227                 adsp_smsm: adsp@2 {
 228                         reg = <2>;
 229                         interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
 230
 231                         interrupt-controller;
 232                         #interrupt-cells = <2>;
 233                 };
 234
 235                 wcnss_smsm: wcnss@7 {
 236                         reg = <7>;
 237                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
 238
 239                         interrupt-controller;
 240                         #interrupt-cells = <2>;
 241                 };
 242         };
 243
 244         soc: soc {
 245                 #address-cells = <1>;
 246                 #size-cells = <1>;
 247                 ranges;
 248                 compatible = "simple-bus";
 249
 250                 intc: interrupt-controller@f9000000 {
 251                         compatible = "qcom,msm-qgic2";
 252                         interrupt-controller;
 253                         #interrupt-cells = <3>;
 254                         reg = <0xf9000000 0x1000>,
 255                               <0xf9002000 0x1000>;
 256                 };
 257
 258                 apcs: syscon@f9011000 {
 259                         compatible = "syscon";
 260                         reg = <0xf9011000 0x1000>;
 261                 };
 262
 263                 timer@f9020000 {
 264                         #address-cells = <1>;
 265                         #size-cells = <1>;
 266                         ranges;
 267                         compatible = "arm,armv7-timer-mem";
 268                         reg = <0xf9020000 0x1000>;
 269                         clock-frequency = <19200000>;
 270
 271                         frame@f9021000 {
 272                                 frame-number = <0>;
 273                                 interrupts = <0 8 0x4>,
 274                                              <0 7 0x4>;
 275                                 reg = <0xf9021000 0x1000>,
 276                                       <0xf9022000 0x1000>;
 277                         };
 278
 279                         frame@f9023000 {
 280                                 frame-number = <1>;
 281                                 interrupts = <0 9 0x4>;
 282                                 reg = <0xf9023000 0x1000>;
 283                                 status = "disabled";
 284                         };
 285
 286                         frame@f9024000 {
 287                                 frame-number = <2>;
 288                                 interrupts = <0 10 0x4>;
 289                                 reg = <0xf9024000 0x1000>;
 290                                 status = "disabled";
 291                         };
 292
 293                         frame@f9025000 {
 294                                 frame-number = <3>;
 295                                 interrupts = <0 11 0x4>;
 296                                 reg = <0xf9025000 0x1000>;
 297                                 status = "disabled";
 298                         };
 299
 300                         frame@f9026000 {
 301                                 frame-number = <4>;
 302                                 interrupts = <0 12 0x4>;
 303                                 reg = <0xf9026000 0x1000>;
 304                                 status = "disabled";
 305                         };
 306
 307                         frame@f9027000 {
 308                                 frame-number = <5>;
 309                                 interrupts = <0 13 0x4>;
 310                                 reg = <0xf9027000 0x1000>;
 311                                 status = "disabled";
 312                         };
 313
 314                         frame@f9028000 {
 315                                 frame-number = <6>;
 316                                 interrupts = <0 14 0x4>;
 317                                 reg = <0xf9028000 0x1000>;
 318                                 status = "disabled";
 319                         };
 320                 };
 321
 322                 saw0: power-controller@f9089000 {
 323                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 324                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 325                 };
 326
 327                 saw1: power-controller@f9099000 {
 328                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 329                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 330                 };
 331
 332                 saw2: power-controller@f90a9000 {
 333                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 334                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 335                 };
 336
 337                 saw3: power-controller@f90b9000 {
 338                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 339                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 340                 };
 341
 342                 saw_l2: power-controller@f9012000 {
 343                         compatible = "qcom,saw2";
 344                         reg = <0xf9012000 0x1000>;
 345                         regulator;
 346                 };
 347
 348                 acc0: clock-controller@f9088000 {
 349                         compatible = "qcom,kpss-acc-v2";
 350                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 351                 };
 352
 353                 acc1: clock-controller@f9098000 {
 354                         compatible = "qcom,kpss-acc-v2";
 355                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 356                 };
 357
 358                 acc2: clock-controller@f90a8000 {
 359                         compatible = "qcom,kpss-acc-v2";
 360                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 361                 };
 362
 363                 acc3: clock-controller@f90b8000 {
 364                         compatible = "qcom,kpss-acc-v2";
 365                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 366                 };
 367
 368                 restart@fc4ab000 {
 369                         compatible = "qcom,pshold";
 370                         reg = <0xfc4ab000 0x4>;
 371                 };
 372
 373                 gcc: clock-controller@fc400000 {
 374                         compatible = "qcom,gcc-msm8974";
 375                         #clock-cells = <1>;
 376                         #reset-cells = <1>;
 377                         #power-domain-cells = <1>;
 378                         reg = <0xfc400000 0x4000>;
 379                 };
 380
 381                 tcsr_mutex_block: syscon@fd484000 {
 382                         compatible = "syscon";
 383                         reg = <0xfd484000 0x2000>;
 384                 };
 385
 386                 mmcc: clock-controller@fd8c0000 {
 387                         compatible = "qcom,mmcc-msm8974";
 388                         #clock-cells = <1>;
 389                         #reset-cells = <1>;
 390                         #power-domain-cells = <1>;
 391                         reg = <0xfd8c0000 0x6000>;
 392                 };
 393
 394                 tcsr_mutex: tcsr-mutex {
 395                         compatible = "qcom,tcsr-mutex";
 396                         syscon = <&tcsr_mutex_block 0 0x80>;
 397
 398                         #hwlock-cells = <1>;
 399                 };
 400
 401                 rpm_msg_ram: memory@fc428000 {
 402                         compatible = "qcom,rpm-msg-ram";
 403                         reg = <0xfc428000 0x4000>;
 404                 };
 405
 406                 blsp1_uart2: serial@f991e000 {
 407                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 408                         reg = <0xf991e000 0x1000>;
 409                         interrupts = <0 108 0x0>;
 410                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 411                         clock-names = "core", "iface";
 412                         status = "disabled";
 413                 };
 414
 415                 sdhci@f9824900 {
 416                         compatible = "qcom,sdhci-msm-v4";
 417                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 418                         reg-names = "hc_mem", "core_mem";
 419                         interrupts = <0 123 0>, <0 138 0>;
 420                         interrupt-names = "hc_irq", "pwr_irq";
 421                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 422                         clock-names = "core", "iface";
 423                         status = "disabled";
 424                 };
 425
 426                 sdhci@f98a4900 {
 427                         compatible = "qcom,sdhci-msm-v4";
 428                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 429                         reg-names = "hc_mem", "core_mem";
 430                         interrupts = <0 125 0>, <0 221 0>;
 431                         interrupt-names = "hc_irq", "pwr_irq";
 432                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 433                         clock-names = "core", "iface";
 434                         status = "disabled";
 435                 };
 436
 437                 rng@f9bff000 {
 438                         compatible = "qcom,prng";
 439                         reg = <0xf9bff000 0x200>;
 440                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 441                         clock-names = "core";
 442                 };
 443
 444                 msmgpio: pinctrl@fd510000 {
 445                         compatible = "qcom,msm8974-pinctrl";
 446                         reg = <0xfd510000 0x4000>;
 447                         gpio-controller;
 448                         #gpio-cells = <2>;
 449                         interrupt-controller;
 450                         #interrupt-cells = <2>;
 451                         interrupts = <0 208 0>;
 452                 };
 453
 454                 blsp_i2c8: i2c@f9964000 {
 455                         status = "disabled";
 456                         compatible = "qcom,i2c-qup-v2.1.1";
 457                         reg = <0xf9964000 0x1000>;
 458                         interrupts = <0 102 IRQ_TYPE_NONE>;
 459                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 460                         clock-names = "core", "iface";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                 };
 464
 465                 blsp_i2c11: i2c@f9967000 {
 466                         status = "disabled";
 467                         compatible = "qcom,i2c-qup-v2.1.1";
 468                         reg = <0xf9967000 0x1000>;
 469                         interrupts = <0 105 IRQ_TYPE_NONE>;
 470                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 471                         clock-names = "core", "iface";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 spmi_bus: spmi@fc4cf000 {
 477                         compatible = "qcom,spmi-pmic-arb";
 478                         reg-names = "core", "intr", "cnfg";
 479                         reg = <0xfc4cf000 0x1000>,
 480                               <0xfc4cb000 0x1000>,
 481                               <0xfc4ca000 0x1000>;
 482                         interrupt-names = "periph_irq";
 483                         interrupts = <0 190 0>;
 484                         qcom,ee = <0>;
 485                         qcom,channel = <0>;
 486                         #address-cells = <2>;
 487                         #size-cells = <0>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <4>;
 490                 };
 491         };
 492
 493         smd {
 494                 compatible = "qcom,smd";
 495
 496                 rpm {
 497                         interrupts = <0 168 1>;
 498                         qcom,ipc = <&apcs 8 0>;
 499                         qcom,smd-edge = <15>;
 500
 501                         rpm_requests {
 502                                 compatible = "qcom,rpm-msm8974";
 503                                 qcom,smd-channels = "rpm_requests";
 504
 505                                 pm8841-regulators {
 506                                         compatible = "qcom,rpm-pm8841-regulators";
 507
 508                                         pm8841_s1: s1 {};
 509                                         pm8841_s2: s2 {};
 510                                         pm8841_s3: s3 {};
 511                                         pm8841_s4: s4 {};
 512                                         pm8841_s5: s5 {};
 513                                         pm8841_s6: s6 {};
 514                                         pm8841_s7: s7 {};
 515                                         pm8841_s8: s8 {};
 516                                 };
 517
 518                                 pm8941-regulators {
 519                                         compatible = "qcom,rpm-pm8941-regulators";
 520
 521                                         pm8941_s1: s1 {};
 522                                         pm8941_s2: s2 {};
 523                                         pm8941_s3: s3 {};
 524                                         pm8941_5v: s4 {};
 525
 526                                         pm8941_l1: l1 {};
 527                                         pm8941_l2: l2 {};
 528                                         pm8941_l3: l3 {};
 529                                         pm8941_l4: l4 {};
 530                                         pm8941_l5: l5 {};
 531                                         pm8941_l6: l6 {};
 532                                         pm8941_l7: l7 {};
 533                                         pm8941_l8: l8 {};
 534                                         pm8941_l9: l9 {};
 535                                         pm8941_l10: l10 {};
 536                                         pm8941_l11: l11 {};
 537                                         pm8941_l12: l12 {};
 538                                         pm8941_l13: l13 {};
 539                                         pm8941_l14: l14 {};
 540                                         pm8941_l15: l15 {};
 541                                         pm8941_l16: l16 {};
 542                                         pm8941_l17: l17 {};
 543                                         pm8941_l18: l18 {};
 544                                         pm8941_l19: l19 {};
 545                                         pm8941_l20: l20 {};
 546                                         pm8941_l21: l21 {};
 547                                         pm8941_l22: l22 {};
 548                                         pm8941_l23: l23 {};
 549                                         pm8941_l24: l24 {};
 550
 551                                         pm8941_lvs1: lvs1 {};
 552                                         pm8941_lvs2: lvs2 {};
 553                                         pm8941_lvs3: lvs3 {};
 554
 555                                         pm8941_5vs1: 5vs1 {};
 556                                         pm8941_5vs2: 5vs2 {};
 557                                 };
 558                         };
 559                 };
 560         };
 561 };