3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include "skeleton.dtsi"
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
18 reg = <0x08000000 0x5100000>;
23 reg = <0x0d100000 0x100000>;
28 reg = <0x0d200000 0xa00000>;
33 reg = <0x0dc00000 0x1900000>;
38 reg = <0x0f500000 0x500000>;
42 smem_region: smem@fa00000 {
43 reg = <0xfa00000 0x200000>;
48 reg = <0x0fc00000 0x160000>;
53 reg = <0x0fd60000 0x1a0000>;
58 reg = <0x0ff00000 0x10100000>;
64 compatible = "simple-bus";
67 compatible = "qcom,scm";
68 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>,
69 <&gcc GCC_CE1_AHB_CLK>;
70 clock-names = "core", "bus", "iface";
77 interrupts = <1 9 0xf04>;
80 compatible = "qcom,krait";
81 enable-method = "qcom,kpss-acc-v2";
84 next-level-cache = <&L2>;
87 cpu-idle-states = <&CPU_SPC>;
91 compatible = "qcom,krait";
92 enable-method = "qcom,kpss-acc-v2";
95 next-level-cache = <&L2>;
98 cpu-idle-states = <&CPU_SPC>;
102 compatible = "qcom,krait";
103 enable-method = "qcom,kpss-acc-v2";
106 next-level-cache = <&L2>;
109 cpu-idle-states = <&CPU_SPC>;
113 compatible = "qcom,krait";
114 enable-method = "qcom,kpss-acc-v2";
117 next-level-cache = <&L2>;
120 cpu-idle-states = <&CPU_SPC>;
124 compatible = "cache";
126 qcom,saw = <&saw_l2>;
131 compatible = "qcom,idle-state-spc",
133 entry-latency-us = <150>;
134 exit-latency-us = <200>;
135 min-residency-us = <2000>;
141 compatible = "qcom,krait-pmu";
142 interrupts = <1 7 0xf04>;
147 compatible = "fixed-clock";
149 clock-frequency = <19200000>;
153 compatible = "fixed-clock";
155 clock-frequency = <32768>;
160 compatible = "arm,armv7-timer";
161 interrupts = <1 2 0xf08>,
165 clock-frequency = <19200000>;
169 compatible = "qcom,smem";
171 memory-region = <&smem_region>;
172 qcom,rpm-msg-ram = <&rpm_msg_ram>;
174 hwlocks = <&tcsr_mutex 3>;
178 compatible = "qcom,smp2p";
179 qcom,smem = <451>, <431>;
181 interrupt-parent = <&intc>;
182 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
184 qcom,ipc = <&apcs 8 18>;
186 qcom,local-pid = <0>;
187 qcom,remote-pid = <4>;
189 wcnss_smp2p_out: master-kernel {
190 qcom,entry-name = "master-kernel";
192 #qcom,state-cells = <1>;
195 wcnss_smp2p_in: slave-kernel {
196 qcom,entry-name = "slave-kernel";
198 interrupt-controller;
199 #interrupt-cells = <2>;
204 compatible = "qcom,smsm";
206 #address-cells = <1>;
209 qcom,ipc-1 = <&apcs 8 13>;
210 qcom,ipc-2 = <&apcs 8 9>;
211 qcom,ipc-3 = <&apcs 8 19>;
216 #qcom,state-cells = <1>;
219 modem_smsm: modem@1 {
221 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
229 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
235 wcnss_smsm: wcnss@7 {
237 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
245 #address-cells = <1>;
248 compatible = "simple-bus";
250 intc: interrupt-controller@f9000000 {
251 compatible = "qcom,msm-qgic2";
252 interrupt-controller;
253 #interrupt-cells = <3>;
254 reg = <0xf9000000 0x1000>,
258 apcs: syscon@f9011000 {
259 compatible = "syscon";
260 reg = <0xf9011000 0x1000>;
264 #address-cells = <1>;
267 compatible = "arm,armv7-timer-mem";
268 reg = <0xf9020000 0x1000>;
269 clock-frequency = <19200000>;
273 interrupts = <0 8 0x4>,
275 reg = <0xf9021000 0x1000>,
281 interrupts = <0 9 0x4>;
282 reg = <0xf9023000 0x1000>;
288 interrupts = <0 10 0x4>;
289 reg = <0xf9024000 0x1000>;
295 interrupts = <0 11 0x4>;
296 reg = <0xf9025000 0x1000>;
302 interrupts = <0 12 0x4>;
303 reg = <0xf9026000 0x1000>;
309 interrupts = <0 13 0x4>;
310 reg = <0xf9027000 0x1000>;
316 interrupts = <0 14 0x4>;
317 reg = <0xf9028000 0x1000>;
322 saw0: power-controller@f9089000 {
323 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
324 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
327 saw1: power-controller@f9099000 {
328 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
329 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
332 saw2: power-controller@f90a9000 {
333 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
334 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
337 saw3: power-controller@f90b9000 {
338 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
339 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
342 saw_l2: power-controller@f9012000 {
343 compatible = "qcom,saw2";
344 reg = <0xf9012000 0x1000>;
348 acc0: clock-controller@f9088000 {
349 compatible = "qcom,kpss-acc-v2";
350 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
353 acc1: clock-controller@f9098000 {
354 compatible = "qcom,kpss-acc-v2";
355 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
358 acc2: clock-controller@f90a8000 {
359 compatible = "qcom,kpss-acc-v2";
360 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
363 acc3: clock-controller@f90b8000 {
364 compatible = "qcom,kpss-acc-v2";
365 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
369 compatible = "qcom,pshold";
370 reg = <0xfc4ab000 0x4>;
373 gcc: clock-controller@fc400000 {
374 compatible = "qcom,gcc-msm8974";
377 #power-domain-cells = <1>;
378 reg = <0xfc400000 0x4000>;
381 tcsr_mutex_block: syscon@fd484000 {
382 compatible = "syscon";
383 reg = <0xfd484000 0x2000>;
386 mmcc: clock-controller@fd8c0000 {
387 compatible = "qcom,mmcc-msm8974";
390 #power-domain-cells = <1>;
391 reg = <0xfd8c0000 0x6000>;
394 tcsr_mutex: tcsr-mutex {
395 compatible = "qcom,tcsr-mutex";
396 syscon = <&tcsr_mutex_block 0 0x80>;
401 rpm_msg_ram: memory@fc428000 {
402 compatible = "qcom,rpm-msg-ram";
403 reg = <0xfc428000 0x4000>;
406 blsp1_uart2: serial@f991e000 {
407 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
408 reg = <0xf991e000 0x1000>;
409 interrupts = <0 108 0x0>;
410 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
411 clock-names = "core", "iface";
416 compatible = "qcom,sdhci-msm-v4";
417 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
418 reg-names = "hc_mem", "core_mem";
419 interrupts = <0 123 0>, <0 138 0>;
420 interrupt-names = "hc_irq", "pwr_irq";
421 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
422 clock-names = "core", "iface";
427 compatible = "qcom,sdhci-msm-v4";
428 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
429 reg-names = "hc_mem", "core_mem";
430 interrupts = <0 125 0>, <0 221 0>;
431 interrupt-names = "hc_irq", "pwr_irq";
432 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
433 clock-names = "core", "iface";
438 compatible = "qcom,prng";
439 reg = <0xf9bff000 0x200>;
440 clocks = <&gcc GCC_PRNG_AHB_CLK>;
441 clock-names = "core";
444 msmgpio: pinctrl@fd510000 {
445 compatible = "qcom,msm8974-pinctrl";
446 reg = <0xfd510000 0x4000>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 interrupts = <0 208 0>;
454 blsp_i2c8: i2c@f9964000 {
456 compatible = "qcom,i2c-qup-v2.1.1";
457 reg = <0xf9964000 0x1000>;
458 interrupts = <0 102 IRQ_TYPE_NONE>;
459 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
460 clock-names = "core", "iface";
461 #address-cells = <1>;
465 blsp_i2c11: i2c@f9967000 {
467 compatible = "qcom,i2c-qup-v2.1.1";
468 reg = <0xf9967000 0x1000>;
469 interrupts = <0 105 IRQ_TYPE_NONE>;
470 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
471 clock-names = "core", "iface";
472 #address-cells = <1>;
476 spmi_bus: spmi@fc4cf000 {
477 compatible = "qcom,spmi-pmic-arb";
478 reg-names = "core", "intr", "cnfg";
479 reg = <0xfc4cf000 0x1000>,
482 interrupt-names = "periph_irq";
483 interrupts = <0 190 0>;
486 #address-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <4>;
494 compatible = "qcom,smd";
497 interrupts = <0 168 1>;
498 qcom,ipc = <&apcs 8 0>;
499 qcom,smd-edge = <15>;
502 compatible = "qcom,rpm-msm8974";
503 qcom,smd-channels = "rpm_requests";
506 compatible = "qcom,rpm-pm8841-regulators";
519 compatible = "qcom,rpm-pm8941-regulators";
551 pm8941_lvs1: lvs1 {};
552 pm8941_lvs2: lvs2 {};
553 pm8941_lvs3: lvs3 {};
555 pm8941_5vs1: 5vs1 {};
556 pm8941_5vs2: 5vs2 {};